Hardware description language

• Describe hardware
– Functionality/behavior
– Delays and concurrency
• Why to model?
– Simulation and verification
• Before chip design: Functional & Timing
• After chip design: fault injection and diagnostic
– Synthesis
 HDL - options

• VHDL: Strongly typed, verbose, deterministic

• Verilog: Weakly typed, concise with efficient notations,
deterministic
• System Verilog: OOP, Verilog superset
• Other domain specific HDL
– Bluespec, Chisel, Handel-C, SystemC
 Verilog

• Module – basic unit

• Module definition
module module_name ( port_list );
port declaration;
…
variable declaration;
…
description of behavior
endmodule
 Half adder example

• Two inputs: A and B

A B Carry Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

• Sum = A XOR B
• Carry = A AND B
 Verilog example – structural model
Module Name

module half_adder ( A, B, Sum, Carry );

Primitives that can be used
input A, B; Port List and, or, xor,
output Sum, Carry; nand, nor, xnor
not
xor U1(Sum, A, B);
A Sum
// Sum = A XOR B;
Half
and U2(Carry, A, B); Adder
// Carry = A AND B B Carry

endmodule;
 Verilog example – dataflow model

module half_adder ( A, B, Sum, Carry );

input A, B;
output Sum, Carry;

assign Sum = A ^ B;
A Sum
// Sum = A XOR B;
Half
assign Carry = A & B; Adder
// Carry = A AND B B Carry

endmodule;
 Verilog Testbench Example
HA_TB
module HA_TB;
reg ra, rb;
wire wsum, wcarry; ra A Sum wsum
half_adder ha_inst(.A(ra), .B(rb), .Sum(wsum), .Carry(wcarry));
Half Adder
initial
begin rb B Carry wcarry
ra = 1’b0; rb = 1’b0;
#10
$display(“A: %b, B: %b, Sum: %b, Carry: %b”, ra, rb, wsum, wcarry)
ra = 1’b1; rb = 1’b0;
#10
Stimulus

$display(“A: %b, B: %b, Sum: %b, Carry: %b”, ra, rb, wsum, wcarry)
ra = 1’b0; rb = 1’b1;
#10
$display(“A: %b, B: %b, Sum: %b, Carry: %b”, ra, rb, wsum, wcarry)
ra = 1’b1; rb = 1’b1 ;
#10
$display(“A: %b, B: %b, Sum: %b, Carry: %b”, ra, rb, wsum, wcarry)
end
endmodule
 How to compile/run/simulate

• Commercial tools
– Mentor’s Modelsim/Questa
– Cadence Incisive
– Synopsys – VCS
– Xilinx Vivado
• Free
– icarcus (both Verilog and VHDL)
– GHDL (only for VHDL)
• Online platform
– edaplayground
 Viewing waveforms

• Free HDL simulator does not offer GUI and waveform

view
• Waveform need to explicitly dumped, see in waveform
viewer
initial
begin
$dumpfile(“ha_inst.vcd”)
$dumpvars;
end

C:\iverilog\bin>iverilog -o ckt.vvp Half_Adder.v HA_TB.v

C:\iverilog\bin>vvp ckt.vvp
C:\iverilog\bin>gtkwave ha_inst.vcd
 Logic optimization

• Input: Boolean expression

• Output: Optimal two level logic(either SOP or POS)
• Optimality criteria
– Minimum number of product/sum term
– Minimum number of literals in each product/sum term
 Area and Delay

• Area depends on number of inputs

• Delay
– Input / Fan-in
– Output / Fan-out
Tp = a1Fin + a2Fin2 + a3Fout
• Transistor size is usually modified for large fan-in gates
 Propagation delay

Delay of gate depends on

Input • Type of Gate
Output
• Input transition type (0->1 or
Tp 1->0)
Input • Output transition type
• Fan-in and Fan-out
Output

Time Maximum Gate delay can be

used for analysis
Propagation Delay
 Delay of two level logic

• For example: F = AB + AC + BC
Delay = Max delay stage 1 + Max delay stage 2
T1
Assume all inputs change at same time

Delay
T2

Input
T3
T

Variation in delay cause glitches at output

 Impact of large fan-in

Tp = a1Fin + a2Fin2 + a3Fout

Tp = 4a1 + 16a2 + a3

Tp = 2(2a1 + 4a2 + a3)

For large N, square term dominate

• Conversion to Multi-level is required to minimize delays
 Delay in multiple level logic

• Longest path from input to output

Critical Path

A n1
B n2
C
Y
D

Short Path
 Delays in Verilog

• Structure modeling
– and #5 a1(out, i1, i2); //fixed delay
– and #(4, 6) a1(out, i1, i2); // (rise time, fall time)
– and #(4, 6, 8) a1(out, i1, i2); // (rise time, fall
time, switch off time)
– No delay means zero delay
• Dataflow modeling
– assign #10 out = in1 & in2;
– wire #10 out;