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Low-power circuits using dynamic threshold devices

Conference Paper · January 2005

DOI: 10.1145/1057661.1057713 · Source: DBLP

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 Low-Power Circuits using Dynamic Threshold Devices
Paul Beckett
Electrical & Computer Engineering
RMIT University
+613 99255301
pbeckett@rmit.edu.au
ABSTRACT
We present simulations for ultra-thin body, fully-depleted,
double-gate (DG) silicon-on-insulator (SOI) devices that can be
readily optimized for both static power loss and performance by
dynamically shifting the threshold voltage during operation. A
small number of simple circuits are analyzed and it is
demonstrated that subthreshold power can be reduced by a factor
in excess of 103 for these examples.
Categories and Subject Descriptors
B.7.1 [INTEGRATED CIRCUITS] Types and Design Styles –
Advanced technologies, VLSI.
General Terms
Design.
Keywords
Subthreshold leakage, double-gate, thin-body, SOI, silicide,
CMOS, nanotechnology.
1. INTRODUCTION
Balancing the needs of low power and high performance in future
nanoscale systems will be a difficult optimization problem that
will have to be addressed at a number of levels [1], [2]. For
example, the analysis in [3] shows that hitting the 2016 ITRS
targets for high-performance logic would require threshold
voltages to be controlled to within 0.1V. This will be increasingly
difficult to achieve as channel lengths scale below 50nm due to
physical effects such as random dopant fluctuation, surface
roughness and variability in device dimensions along with
electrical effects such as charge sharing and DIBL.
Ultimately, of course, it will be decisions about supply and
threshold voltages that will determine both the dynamic and sub-
threshold power loss in a system - as well as its operating
frequency. For example, as the supply voltage is reduced, thereby
saving dynamic power, it will become increasingly difficult to
find a fixed threshold voltage that optimizes both delay and static
power, especially given a likely increase in process variability.
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GLSVLSI’05, April 17–19, 2005, Chicago, Illinois, USA.
Copyright ACM 1-59593-057-4/05/0004...$5.00.
One solution is to allow VTH to vary, thereby changing the
optimization problem into one of setting an appropriate threshold
in a particular part of the system or during a particular part of its
operating cycle. There have already been a number of proposals
(e.g. [7, 8]) that exploit the shifts in threshold voltage that can be
produced by modulating the back-gate bias in double-gate
devices. Their common objective is to allow subthreshold power
and delay to be optimized separately, thereby reducing the need to
carefully manage the threshold voltage and subthreshold slope in
order to achieve a particular power-delay design point.
This paper focuses on the application of thin-body (TB), fully-
depleted (FD) double-gate (DG) silicon-on-insulator (SOI)
devices. These are likely to become a preferred nanoscale circuit
element due to their potentially superior sub-threshold
performance and better control of short-channel effects. By
simulation it is shown that, as the channel thickness reduces to the
order of 5nm, the effect of the back gate bias increases to a point
where threshold shifts of greater than 400mV are possible with
±1V back gate bias changes.
The remainder of the paper proceeds as follows. In Section 2 we
present the results of simulations performed on TBFD-DGSOI
devices with fully silicided source and drain regions showing the
scale of the threshold shifts possible with this technology as the
channel thickness reduces. In Section 3 we present SPICE results
for circuits based on these devices demonstrating how power and
delay can be separately optimized. In Section 4 we conclude and
briefly look at one potential application of the technique.
2. THIN BODY SILICIDE DEVICES
The increased difficulty in maintaining low IOFF as channel lengths
scale down below 50nm has resulted in a revival of interest in
Schottky barrier MOSFETs (first described more than 30 years
ago [9]), in which metal silicides (e.g. PtSi, ErSi etc.) replace the
heavily doped silicon source and drain regions [10, 11]. Metal
silicides form natural Schottky barriers to silicon substrates,
acting to confine carriers and reducing or eliminating the need for
impurities in the channel to prevent current flow in the "off"
condition [12]. Compared with conventional devices these
exhibit several advantages, including the elimination of punch-
through and latch-up. As well as offering a significantly simpler
processing technology, they may also be more compact and
scalable than conventional CMOS due to the elimination of the
well(s), body contacts and isolation regions. At the ultimate
dimensions for this technology (e.g. lengths in the order of 10nm),
the channels would effectively become undoped silicon wires with
regular silicide patterns forming the source/drain regions. At this
scale it may be possible to approach densities of 108 gates/mm2.
However, this comes at a cost - the overall current drive of
Schottky barrier devices can be significantly lower than MOS due
to the very high resistance of their source/drain regions at low
supply voltages [13]. The resultant loss in performance (implied
by an increased τ=CV/I) would have to be made up at the
architectural level.
Sidewall
GF
Gate Oxide SiO2
Oxide
TOXF = TOXB = 1.5nm
ErSi1.7 ErSi1.7
S D
Self-aligned erSi S/D
φBN =0.28
Si channel GB
Metal gates:
TSI = 5-30nm
ψ =variable
ND = 1015 cm-3
LGATE = 4 x TSI
Figure 1. Simplified view of a n-type thin body, fully-
depleted double-gate silicide transistor with undoped
channel. The p-type uses PtSi source/drain.
Figure 2. Threshold voltage change (∆ ∆VTH) vs. back gate
voltage at various tSI for the n-type device of Figure 1.
P-type device characteristics are similar.
Figure 3. TCAD simulated log(ID) vs VFG (n-type) for
various body thickness values (tSI). ID has been normalized
to its value at VFG=1V, showing the relative effect on IOFF
achieved with a –1V shift in VBG. VDD=1V, and the initial
threshold voltage for each curve (at VBG=0) has been set to
approximately 0.2V.
Thin-body double-gate p and n-type silicide S/D devices of the
general form shown in Figure 1 were analyzed with a commercial
TCAD simulator1 using classical drift-diffusion models. These
models have been shown to be sufficiently accurate to around
tSI=5nm, the limit of this work [14]. The devices have uniform,
lightly doped channels (ND = 1015 cm-3) with source/ drain regions
1
Atlas/SPisces - Silvaco Inc.
of ErSi1.7 (n-type: barrier height φBN = 0.28eV above Si) and PtSi.
(p-type: φBP = 0.23eV). The gate work function (ψ) was adjusted to
give the desired threshold voltage VBG=0. The gate length was set at
4xtSI, to maintain good gate control and to reduce short channel
effects that would unnecessarily complicate the analysis.
Figure 2 illustrates the sensitivity of the threshold voltage (as seen at
the front gate) to the back gate bias with various values of channel
thickness (tSI) between 5nm and 30nm. These plots are for the n-
type transistor; those for the p-type have a similar form. In Figure 2
the threshold values have been normalized such that ∆VTH=0 at
VBG=0. It can be seen that as the channel thickness is reduced the
threshold sensitivity increases to a point where at tSI=5nm, setting
VBG = -1V can produce ~0.45V shift in threshold voltage. A shift of
similar magnitude is observed for the p-type device at VBG=VDD+1.
While it is theoretically possible for DG-SOI transistors to approach
the ideal subthreshold slope for MOS (~60mv/decade) when used in
double gate mode (both gates driven together), no device fabricated
to date has even approached this figure. In the ground-plane mode,
the behavior of S is similar to that of planar devices and is given by
[15]:
kT  C  (1)
S= ln(10)1 + S 
q  C OXF 
where: COXF = the front gate oxide capacitance ≈ εOX/TOXF and CS is
the effective body capacitance between the inversion layer and the
back gate: CS ≈ εSI/tSI if the back surface is in accumulation, and CS
= CSICOXB/(CSI+COXB) in depletion. Substituting εSI ≈ krεOX, (kr =
εSI/εOX ≈ 3 for SiO2 dielectric), the subthreshold slope becomes:
 k r TOXF  (2)
S ≈ 601 +  mv/decade.
 k T
r OXB + TSI 
The term krTOXB becomes zero if the back surface is in
accumulation.
While reducing the body thickness increases the threshold
sensitivity (∂VTH/∂VBG), Equation (2) implies that it also degrades
the subthreshold slope. To maintain S<100mV/decade at tSI=5nm
would require the effective oxide thickness to be less than 1nm,
something that would be extremely difficult to manufacture and
likely to lead to high gate tunneling currents and oxide reliability
problems. Typical values of subthreshold slope observed in devices
fabricated to date (e.g. [16]) range between 100 and 150mV/decade
(i.e. CS/COX between 0.6 and 1.5). It is suggested in [14] that this
restricts the VTH tuning range (e.g. to |VBG|<0.25 in that study).
However, it appears from our work that useful subthreshold leakage
reductions can still occur well outside this range for tSI ≥ 5nm.
Although the sensitivity of the subthreshold shift to back-gate bias
(∂VTH/∂VBG) increases monotonically with reducing tSI, the
interaction between ∂S/∂VBG and ∂VTH/∂VBG results in the
minimum absolute subthreshold current being achieved at tSI =
10nm. Equation 2 also implies that moving to hi-k gate dielectrics
(as well as serving to reduce gate leakage) can significantly improve
S in this case. For example, using HfSiO4 (εr > 12), kr will become
less than 1.0 and the worse-case slope (i.e. in accumulation) will
reduce to approximately 78mV/decade, although it is likely that this
will be at the expense of reduced channel mobility and increased
short channel effects [17].
3. LOW-POWER VARIABLE THRESHOLD at 0V back-gate bias (the devices are symmetrical). The first two
groups are based on the supply and threshold targets for the ITRS
CIRCUITS high-performance and low-operating power technologies from 2010
The TCAD results for the p and n-type devices with tSI=5nm were through 2018. Using a ±1V shift in back gate bias achieves an
used to approximately calibrate University of Florida physically approximate shift in threshold of 0.45V (relative to the values listed
based (level 10) FDSOI SPICE models which were then used in in the table). As a result, IOFF is reduced by typically in excess of
circuits with the general form shown in Figure 4. The simulated 5x103 in these examples. Where VDD<0.6V, the magnitude of the
ID vs. VG for both p and n-type devices with tSI=5nm and threshold voltage becomes greater than the supply, so that the circuit
TOX=1.5nm is shown in Figure 5. It can be seen that by shifting would operating entirely in subthreshold mode. In the next section
the bias on the back gate (VBG) by 1 volt above VDD or below we suggest a way of using these devices that will avoid the
ground, the value of IOFF (ID at VGF=0) can be reduced by a factor performance costs associated with subthreshold operation.
of more than 104 (with an accompanying impact on drive current).
This is illustrated in Figure 6 for a basic inverter (long channel –
L=0.33µm, WN = 1.0µm; WP = 2.0µm; VDD=1.0, VTH≈0.3; FO-4).
In this example, ratio of IOFF between the two modes is more than
5x104. At the same time, the average FO-4 delay –
TP=(TPLH+TPHL)/2 - increases by a factor of almost five. Whereas
the standby current in this case is an order of magnitude below the
ITRS 2018 target for low standby power technology (at
VTH=0.4V), the nominal saturation drive current of these silicide
S/D devices is 11 times lower (~90µA/µm vs. 990µA/µm),
implying that the FO-4 delay will be at least an order of
magnitude greater than the ITRS target. Mode IOFF (A/µm) TP (pS)
High speed 5 x10-7 100
Low power 1.1 x 10-11 490
LSTP 2018 target 1 x 10-10 10pS
Mode VGB(p) VGB(n)
Figure 6. Basic inverter characteristics (FO-4): Curve 1 =
High 1V 0V
speed high-speed mode; curve 2 = low-power mode. Also
shown are the average IOFF and average FO-4
Low +2V -1V propagation delays for both modes. The ITRS 2018
power
low standby power and delay targets for a single
nMOS device are included for comparison.
Table 1. Subthreshold leakage power vs. supply voltage for
Figure 4. The general form of the CMOS transistor stack a conventional 1-bit CMOS full-adder circuit under various
with threshold shift. threshold scaling regimes; tSI=5nm; ∆VBG=±
±1V.
Scaling POFF (µW) POFF (nW) Power
VDD VTH (speed) (power) Ratio
ITRS 1.0 0.15 28 5.5 5.5x103
HP 0.8 0.14 22 1.6 1.3 x103
logic 0.7 0.13 8.75 3.0 2.8 x103
ITRS 0.7 0.22 6.4 0.5 1.3x104
LOP 0.6 0.19 7.8 1.0 7.8x103
0.5 0.17 7.0 1.0 7.0x103
Fixed 1.0 0.2 17 1.8 9.4x103
VTH 0.8 0.2 9.5 1.1 8.9 x103
0.7 0.2 8.5 0.9 9.3 x103

Figure 5. SPICE simulated ID vs. VGS characteristics for p
and n-type double gate silicide S/D devices - |VTH|≈≈0.3;
tSI=5nm; W/L=3. Low-power mode (open triangles)
VDD=1; VBGP=2, VBGN=-1; High speed mode (filled
diamonds) VBGP=1, VBGN=0. Data from fabricated p-type
silicide devices reported in [18] and n-type from [19] are
included for comparison (open circles).
Table 1 shows the results for a more complex circuit – a
conventional CMOS full-adder made up of 28 transistors (14 each
of p and n type), which was analysed over a range of supply and
threshold values. The threshold values shown here are for the nFET
4. CONCLUSIONS
We have shown that the threshold voltage in ultra-thin-body, fully-
depleted, double-gate (DG) silicon-on-insulator (SOI) transistor
circuits becomes increasingly sensitive to back-gate bias as the
channel thickness is reduced. However, this comes at the cost of
poorer subthreshold slope. The effect can be used to reduce the
standby power of a circuit by dynamically shifting the threshold
during operation. As the back gate of a double gate transistor
presents approximately the same load as the front gate, such mode-
switching can achieved at normal circuit speeds. Simulations of a
small number of simple circuits indicate that the technique can
reduce subthreshold leakage power by a factor in excess of 103 in
typical circuits regardless of its impact on subthreshold slope.
 As operation close to or within the subthreshold region will result in
extremely poor performance, we would ideally set the active
threshold values for just those parts of the system that are operating
at any particular time. Thus the technique would be especially
applicable to architectures such as asynchronous spatial computing
[20] in which run-time circuit activity can be easily detected. In
spatial computing, applications written in high-level languages are
compiled directly into hardware circuits that exhibit only localized
communication and require no global control, such as a master
clock. Data flow between operators is controlled by handshaking
and it is therefore straightforward to determine when a particular
part of the system is active at a given time and to set the appropriate
power mode (Figure 7). In future work, we will examine both the
dynamic and static power behavior of these circuits as well as the
power/performance tradeoffs for more complex asynchronous
circuits compiled directly from high level language.
Handshake
Rdy (i-1) C Nanoelectronics," Proc. Advanced Workshop on Frontiers in
Level shift/bias
generator
Completion
Logic /Latch
Data In Stage Logic
Delay
Ackn(i)
Figure 7. A conventional asynchronous computing stage
with added level-shift/back gate bias generator.
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