Multiple Through-Wafer Interconnects For MEMS Applications

1.
2 Multiple Through-wafer Interconnects

for MEMS Applications
M. Heschel, Technical University of Denmark, Lyngby,

Denmark
J. F. Kuhmann, HYMITE ApS, Lyngby,
Denmark
S. Bouwstra, Microcosm Technologies BV, Amsterdam,
The Netherlands
Abstract
This chapter reports on the design and manufacturing of multiple

through-wafer interconnects for stacking of microelectromechanical
devices. The feedthroughs have been applied to an interconnect (inter-
mediate) layer for an integrated microphone. The integrated micro-
phone consists of the transducer part and an application specific inte-
grated circuit (ASIC). The two parts are joined by stacking them on top
of each other with the interconnect (intermediate) layer between them.
The intermediate layer is a multifunctional layer. It provides the micro-
phone with an acoustic frontchamber. The intermediate layer ensures
the interchange of acoustical and electrical signals with the environ-
ment. Also, the intermediate layer protects the microphone during dic-
ing, chip handling and in operation. The two active components are
electrically connected through the intermediate layer by multiple wafer
frontside to backside interconnects. The feedthrough interconnects are
provided with under bump metallizations (UBM), solder bumps and
sealing rings on the microphone side and top surface metallizations
(TSM) on the ASIC side. The entire metallization system is based on
electroplating techniques. The patterning of the metallizations has been
done utilizing an electrodepositable photoresist (EDPR) as a plating
mold. Several EDPR processes have been developed which are opti-
mized for the respective metallization. The feedthrough interconnects
have been optimized in terms of series resistance and parallel capaci-
tance. Electrical characterization of the feedthrough interconnects has
been carried out analytically and experimentally. The series resistance
of one single interconnect wire is in the order of 100 mX. The parallel
(parasitic) capacitance is in the order of 2 pF. Coupling between two
adjacent feedthrough interconnects is negligible for low relative humid-
22 1.2 Multiple Through-wafer Interconnects for MEMS Applications
ity (<50%). For high relative humidity (>90%) the impedance between
two wires may be reduced due to a condensed water film. Sensitivity
measurements performed before and after bonding of the interconnect
layer to the microphone showed identical results which proves suffi-
cient (TX) isolation between the feedthrough wires.
Keywords: Feedthroughs; Through-wafer interconnects; Stacking; In-

tegrated microphone; Electrodepositable photoresist
Contents
1.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.2.2 Wafer Feedthrough Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.2.2.1 Backside Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.2.2.2 Single Feedthroughs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.2.2.3 Multiple Feedthroughs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.2.2.4 Buried Feedthroughs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.2.2.5 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.2.3 Stacking Approach for an Integrated Microphone . . . . . . . . . . . . . . . . 28

1.2.3.1 Topology Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.2.3.2 Intermediate Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.2.3.3 Interconnect Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.2.3.3.1 Solder Bump Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.2.3.3.2 Through-wafer Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.2.3.3.3 Conductive Adhesive Bonding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.2.4 Intermediate Layer – Technical Aspects . . . . . . . . . . . . . . . . . . . . . . 34

1.2.4.1 Bulk Micromachining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.2.4.2 Bulk Contact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1.2.4.3 Eagle 2100 ED Electrodepositable Photoresist . . . . . . . . . . . . . . . . . . 37
1.2.4.3.1 Deposition Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1.2.4.3.2 Baking Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1.2.4.4 Lithography on (111) Sidewalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.2.4.4.1 Light Reflections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
1.2.4.4.2 Mask-Resist Distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.2.4.4.3 Relative Resist Thickness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.2.4.5 Thin-film Feedthroughs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
1.2.4.5.1 Etching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
1.2.4.5.2 Lift-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
1.2.5 Electroplated Through-wafer Interconnects . . . . . . . . . . . . . . . . . . . . 46

1.2.5.1 Metalization Scheme and Processing . . . . . . . . . . . . . . . . . . . . . . . . 46
A1.2.1 Introduction 23
1.2.5.2 Electroplating Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

1.2.5.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
1.2.5.4 Electrical Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1.2.5.4.1 Interconnect Wire Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1.2.5.4.2 Series Resistance Rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
1.2.5.4.3 Parasitic Capacitance Cp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
1.2.5.4.4 Self-inductance Ls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
1.2.5.4.5 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
1.2.5.4.6 Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
1.2.6 Summary and Future Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
1.2.7 Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
1.2.8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
1.2.1 Introduction
By most of the MEMS community, it is realized that packaging of microelectro-

mechanical systems (MEMS) or devices (transducers) is as important as manufac-
turing the MEMS or transducer itself. It is also realized that a substantial part of
the packaging should be integrated rather than added on. This statement may
sound simple but it puts a lot of constraints on the device design and process de-
velopment. Often, compromises in device performance have to be made in order
to meet packaging demands. Key issues to be addressed include hermeticity,
shielding, protective coatings, use of biocompatible materials, electrical intercon-
nections and subsequent integration. Often, the active side of the transducer is di-
rectly facing the environment. In most of these cases, electrical contacts have to
be made from the topside of the device to the substrate on which the device is
mounted.
Additionally, MEMS packaging is usually application-specific packaging,
which means that every single application requires its own packaging concept.
Therefore, it should be the goal of the MEMS community to establish a packag-
ing toolbox consisting of simple and versatile processes. In practice, the develop-
ment of each tool in the box is driven by a specific application.
This chapter describes multiple through-wafer interconnects. This addition to
the MEMS packaging toolbox has been developed specifically to meet the re-
quirements of an integrated microphone for hearing aids [1]. The integrated mi-
crophone consists of the actual microphone and an application-specific integrated
circuit (ASIC) for signal conditioning. Figure 1.2-1 shows an exploded view of
the integrated microphone (a) and a final system mounted on a test socket (b).
The market for hearing aid instruments shows a clear trend towards further device
miniaturization, simultaneously reducing costs and improving performance and
Figure 1.2-1. Integrated microphone for hearing aid applications. (a) Exploded view (with
permission); (b) stacked system mounted on test socket (courtesy of Microtronic).
manufacturability. The space constraints require the size of the individual compo-
nents and that of the whole instrument to be small. Therefore, the integration con-
cept we pursue is based on stacking technologies with the through-wafer intercon-
nects playing a key role.
Through-wafer interconnects are useful also for other MEMS applications, or
even semiconductor technology applications in general, and, consequently, are at-
tracting more and more attention. Some basic approaches are described in Sec-
tion 1.2.2. Section 1.2.3 outlines the stacking concept and introduces the intercon-
nect (intermediate) layer as an essential part of it. The interconnect layer is de-
scribed in more detail in Section 1.2.4, focusing on electrodepositable photoresist
as the core technology. Section 1.2.5 discusses electroplated feedthroughs and
their electrical characterization. Finally, Section 1.2.6 summarizes this chapter and
discusses the future outlook.
A more detailed description of the work presented here can be found in [2].
1.2.2 Wafer Feedthrough Technologies
Electrical wafer feedthroughs are required for topologies with multiple chips
stacked on top of each other or, simply, for components where backside contacts
are required. The through-holes can be realized in two ways: straight vertical
holes, either by laser processing or (deep) reactive ion etching (DRIE), or holes
with sloped sidewalls using crystalorientation-dependent etching of (100) silicon.
In the following we refer to them as dry etched and wet etched holes, respec-
A1.2.2 Wafer Feedthrough Technologies 25
tively. Dry etched holes occupy much less surface area per hole. On the other
hand, they do not allow for patterning of the metalization inside the hole (it is
possible with synchrotron x-ray radiation to reach a depth of field according to
wafer thickness). Wet etching results in some dead area on the wafer surface. The
amount of additional area depends on the wafer thickness. Here, direct or indirect
writing is possible because of the sloping sidewalls. The type of through-hole also
determines, to some extent, the deposition technique for the interconnect metaliza-
tion. Standard techniques are e-beam evaporation, sputtering, and electroless plat-
ing. All three could be followed by electroplating to obtain thicker layers. An al-
ternative could be highly doped low-pressure chemical vapor deposition (LPCVD)
polysilicon, or CVD metals (Cu, W, Al).
All the mentioned techniques can be used for wet etched holes. For dry etched
holes the number of techniques is limited. Evaporation fails because of its inabil-
ity to cover the inside of the hole. For sputtering the aspect ratio of height to
width of the hole that can be covered is limited. If it exceeds six the sputtered
layer becomes discontinuous deep inside the hole, even for double-sided sputter-
ing [3]. Electroless plating could cover any surface but requires a proper starting
layer. To overcome the problem of high aspect ratios, CVD of metals can be ap-
plied. Especially Cu could serve as a plating base for subsequent electroplating.
CVD metals often require a nucleation layer, eg, TiN, which is deposited first [4].
1.2.2.1 Backside Contacts
Backside contacts are extensively used in chemical sensors where the sensing ele-
ment has to be exposed to the (often harsh) environment, whereas the other parts,
such as interface circuitry, have to be hermetically encapsulated and protected
from the environment. In principle, a membrane (silicon plus deposited layers) is
used to separate frontside and backside. Electrical contact is made by heavily
doped areas in this membrane. Some work has been presented on backside con-
tacting of ISFET sensors [5–8]. Although slightly different in processing, they all
rely on anisotropically wet etched holes and highly doped connections to drain
and source contacts. The micromachining of the wafers is performed prior to IS-
FET processing, which puts constraints on the wafer handling during subsequent
processing. Doping of the remaining bulk silicon is done by ion implantation
from both sides, followed by diffusion. The ion species for doping must be the
opposite of the substrate in order to get insulated contacts. Finally, metal is depos-
ited, structured, and heat treated to form ohmic contacts.
Although containing only one electrical interconnection per through-hole, the
presented technologies for backside contacting of chemically sensitive devices are
the optimum solution for the applications given here. Only standard silicon pro-
cesses are used, providing full integration of the feedthrough fabrication into the
device processing. No problems with reduced mechanical stability due to the an-
isotropically etched pits were reported, provided that the wafer was handled prop-
erly. On the other hand, the introduced p-n junctions can cause leakage currents,
which could interfere with the measured signals. In such a case an oxide layer
should be used as an insulation layer between the bulk and the contact.
1.2.2.2 Single Feedthroughs
Single feedthroughs were realized using both dry and wet etched through-holes.
Linder [9] presented single feedthroughs in wet etched holes which were designed
for signal (patterned metalization) and power lines (fully metalized). The technol-
ogy for both types is based on electroplating of gold into a mold of polyimide
[10, 11] or electrodepositable photoresist [12].
A thin film through-wafer interconnect for wafer to wafer bonding was pre-
sented by Wolffenbuttel and Wise [13]. The bonding technology used is eutectic
Au-Si bonding, a standard technique used for silicon die bonding. The through-
holes are wet etched. The bottom wafer has a metalization pattern facing the
through-hole opening. After eutectic bonding, the final feedthrough interconnects
are made by metal evaporation into the etch pits.
Others filled wet etched through-holes completely with electroplated metals
[14, 15] or conductive adhesive [16].
Ramm et al. [17] presented the so-called interchip via concept, which is based
on dry etched cavities by reactive ion etching (RIE). These cavities are as deep as
14 lm and have an aspect ratio of 5–10. The wafers are subsequently thinned
down to open the interchip vias from the rear. After bonding the thinned wafer on
top of the second wafer to be stacked, the vias are filled by CVD-TiN and CVD-
W. The great advantage of this technology is the extremely small hole size, which
gives an interconnect density of some 100 000 feedthroughs per cm2 .
Alizadeh-Taheri et al. [18] presented feedthroughs in dry etched holes with a
somewhat larger opening. The holes are etched using RIE in a SF6 -O2 plasma.
The openings of the through-holes are about 200 lm for a wafer thickness of
about 500 lm. After oxidation the vias are coated with sputtered Al.
1.2.2.3 Multiple Feedthroughs
The major challenge in realizing multiple feedthroughs per through-hole is the

patterning of the interconnect metalization. The through-holes can be regarded as
a highly structured surface where standard resist deposition techniques fail. There
are mainly two ways to overcome this problem: evaporation through a shadow
mask and electrodepositable photoresists (EDPR). Alternatively, for prototyping
laser etching technique can be used [19].
Burger et al. [20] used the first technique, evaporation through a shadow mask,
to realize multiple through-wafer interconnects. The shadow mask was fabricated
in silicon using standard micromachining processes. The shadow mask and
through-hole wafer are bonded together using a thin photoresist layer. After pro-
A1.2.2 Wafer Feedthrough Technologies 27
cessing, the two wafers can easily be separated again in an oxygen plasma. Alu-
minum is evaporated using different source sizes. It turned out that the source
size determines the steepness of the deposited aluminum lines, a small metal
source results in a very sharp line edge whereas a large source gives very sloped
sidewalls and broadened line widths. The resolution obtained with a mask was
10 lm for a wafer separation of 380 lm, but a minimum line width of 5 lm was
reported to be achievable. A critical issue addressed by the authors is the shift of
pattern due to rotation of the wafer in regard to the metal source. A rotation angle
of only 1 8 results in a pattern shift of 10 lm. An enlargement of the metal pattern
compared with the mask dimensions is unavoidable because of the difference in
sizes (metal source to mask/wafer). However, this enlargement can be determined
analytically and implemented in the mask design. The feedthrough structures are
not processed completely through the wafer but stop at a thin silicon nitride mem-
brane. The final feedthroughs are made by surface processing the backside of the
wafer.
Christensen et al. [21] used the second way discussed above, EDPR. The
EDPR used was a Shipley EAGLE 2100 ED/PR. Wet etching forms the through-
holes, followed by thermal oxidation and double-sided e-beam evaporation of the
seed layer. The seed layer for the resist deposition also serves as interconnect me-
talization. The EDPR is deposited and patterned on both sides using standard dou-
ble-sided exposure tools. Then, the resist is used as an etch mask to structure the
interconnect metalization. The minimum line width achieved is 30 lm. Going
further down reflections from the opposite sidewall lead to short-circuits in the
through-hole bottom.
1.2.2.4 Buried Feedthroughs
Buried feedthroughs are undoubtedly the most elegant way to make frontside to
backside interconnections. They do not require any through-hole processing. The
feedthrough processing relies on thermomigration of aluminum droplets through
the silicon wafer [22–27]. To obtain insulated interconnects n-type silicon must be
used. After evaporation of the aluminum droplets on to the frontside, the wafer is
heated to approximately 1000 8C and maintained at this temperature. Additionally,
a temperature gradient is applied (150 8C/cm) with the rear side of the wafer
being the hotter one. The temperature gradient causes a concentration gradient of
dissolved silicon in the aluminum droplet and, thus, a net movement of silicon to-
wards the wafer frontside. Silicon at the aluminum propagation front dissolves
and recrystallizes at the droplet rear. Aluminum is incorporated during recrystalli-
zation, yielding highly doped through-wafer vias. The concentration of Al and Si
in the trail is that of eutectic AlSi (88.8 at% Al, 12.2 at% Si). General challenges
concerning the thermomigration process include non-uniform temperature distribu-
tion and defects in silicon.
1.2.2.5 Comparison
From our point of view, important parameters of the feedthrough interconnects de-
scribed above are summarized in Table 1.2-1. For backside contacts neither series
resistance nor parasitic capacitance are of any importance. Moderate values of the
resistance can easily be achieved with thin, evaporated metal layers. The capaci-
tance is given by the size of the through-hole and the p-n junction. The size of
the through-hole also determines the parasitic capacitance for single, unstructured
feedthroughs. The series resistance depends on the interconnect metalization. The
parasitic capacitance is significantly reduced for multiple feedthroughs. On the
other hand, the series resistance is higher. This, however, is also caused by the
thin, e-beam evaporated metalizations of the two approaches presented here. Feed-
throughs realized by thermomigration of Al show moderate parasitic capacitances.
The relatively high resistances are due to the large wafer thickness and the rela-
tively high resistivity of AlSi. The spatial density of feedthrough interconnects is
shown in Table 1.2-2. We considered only those publications in which the number
of feedthroughs per area is an issue. In addition to the substrate thickness, the
feedthrough density also depends on the via width/diameter. Each of the presented
approaches uses a different technology which has been optimized for a specific
application. The last column in Table 1.2-2 shows feedthrough densities normal-
ized to a wafer thickness of 350 lm.
1.2.3 Stacking Approach for an Integrated Microphone
As already shown in Figure 1.2-1, our approach for an integrated microphone is

based on a multichip module (MCM) concept. The stacking topology and the re-
spective bonding techniques depend very much on the individual components,
especially their sizes, surface topographies and metalizations.
The microphone consists of the transducer chip and a backchamber chip
bonded together using thin-film anodic bonding [28]. The size of the two-layer
microphone is 3.0 × 3.0 × 0.7 mm3. The microphone is based on a capacitive read-
out. The parallel-plate capacitor is formed by a moving membrane and a stiff, per-
forated backplate. Both electrodes are very vulnerable, while the backplate pro-
trudes from the surface by approximately 5 lm.
The metalization system applied for this microphone chip yields bondpads
which are wettable for solder bonding. The bondpads are arranged close to the
electrodes (membrane, backplate) in order to avoid large parasitic loads.
In the current development stage for this microphone, the ASIC is manufac-
tured as part of a multi-project wafer (MPW) in an IC foundry, which means that
only the circuit layout and chip size are free to change (at least to some extent).
The chip size is 3.0 × 1.0 mm2. The chip metalization is Al. The bondpads are ar-
ranged close to the chip edges. The ASICs are delivered on die level.
A1.2.3 Stacking Approach for an Integrated Microphone 29
Table 1.2-1. Feedthrough parameters seen from an electrical point of view
Interconnect Insulation Series Parasitic Application area Ref.

material technology resistance capacitance
(pF)
Backside contacts – wet etched holes

Cr-Cu p-n n/a n/a a ISFET sensors [6]
Ti-Cu–Au p-n n/a n/a a ISFET sensors [7]
Al p-n n/a n/a a ISFET sensors [8]
Polysilicon Thermal ≤ 40 X 30 Shear stress [59]
(LPCVD) SiO2 sensors
Single feedthroughs – wet etched holes
Au PECVD 1–10 mX 30–60 Memory stacks [9]
(electroplating) SiO2
Ti-Au low temp. n/a n/a a Integrated sensors [13]
(evaporation) oxide (LTO)
Solder SiO2 10–15 mX n/a a Substrates for 3D [14]
(pre-form) MCM
Ni (electroplating) Thermal mX < 10 Integrated sensors [15]
SiO2
Conductive Pyrex n/a n/a a Hermetically [16]
adhesive substrate sealed sensors
Single feedthroughs – dry etched holes
SnAg Spin-on glass n/a n/a Feasibility study [60]
(stud bumping)
W (CVD) TEOS 2–4 X n/a CMOS wafer [17]
SiO2 stacks
Polysilicon Thermal n/a n/a 3D micro vision [61]
(LPCVD) SiO2 system
Al (sputtering) Thermal n/a n/a Integrated sensors [18]
SiO2
Multiple feedthroughs – wet etched holes
Al (evaporation) LPCVD <5 X <1 Electrical feed- [20]
Si3N4 throughs
Ti-Au Thermal 3 Xb <1b High-density [21]
(evaporation) SiO2 feedthroughs
Buried feedthroughs – Al thermomigration
Al (evaporation) p-n 20 X n/a Stacking of ICs [25]
Al (evaporation) p-n 50 X 5 Implantable [26]
electrodes
Al (evaporation) p-n n/a c n/a Photosensing array [27]
a
A parasitic capacitance of the order of tens of pF must be expected, depending on the in-
sulating layer and the wafer thickness.
b
For a single feedthrough wire.
c
Based on the data given in [26] we can calculate the resistivity to be 0.4 X cm (eutectic
AlSi), which yields a resistance of 254 X.
Table 1.2-2. Spatial feedthrough densities of selected technologies
Technology Feed- Substrate Wire Wire Ref. Normal-

through ized
density thickness diameter pitch FT den-
sity
Through-hole Wire (mm–2) (lm) (lm) (lm) (mm–2)
Dry (RIE) Single 1000 14 1.4 n/a [17] 240

Dry (RIE) Single 20 480 200 400 [18] 240
Wet (KOH) Single 1.3 300–600 Fully meta- n/a a [5–16, 4.3
lized 59]
Wet (KOH) Multiple b 36 380 10 20 [20] 165
Wet (KOH) Multiple c 55 350 30 60 [21] 55
Buried 4.4 1650 325 400 [26] 100
Buried 9 1900 100 325 [27] 100
a
Depends on substrate thickness and size of the through-holes.
b
Metal evaporation through shadow mask.
c
Electrodepositable photoresist.
The basic requirements of the microphone with regard to the stacking concept
comprise a low parasitic load between microphone and ASIC (short electrical in-
terconnects with small width) and a sufficient frontchamber volume. The micro-
phone stack is directly attached to the housing of the hearing instrument by most
manufacturers. The electrical connections to the other components are realized by
wires, flexprint or litze wires, which means that either the microphone or the IC
has to provide electrical access. Owing to the very compliant interconnects, vibra-
tion (‘acoustic’) coupling between the acoustically sensitive parts (microphone,
loudspeaker) can be avoided. The final stack must be encapsulated and shielded.
To prevent the encapsulation material from entering the inner area of the stack, it
must be sealed from the environment. On the other hand, the microphone must
have controlled acoustic access (sound inlet) from the environment.
1.2.3.1 Topology Discussion
Four basic topologies for the stacking of the microphone and the ASIC can be
distinguished, based on the arrangement of their active sides (see Figure 1.2-2).
The main selection criteria comprise through-wafer interconnects in active layers,
parasitic loads, suitable bonding techniques, and acoustic and electrical access.
Topologies (b) and (d) require post-processing of the ASIC die. While this can
in principle be accomplished if the ASICs are delivered at wafer level [10, 12],
this would be difficult to achieve technologically, and at a high expense of real es-
tate. As long as the ASICs are only available at chip level, the challenge would
be even much greater. The approach in (c) requires feedthroughs in both the mi-
Figure 1.2-2. Schematic diagram of the four principle stacking topologies outlining the ac-
tive sides of the components and the electrical interconnects through and between them.
crophone and the backchamber. In addition to the worse electrical performance,

proper integration of the feedthrough manufacturing into the microphone proces-
sing is very difficult to achieve. Compromises may be necessary, decreasing the
acoustic and electrical performance of the stack. The topology in Figure 1.2-2 a
does not require feedthroughs through active layers, which was the main criterion
to pursue this topology. Owing to the Al metalization on the ASIC (if the metali-
zation is not post-processed after the standard foundry process), only conductive
adhesive bonding can be used to join the two components. An underfiller must be
applied to ensure sufficient mechanical strength. Care has to be taken to prevent
the underfiller from clogging the holes in the microphone backplate. If the ASIC
does not extend the microphone surface on one side, the latter has to provide elec-
trical access for the rest of the hearing instrument. This means additional intercon-
nects between the two components to feed the signal back to the microphone. The
microphone would require a two-level metalization. In principle this is not impos-
sible, but it would add to the complexity of the processing.
To overcome the shortcomings (microphone protection, bonding techniques, elec-
trical access, controlled acoustic inlet), we introduced an additional chip between the
microphone and ASIC, termed interconnect or intermediate layer. A schematic dia-
gram of the stacking approach is shown in Figure 1.2-3. The focus is on how the
above problems were solved. The parasitic load increased, depending on the thick-
Figure 1.2-3. Schematic diagram of the chosen stacking topology.

ness of the intermediate layer, the width of the metalization, and the thickness and
material properties of the insulation layer underneath the metalization. The con-
trolled acoustic inlet is realized at the same time as the frontchamber and through-
holes are processed. Complete sealing of the inner part of the stack is accomplished
by applying a solder sealing ring between the microphone and intermediate layer and
an underfiller between the intermediate layer and ASIC.
1.2.3.2 Intermediate Layer
The main purpose of the intermediate layer is to separate the microphone and
ASIC in order to utilize the bonding techniques which are most appropriate for
the two components. Additionally, the intermediate layer reroutes the two bond-
pad layouts. It also provides the microphone with a frontchamber and a controlled
sound inlet, and the entire stack with electrical terminations to the outer world.
Figure 1.2-4 a shows the microphone side of the intermediate layer. The smaller
through-holes carry the electrical interconnects between the microphone and
ASIC. They are covered by the ASIC and sealed by the underfiller. The larger
hole provides acoustic access to the microphone. A rim of original wafer thick-
ness carries the sealing ring. The H-shaped platform is used for re-routing the me-
talization pattern on the ASIC side (see Figure 1.2-4 b), and to enlarge the area for
the underfiller. Additionally, the H-shaped platform enhances the mechanical stab-
ility and allows handling of the intermediate layer using a standard flip chip bon-
der.
Figure 1.2-4. Layout of the intermediate layer. (a) Microphone side; (b) ASIC side.
1.2.3.3 Interconnect Techniques
We distinguish three interconnect levels: level 1 between the microphone and in-
termediate layer, level 2 through the intermediate layer and level 3 between the
intermediate layer and ASIC. The level 1 interconnect is realized by solder bump
bonding. Wafer feedthroughs provide the intermediate layer with multiple front-
side to backside interconnects (level 2). Conductive adhesive bonding using Au
stud bumps is applied for the level 3 interconnects. The intermediate layer has not
only to provide the feedthrough interconnects, but also under-bump metalization
(UBM) and solder bumps for the level 1 bonding and top surface metalization
(TSM) for the adhesive bonding. Figure 1.2-5 shows the metalization scheme of
the intermediate layer.
1.2.3.3.1 Solder Bump Bonding
Using solder bump bonding (SBB), it is possible to combine single interconnects

with a sealing ring in one process [29]. In addition to the sealing capability, the
solder ring also improves the mechanical stability. The bonding process needs to
be fluxless because of the delicate surface of the microphone. In contrast to alter-
native fluxless processes [29–31], our technology uses as-deposited bumps and
combines solder reflow and bonding in one step [32]. During heating the solder
the bumps start to reflow and, thus, break the native solder oxide layer on the sur-
face. Fast re-oxidation during bonding is prevented owing to a low oxygen partial
pressure in the range 10 2 –10 4 Pa, depending on the equipment used. We inves-
tigated pure Sn and eutectic SnAg as the bump material. The actual bonding is
preceded by a prebonding step. Here, a mechanical bond is achieved by applying
moderate temperatures and forces. The prebonding is necessary to ensure wetting
of the microphone metalization by the solder. The solder material is electroplated
and, thus, contains organic contaminants. During reflow these contaminants will
Figure 1.2-5. Metalization scheme of the intermediate layer.

be driven out to the surface and, in the case of fluxless processes, prevent wetting
of the TSM on the microphone.
1.2.3.3.2 Through-wafer Interconnects
The feedthrough interconnects are processed in three different ways [21, 33, 34].
The interconnects are realized as multiple feedthroughs per through-hole. The pat-
terning of the interconnect metalization is done by utilizing an EDPR. The feed-
through interconnects are optimized with regard to low series resistance and small
parasitic capacitance. The bondpads on the microphone side of the feedthroughs
are provided with Ni UBMs and solder bumps. The bondpads on the ASIC side
feature TSMs, consisting of Ni as diffusion barrier and Au as bondable surface. A
solder sealing ring on the microphone side of the intermediate layer is processed
at the same time as the solder bumps. Besides sealing the inner part of the stack,
it provides the bulk of the intermediate layer with ground potential.
1.2.3.3.3 Conductive Adhesive Bonding
Conductive adhesive bonding (CAB) is the only technique that allows flip chip
bonding of single dies with Al metalization without extended post-processing of
the latter. The process uses gold studs dip-coated in conductive adhesive [35].
The gold studs are used since adhesives usually cannot form strong bonds to the
Al metalization without pretreatment of the bond pads [36]. The process of stud
bump formation is the same as for conventional wire bonding. To obtain an uni-
form height the bumps are leveled by pressing them against a flat surface [35].
The bond obtained is strong enough to handle the bonded chips, but not strong
enough to serve as a stable mechanical bond. To enhance the mechanical stability
and to provide a hermetic seal, a non-conductive adhesive is used, a so-called un-
derfiller. It is applied at one or two (neighboring) sides of the stack and fills the
gap by capillary forces. The curing temperatures of the adhesives are well below
the soldering temperature, ensuring integrity of the solder bump bond.
1.2.4 Intermediate Layer – Technical Aspects
1.2.4.1 Bulk Micromachining
In our application, bulk micromachining means realizing both through-holes and

frontchamber. These structures are etched anisotropically using 28 wt% KOH at
80 8C. We chose an anisotropic wet etch technique for two reasons. First, the
sloped sidewalls of the etched holes allow photolithography on them using stan-
A1.2.4 Intermediate Layer – Technical Aspects 35
dard exposure tools. Second, wet etch techniques allow for batch processing, thus
being faster and more economical than dry etch techniques. The main challenge
in through-hole etching is the combination of both through-holes and frontcham-
ber in one process sequence. Key issues for designing this process are cost effi-
ciency (number of process steps, batch process capability) and reproducibility. To
meet these requirements we used a so-called dynamic mask process (SiO2 ). This
process makes use of the relatively high etch rate of SiO2 in KOH. Both etch
rates (Si and SiO2 ) are very sensitive to changes in KOH concentration. Whereas
that of silicon decreases with increasing concentration, the etch rate of SiO2 in-
creases. Since the etch process is based on dissolving the dynamic SiO2 mask in
a given time, care has to be taken to maintain uniform etching conditions. The
complete etch mask consists of thermally grown SiO2 of 1 lm and a layer of sili-
con-rich SiNx of 150 nm. A first lithography step defines the three through-holes,
followed by reactive ion etching (SF6 -O2 plasma) of the SiNx , and wet etching
(BHF) of the SiO2 layer. The frontchamber area is defined by a second lithogra-
phy step and subsequent reactive ion etching. The remaining SiO2 serves as dy-
namic mask. During etching the silicon wafer in KOH the dynamic mask is also
etched. When the dynamic mask has dissolved completely, the now exposed sili-
con is thinned down. After stripping residual etch mask layers, thermal SiO2 is
grown to serve as a dielectric layer. The bottom of the H-shaped platform shows
a ridge at the center. This is due to the fact that the convex corners exposed to
KOH after dissolving the dynamic mask exhibit very fast etching crystal planes,
which etch faster than the (100) surface plane. This results in fast lateral etching.
Figure 1.2-6 shows SEM images of a completely etched intermediate layer using
the dynamic mask process.
Figure 1.2-6. Completely etched intermediate layer using the dynamic mask process. (a)
Top view of well etched sample. The inset shows a close-up of the remaining (111) planes
in the corner of a throughhole. (b) Too fast lateral etching due to unstable etching condi-
tions.
1.2.4.2 Bulk Contact
Realizing the bulk contact as add-on processing [2] after having completed the
bulk micromachining is advantageous for prototyping where usually only a lim-
ited number of wafers are processed. However, once the layouts are settled and
manufacturing starts, the large number of single-wafer processes turns into a han-
dicap. Therefore, we developed a process sequence which defines the contact
areas before the bulk micromachining using exclusively batch processes. The new
combined processing makes use of a technology widely used in CMOS manufac-
turing, the LOCOS (local oxidation of silicon) process [37]. Figure 1.2-7 shows a
simplified process sequence for the intermediate layer utilizing a modified (dou-
ble) LOCOS process. Only the microphone side of the intermediate layer is
shown.
First, a dry thermal SiO2 layer is grown with a thickness of about 60 nm. Next,
we deposit 150 nm Si3 N4 by LPCVD and convert about 20 nm into SiO2 by wet
thermal oxidation. We use standard photolithography (spin-on resist) to define the
contact area (step 1). The thin conversion-SiO2 is patterned in BHF and serves as
an etch mask for the subsequent structuring of the Si3 N4 layer in phosphoric acid
at 180 8C (step 2). A wet thermal oxidation and a LPCVD silicon-rich SiNx form
the etch mask for the bulk micromachining as described above (step 3). The first
(LOCOS) Si3 N4 layer is lifted at the structure edges forming ‘birds’ beaks’ due to
oxidation underneath these areas. This oxidation is caused by lateral diffusion
through the thin, dry SiO2 . The diffusion length corresponds to the thickness of
the dynamic mask SiO2 thickness. The etching of the frontchamber and the
through-holes is done as described above. After completing the bulk microma-
chining, we strip the etch mask layers in phosphoric acid (SiNx ) and BHF (SiO2 ),
respectively (step 4). Next, the dielectric layer is grown by wet thermal oxidation,
which, again, converts the surface of the LOCOS Si3 N4 into SiO2 (step 5). On
top of the oxide layer we deposit LPCVD Si3 N4 . This layer is used to compen-
sate for wafer bowing due to the non-symmetric topologies of the two sides of
Figure 1.2-7. Intermediate layer process sequence combining bulk micromachining and
LOCOS process. The focus is on the bulk contact area on the microphone side.
Figure 1.2-8. SEM image of intermediate layer focusing on the transition between contact
area and dielectric layer.
the intermediate layer. Only the nitride on the microphone side is stripped by
RIE. This etch step also removes the thin conversion oxide and the LOCOS ni-
tride. The etching stops on the dry oxide. A short dip in BHF removes the latter
(step 6). The lateral oxidation underneath the LOCOS Si3 N4 results in the above
mentioned birds beaks. Too high birds beaks can give problems in subsequent
processing, such as evaporation of the Eagle resist plating base for feedthrough
processing. The rather poor step coverage of e-beam evaporation could result in a
non-continuous plating base. However, the 1 lm birds beak on our samples does
not cause any problems. An SEM image outlining contact area, dielectric layer,
and birds beak is shown in Figure 1.2-8.
1.2.4.3 Eagle 2100 ED Electrodepositable Photoresist
Generally, an EDPR solution is made up of an emulsion working bath containing

10–15 % organic solids in aqueous solution. The solids are so-called micelles
containing a microenvironment of the photoresist, which means photosensitive
elements, contrast enhancers, and chargable polymers as the backbone. For a
more detailed description, see Vidusek [38] and Merricks [39]. The micelles be-
come electrically charged in an acidic or alkaline environment, depending on the
polymer used. By applying an electric field, negatively charged micelles migrate
towards the anode (anaphoresis), whereas positively charged micelles migrate to-
wards the cathode (cataphoresis). Shipley’s Eagle 2100 ED/PR is a negative-tone,
cataphoretic photoresist. It is used in the packaging industry for structuring of
copper metalized printed circuit boards.
1.2.4.3.1 Deposition Parameters
In addition to the bath composition, deposition temperature, voltage, and duration

are the most important resist deposition parameters. We found only marginal influ-
ences on varying the distance between the two electrodes and changing the plat-
ing base material.
Bath Temperature. The plots of resist thickness versus bath temperature (see Fig-
ure 1.2-9) exhibit a minimum with thicker coatings on either side. At low bath
temperatures the resist is very porous (low density), which is due to a high bath
viscosity. Increasing the bath temperature lowers the viscosity of the bath, the re-
sist film density increases, and, consequently, the resist thickness decreases. On
increasing the bath temperature further, the resist thickness increases again owing
to lowered film resistivity. Also, ionic transport through the resist film takes
place, resulting in further micelle deposition. The bath temperature strongly af-
fects the adhesion of the resist layer to its plating base. At low bath temperatures
the adhesion is very poor but it improves at higher temperatures starting at 30 8C.
Deposition Voltage. The deposition voltage affects the resist thickness only at
higher bath temperatures. Here, very thick coatings can be obtained by chosing a
proper voltage ( 150 V). Although not affecting resist thickness in the low-tem-
perature range, the deposition voltage determines to some extent the deposition
time (self-termination). Here, higher voltages result in shorter deposition dura-
tions, probably owing to a higher migration speed. Large areas to be coated and/
or thin plating base layers may result in very high local current densities, espe-
cially in the vicinity of the contacts. The resulting local heating leads to signifi-
cant variations in resist thickness, which mainly applies to the right-hand side of
the curves in Figure 1.2-9. In those situations a (low) constant-current deposition
is preferable.
Figure 1.2-9. Resist thickness as a function of bath temperature, deposition voltage, and
deposition time. Bath conductivity, 305 lS/cm; solids, 12%.
Deposition time. At low bath temperatures, the deposition process is self-terminat-

ing. Depending on the deposition voltage, the coating process is finished after
about 3–6 s. On increasing the bath temperature, the current shows a similar be-
havior, but it does not go completely to zero. Here, the deposition process con-
tinues with a very low deposition rate. At even higher bath temperatures a second
current peak occurs. This second peak is caused by dielectric breakdown due to a
too high deposition voltage combined with long deposition durations. It occurs
only under these conditions. Additionally, it depends on the age of the resist bath.
Extending the deposition process after the second peak yields coatings with a sur-
face roughness of up to 20 lm.
Bath Composition Parameters. Controlling the bath composition means primarily

controlling conductivity, acidity, and content of solids. Variations in conductivity
and acidity can affect the migration speed and hydrolysis of water, respectively.
Especially the latter can have significant implications for the final coating quality.
Conductivity and acidity are related to each other and controlled by keeping the
former at a constant level. The content of solids is determined by drying a sample
of resist emulsion and measuring the difference in weight. However, the solid
content affects resist thickness only marginally. A more important parameter is the
plasticizer content [40]. The plasticizer controls the glass transition temperature,
Tg , of the resist particles and, thus, the leveling process of the resist film during
deposition and baking. A sufficient high plasticizer content decreases Tg and
yields better resist film uniformity. The plasticizer content varies with time by
being co-deposited with micelles and by evaporation, the latter being negligible at
low bath temperatures. Plasticizer degradation results in a shift of the resist thick-
ness curve in Figure 1.2-9 to higher bath temperatures (see Figure 1.2-10). The
plasticizer content will eventually go to zero if not replenished regularly.
Figure 1.2-10. Shift in resist thickness versus bath temperature due to degradation of plas-
ticizer content.
1.2.4.3.2 Baking Procedure
Already during electrodeposition coalescence of the resist film takes place by

driving out water and occluded ions by electro-osmosis. However, there is a small
percentage (about 5%) of water left which needs to be removed in order not to af-
fect subsequent exposure and development. Full coalescence is achieved by bak-
ing the samples at elevated temperatures [40]. Baking also improves adhesion and
fuses possible pinholes. How the resist surface changes with baking is shown in
Figure 1.2-11. However, baking can cause major problems if sharp-edged features
are present, which is the case in our applications. Here, baking would lead to re-
flow of the resist from these corners or edges. The level of reflow depends on,
among others, the plasticizer content. The higher the plasticizer content, the
stronger is the reflow. Figure 1.2-12 shows an anisotropically etched through-hole
coated with Eagle photoresist before any baking treatment. The two close-ups
show the obtuse and acute corners. It turns out that the as-deposited coating is
very uniform all over the structure. Figure 1.2-13 shows SEM images of samples
baked under different conditions. Baking the resist at 50 8C results in a slight re-
flow at the obtuse corner and a strong reflow at the acute corner. Increasing the
temperature to 65 8C or even 80 8C results in a strong reflow at both the obtuse
and acute corners.
In order to perform subsequent processing such as etching, lift-off, or electro-
plating successfully, excessive reflow must be avoided. Some reflow is acceptable
for etching processes as long as the areas to be protected by the resist are not ex-
posed to the etchant. Besides, for etching and electroplating the requirement on
adhesion is high. Therefore, sufficient baking is essential. However, for lift-off or
electroplating we need uniform coatings all over the wafer. For that purpose we
developed a new process which is able to replace the standard baking procedure.
This new process is based on applying a vacuum after resist coating to remove
water residues from the deposit [33]. No noticeable reflow takes place (Fig-
ure 1.2-14). Vacuum treatment does not enhance adhesion. In cases where uni-
form coating AND fair adhesion is required the already vacuum-treated resist
should be baked for a very short time.
Figure 1.2-11. Influence of baking on resist surface topography. (a) Resist surface as de-
posited; (b) after baking at 60 8C; (c) after baking at 70 8C. Baking duration, 25 min each.
Figure 1.2-12. As-deposited Eagle resist on silicon wafer with anisotropically etched
through-holes. Close-up: obtuse (top) and acute (bottom) corner of through-hole. Deposi-
tion conditions: 45 s at 34 8C and 125 V.
Figure 1.2-13. Influence of baking conditions on reflow behavior of Eagle resist at sharp
edged corners of anisotropically etched through-holes. SEM images of obtuse (left) and
acute (right) corner coverage. The resist thickness at flat surfaces is around 12 lm.
Figure 1.2-14. SEM images of (a) obtuse and (b) acute corner for vacuum-treated resist.
Conditions: 1 h at 10–4 Pa.
1.2.4.4 Lithography on (111) Sidewalls
The main challenge in patterning multiple feedthroughs concerns the nonunifor-

mity in resist exposure conditions across a complete feedthrough structure. The in-
terconnect starts on the flat surface, runs across the tilted (111) sidewalls for sev-
eral hundred microns down to the through-hole bottom, and ends on the backside
of the wafer. Even though the EDPR is deposited conformally with uniform or
near-to-uniform thickness, the geometry of a through-hole still leads to challenges
in UV exposure through a photomask. Optimization of resist exposure (which
strongly affects subsequent processing steps) of a complete frontside feedthrough
structure (on (100) and (111) surfaces) is hindered by the varying angle of inci-
dence of light a, mask to resist gap g and resist thickness t along the line of the
incident light (Figure 1.2-15).
Figure 1.2-15. Variation of exposure conditions along a feedthrough structure.

1.2.4.4.1 Light Reflections

The deviation of the angle of incidence from 0 to 54.74 8 is the most severe prob-
lem. Incident radiation is partially reflected on the air/resist and resist/plating base
interfaces, leading to cross-exposure, and, eventually, ghost images on opposite
sidewalls. The seriousness of the reflection problem depends on the amount of re-
sist to be illuminated. Since we use a negative working resist we expose most of
the area for lift-off and electroplating processes. A thorough discussion of that
problem was presented by Linder [9]. There are several ways to overcome unde-
sired reflections. The one proposed by Linder makes use of linearly polarized ra-
diation. Using the parallel polarized light component on the sidewall to be ex-
posed, no reflections from the resist surface occur. This is due to the fact that the
angle of incidence a = 54.74 is close to the Brewster angle H of the photoresist,
which is about 58 (Brewster angle: H arctannresist=nair ; nresist 1:6. At the
Brewster angle, the reflection coefficient exhibits its minimum; for non-absorbing
materials it is zero [9]. On the other hand, light is also reflected from the resist/
plating base interface. Here, the angle of incidence a is about 30 8. Reflections
can be reduced by polarization of the incident light only on two opposite side-
walls. Resist on the other two sidewalls of the through-hole will be exposed to
the perpendicular polarized light component, resulting in a large reflection coeffi-
cient at the air/resist interface.
A second way to get rid of reflections is the use of antireflective coatings
(ARCs). ARCs are extensively used for sub-micron lithography in the deep ultra-
violet (DUV) exposure wavelength range. For a detailed discussion of different
types of ARCs, see [41]. In our application, however, the number of requirements
on such a layer is too numerous to make ARCs a suitable candidate. Some of the
most important requirements are process integrity with the EDPR process, high
conductivity, proper angle of incidence and wavelength range, and suitable de-
position and stripping techniques.
The simplest way to avoid reflections is to minimize the exposed area on the
sidewalls. In cases where a negative resist is used and the patterning technique is
lift-off or electroplating, this can be achieved by introducing a suitable compensa-
tion pattern. Figure 1.2-16 shows three different options for lift-off and plating
techniques (clear field mask). Figure 1.2-16 a shows the worst case: feedthrough
structures on only one side. Here, the entire area of the other three sidewalls is
exposed to light. Reflected light exposes the resist in the lower region of the side-
wall to be patterned, which then becomes resistant to the developer. This results
in open circuits. The height of this region depends on the size of the through-
hole. If the opening on the cavity etch window is at least 3.5 times the wafer
thickness, all reflected light passes through the bottom hole. Figure 1.2-16 b
shows feedthroughs on all four sidewalls. Here, the light is reflected according to
the feedthrough pattern. If the interconnect lines are arranged directly opposite,
the reflected light leads to a decreasing linewidth of the feedthroughs due to
broadening of the light (Fresnel diffraction). Figure 1.2-16 c shows a feedthrough
pattern on only one sidewall, again, however, combined with compensation struc-
tures on the other sidewalls. These additional structures are only present in the
Figure 1.2-16. Light reflections for different feedthrough arrangements. The upper figures
show the mask layout. The lower figures show SEM images of the feedthrough intercon-
nects in the through-hole bottom. (a) Feedthroughs on one side; (b) feedthroughs on all
four sides; (c) feedthroughs on one side combined with compensation structures.
upper part of the through-hole. The resulting feedthrough interconnects exhibit

uniform linewidths all the way down to the through-hole bottom.
1.2.4.4.2 Mask-Resist Distance
The distance between mask and resist is not constant but varies owing to the
tilted (111) sidewalls. The increasing gap between the mask and resist lowers the
resolution due to Fresnel diffraction. However, knowing the exact deviation (ex-
perimentally determined) of the wire dimensions in the through-hole from that on
the mask, a tapered feedthrough layout can compensate for this. Depending on
the metalization patterning technique (etching or lift-off/electroplating), the wire
width on the photomask gradually decreases or increases with increasing gap. The
feedthrough structures in Figure 1.2-16 c were realized using tapered structures on
the photomask.
1.2.4.4.3 Relative Resist Thickness

The relative resist thickness is that one normal to the wafer surface, as seen from
the light source during exposure. Owing to the tilted (111) sidewalls, this thick-
ness (t111 ) differs from that on the flat surface (t100 ) following the expression
1 p
t111 t100 3t100 : 1
cos 54:748
For a resist thickness t100 = 8 lm, the relative thickness becomes t111 = 13 lm.
Optimum exposure conditions on the flat surface result in underexposure on the
sidewalls. Optimum exposure conditions on the sidewalls result in overexposure
on the flat surface. Which exposure conditions to use depends on the feedthrough
patterning technique. For etching and electroplating techniques only the overexpo-
sure option can be used in order to achieve sufficient resist adhesion and etchant/
bath stability.
1.2.4.5 Thin-film Feedthroughs
1.2.4.5.1 Etching
Etching as a patterning technique for multiple feedthroughs was described by

Christensen et al. [21]. Etching techniques are well suited for multiple feed-
through patterning as long as the metalization system is simple, consisting prefer-
ably of only one or two metal layers. More layers may lead to selectivity prob-
lems due to the need of different etchants. Additionally, differences in electro-
chemical potentials between metal layers can drastically affect their etch behavior.
1.2.4.5.2 Lift-off
For multiple feedthroughs compatible with the bonding techniques described in

Section 1.2.3, we developed a lift-off technique. We deposit the resist at low bath
temperatures, using a thin layer of Ti as plating base. The resist is dried in vacu-
um. The exposure dose is chosen to yield optimum results on the wafer surface.
After development, the exposed Ti is stripped, followed by e-beam evaporation of
the interconnect metalization. The lift-off is done in acetone. Finally, we strip the
remainder of the plating base.
The wettable surface is not limited to the bondpads, but is present all over the
interconnect lines. To prevent the molten solder from spreading further on to the
feedthrough interconnects, we provide the latter with a so-called solder dam. The
solder dam, realized only on the microphone side of the intermediate layer, is
made of SiO2 deposited by means of plasma-enhanced chemical vapor deposition
(PECVD).
Stacking experiments with passive test devices showed that the chosen metali-
zation scheme is well suited for flip chip solder bonding and conductive adhesive
bonding. On the other hand, electrical measurements showed series resistances as
high as 26 X for a single feedthrough interconnect. The calculated wire resistance,
applying the same geometric dimensions, is only about 13 X, which means a fac-
tor of two smaller. It is obvious that the limiting factor is the resistance at the
through-hole edge, the acute corner. Here, the feedthrough metalization is signifi-
cantly thinner than elsewhere. Investigations carried out with thicker interconnects
showed an increased factor between the calculated and the measured resistance.
1.2.5 Electroplated Through-wafer Interconnects
1.2.5.1 Metalization Scheme and Processing
Feedthrough interconnects based on thin-film technologies always exhibit high se-

ries resistances of the order of several ohm if the feedthrough width is small in or-
der to have a low parasitic load, even if the feedthrough pattern should be given a
large width at the sharp corner. This means that feedthroughs realized by etching
or lift-off techniques cannot be used for our low-power application. To meet the
requirements for low resistance and low parasitic capacitance will be difficult.
Much better characteristics are potentially feasible with electroplated feed-
throughs. Further, such a technology is very cost-effective and, as with lift-off,
one can have a complex metalization scheme, complete with diffusion barriers,
wettable surfaces, and solder dam (Figure 1.2-5). For the feedthrough wires we
use Cu because of its low resistivity. Since our solder bond technology does not
use fluxing agents, the oxidized Cu lines readily serve as solder dam. This signifi-
cantly reduces the number of process steps and contributes to the cost-effective-
ness of our technology. The TSM for the CAB consists of Ni as diffusion barrier
and Au as bondable surface. The UBM on the microphone side consists of Ni as
wettable surface. The solder material is either Sn or eutectic SnAg. As mold for
all plating processes we use Eagle resist. Figure 1.2-17 shows a simplified se-
quence for the processing of this interconnect metalization scheme. The plating
base for all metal plating processes and for the Eagle resist consists of 100 nm Au
on top of 15 nm Ti and is deposited by e-beam evaporation (step 1). Mold 1 for
Cu plating is formed by thin, 8 lm Eagle resist. After lithography, Cu is electro-
plated to form the interconnect lines (step 2). Both sides are plated at one time,
using only one counter electrode. The Cu thickness is 3 lm. Mold 2 is a 25 lm
thick Eagle resist. Baking is performed at 80 8C. After lithography, the exposed
Cu landings on the ASIC side are activated in dry acid followed by electroplating
of Ni and Au (step 3). The thicknesses are 3 and 1 lm for Ni and Au, respec-
tively. Next, mold 3 is deposited and baked using the same conditions as for
mold 2. The Cu bondpads on the microphone side are activated and Ni is plated,
followed by Sn or SnAg (step 4). The thicknesses are 3 and 20 lm for Ni and
Sn/SnAg, respectively. The total height of the bumps must not exceed the resist
height. Overplated bumps result in mushroom structures causing two problems:
Eagle residues will remain at the bump sides protected by the mushroom head,
and, owing to a very small pitch (180 lm), adjacent bumps will be shortened dur-
ing prebonding.
A1.2.5 Electroplated Through-wafer Interconnects 47
Figure 1.2-17. Simplified process sequence for electroplated feedthrough interconnects.
Figure 1.2-18. (a) Electrical multiple feedthrough structures showing the interconnect
wires, UBM, solder bumps, and solder sealing ring. (b) UBM with reflown Sn bump.
Figure 1.2-19. (a) Bondpad on ASIC side. (b) Close-up of Ni/Au TSM.
Stripping of mold 3 is not as straightforward as stripping of the other two

molds. The resist must only be removed in acetone, followed by careful descum-
ming (standard stripping procedures are based on Eagle 2010 Remover or concen-
trated Eagle 2005 Developer). Further details are given below. The Au plating
base is stripped in Entreat 100 [42], selectively over all other metals. The Ti adhe-
sion layer is stripped in KOH-H2 O2 , which also oxidizes the Cu wires further.
Finished electroplated feedthrough structures are shown in Figure 1.2-18 a as
deposited and Figure 1.2-18 b shows a close-up of a fluxlessly reflown solder
bump, outlining the excellent quality of the solder dam. Figure 1.2-19 a shows a
bondpad on the ASIC side and Figure 1.2-19 b a close-up of the Ni/Au TSM.
1.2.5.2 Electroplating Aspects
Although not an electroplating process, we include some aspects of etching of the

Au plating base here. As already mentioned above, we use Entreat 100, which
etches Au selectively over Sn, SnAg, Ni, and Cu. However, in some cases it
could not etch the Au layer around the Sn structures (sealing rings and bumps).
The problem is diffusion of Sn along the bump sidewall surface into the Au plat-
ing base. There, Au and Sn form intermetallic phases. In the presence of an or-
ganic acid, such as lactic acid in Eagle 2005 and acetic acid in Eagle 2010, a salt
is formed which withstands the Au etchant [43]. This could not be observed
when etching the Au layer directly after Cu or Ni/Au plating. That is why we use
exclusively acetone to remove the Eagle resist after Sn plating. Figure 1.2-20 a
shows a row of reflown Sn bumps connected by Cu lines after plating base strip-
ping. The Eagle resist was removed in Eagle 2010 Remover. All Sn bumps are
surrounded by plating base residues. These residues are not present around the
pure Cu lines. The plating base residues are not wettable for soldering (see Fig-
ure 1.2-20 b) and, thus, cannot be pure Au, Sn, or AuSn. That Sn had diffused
into these areas was demonstrated by secondary ion mass spectroscopy (SIMS)
Figure 1.2-20. (a) Reflown Sn bumps connected by Cu lines and surrounded by plating
base residues. (b) Reflown Sn bumps with residual plating base outlining the nonwettabil-
ity of the latter.
Figure 1.2-21. SIMS spectra of (a) plating base far away from Sn structures and (b) plat-
ing base in the close vicinity of Sn structures.
measurements. Figure 1.2-21 a shows a SIMS depth profile for the plating base far
away from any Sn structures and Figure 1.2-21 b shows that in the close vicinity
of Sn structures. The count rate of Sn in Figure 1.2-21 a is about 103 cps. It is
about 105 cps in Figure 1.2-21 b, which clearly indicates strong diffusion of Sn
into the plating base in these areas.
All metal electroplating baths have to be in the mildly acidic or alkaline range
in order to be compatible with the Eagle resist (metal electroplating was done in
collaboration with the Institute of Manufacturing Engineering at the Technical
University of Denmark). Bath specifications and an overview over the most im-
portant plating parameters are given in Table 1.2-3.
In addition to the bath temperature, the current density is a very important plat-
ing parameter. It is of crucial importance to know the exact area to be plated in
order to adjust the current accordingly. Increasing the current usually increases the
deposition rate. However, the metals cannot be deposited with unlimited speed, as
at some point diffusion processes become dominant. This is the so-called limiting
current density [44]. If the current is too high, the current efficiency decreases be-
cause more of the transferred charge is used for hydrolysis of water. First, this
changes the metal deposition conditions due to an increased pH value. Second,
Table 1.2-3. Electroplating parameters and bath specifications
Metal Bath type pH Temp. Current density Dep. rate

(8C) (A/dm2) (lm/min)
Cu Pyrophosphate [62] 9.0 55 1.25 0.25

Ni Sulfamate [62] 4.5 40 1.25 0.25
Au ENGOLD 95RPC [63] 4.3 35 0.55 0.10
Sn DGV SN-232 [45] 6.5 20 0.50 0.50
and for us even more important, is the generation of hydrogen bubbles. If these
gas bubbles stick to the surface, metal deposition is prevented locally, which can,
in the worst case, lead to open circuits. Additionally, growing hydrogen bubbles
introduce an enormous force on the Eagle resist and can lift it off. Consequently,
the current density should always be chosen so that a 100% current efficiency is
achieved. However, for some plating baths it will never reach 100%. This is be-
cause of parasitic reduction processes of higher oxidation steps to lower ones
which do not result in deposition. In our case it is only the Sn bath that behaves
in that way. Sn2 at the bath surface oxidizes to Sn4 [45]. During electroplating
the Sn4 is reduced again, consuming part of the transferred charge. If the parasi-
tic reduction processes consume a considerable part of the current, it can signifi-
cantly affect the uniformity of the deposit.
1.2.5.3 Results
Figure 1.2-22 shows (a) the microphone side and (b) the ASIC side of an inter-
mediate layer fabricated utilizing the dynamic mask micromachining and electro-
plating of feedthrough interconnects. The sealing rings are bulk-contacted utilizing
the double LOCOS process. The resistance between two sealing rings is about
380 X. This high resistance is due to the resistance in the bulk silicon
(q = 50 X cm) and unknown Schottky barriers between the (n-type) bulk silicon
and the Ti adhesion layer. The contact resistance can be reduced by annealing. At
elevated temperatures (750 8C [4]) Ti forms a low-resistivity silicide with silicon.
We performed test bonding experiments in order to investigate the quality of
the electroplated metalization system. Microphone dummies and intermediate
chips were bonded together using the fluxless solder bonding technique described
above. The native Cu2 O showed excellent solder dam behavior. Since the decom-
position of the Cu2 O takes place at temperatures above 600 8C for an oxygen par-
tial pressure of 10 7 Pa [46], this technology is also applicable for solders with
Figure 1.2-22. Finished intermediate layer. (a) Microphone side; (b) ASIC side.
Figure 1.2-23. Cratering after destructive shear test.
higher melting points. We investigated the strength of the solder bonds with shear
testing. The fracture occurred predominantly in the silicon (cratering), which ac-
counts for nonideal application of the shear force, but also for excellent adhesion.
A SEM picture of the sheared intermediate layer can be seen in Figure 1.2-23.
1.2.5.4 Electrical Characterization
1.2.5.4.1 Interconnect Wire Model
The most important electrical properties of the feedthrough interconnects are the
series resistance Rs and the parasitic capacitance (parallel capacitance to ground)
Cp . Both must be minimized in order to fulfill the strong requirements for low
power and high signal-to-noise ratio of the complete stack. The specifications for
these parameters are Rs < 1 X and Cp < 5 pF. In addition to these two parame-
ters, an interconnect wire is characterized by its self-inductance, Ls . Since Ls is
not a material parameter but depends on the current return path, we will discuss
all present arrangements. As stated earlier, the intermediate layer can be grounded
or floating, which has a significant impact on the inductance.
A single feedthrough wire can be modeled as shown in Figure 1.2-24. The
rather short length of our feedthroughs allows us to apply a simple lumped RC
network (the more complicated transmission line theory must be applied when the
rise time of the signal is equal to or smaller than the traveling time. Our feed-
through wires have a length of < 1 mm. The resulting traveling time on silicon di-
oxide is 6.7 ps. The signal rise time for standard CMOS is in the nanoseconds
range [47]). We assume an uniform thickness along the interconnect wire. The
material parameters are those of bulk material and are taken from reference
Figure 1.2-24. Simplified model of a single feedthrough interconnect. (a) Schematic cross
section of a feedthrough wire including geometry and material parameters; (b) equivalent
circuit model for a single feedthrough wire.
books. One has to be aware that especially the resistivity of electroplated metals
can deviate significantly from bulk values found in the literature.
Coupling between adjacent wires is shown schematically in Figure 1.2-25 a. In
addition to the wire parameters and the geometric dimensions, the presence (and
thickness) of a condensed water film has a significant impact on the coupling pa-
Figure 1.2-25. Simplified model of coupling between two adjacent interconnect wires. (a)
Schematic diagram; (b) equivalent circuit. The two wires W1 and W2 are indicated by their
terminals A and B.
rameters. The chief coupling parameters are wire-to-wire resistance, mutual capa-
citance, and mutual inductance. The respective equivalent circuit for the coupling
situation is shown in Figure 1.2-25 b.
The feedthroughs on the intermediate layer are of different lengths. Therefore,
we give all parameters per length. All numbers presented (analytical and experi-
mental) are for room temperature. Wire width w 40 lm and wire thickness
t 3 lm are default values.
1.2.5.4.2 Series Resistance Rs
The wire series resistance Rs is a function of the geometric dimensions, the

material parameters, and the frequency. The first two determine the conductor loss
RDC (for f = 0), whereas the last one determines the so-called skin effect loss RAC
(at higher frequencies the current is not uniformly distributed over the entire
cross-sectional conductor area but concentrates near the conductor surface. The ef-
fective cross-sectional area is given by the skin depth d and the corrected width
(perimeter) weff ). The wire resistance in general can be written as
l
Rs qCu X 2
weff
where qCu is the resistivity of Cu. The effective wire width weff and skin depth d
are both functions of frequency f. For f 0 they equal the geometric width w
and thickness t, respectively. By substituting expressions for d [48] and weff [9]
into Equation (2) the series resistance becomes
2 s w w
3
l0 lCu p f 1:0483 0:218 ln t 0:772e 5
t
1
Rs qCu l4 X 3
wt qCu 2w t
where l0 is the permeability in air and lCu is the relative permeability of Cu. The
resistance increases due to the skin effect above a frequency of 107 Hz. The fre-
quency in which we are interested is in the range 100 Hz–20 kHz. Thus, for our
application it is sufficient to consider only the DC resistance, which means that
Rs is equal RDC . R0s for different interconnect widths and thicknesses is shown in
Table 1.2-4. The series resistance per length for the wire dimensions used on the
intermediate layer is R0s = 0.143 X/mm. The three feedthrough wires are not of uni-
form length but vary between 760 lm and 1 mm. Thus, the resulting series resis-
tances vary between 0.108 X and 0.143 X.
Table 1.2-4. Series resistance per length for different feedthrough wire widths and thick-
nesses. The bold numbers are the default values and the respective series resistance per
length
R0s (X/mm) Thickness t (lm)
1 3 5
Width 30 0.573 0.191 0.115

w 40 0.430 0.143 0.086
(lm) 50 0.344 0.115 0.068
1.2.5.4.3 Parasitic Capacitance Cp

The parasitic capacitance Cp is mainly determined by the lateral dimensions of
the feedthrough interconnects (width w, length l), including bondpads, and the
thickness h and the dielectric constant eSiO2 of the insulating layer. Depending on
the thickness of the interconnect wire and the doping level of the bulk silicon,
fringe effects and depletion capacitance must also be taken into account. Thus,
the parasitic capacitance is given by the interconnect capacitance Cplate, which in-
cludes fringe effects, and the depletion capacitance Cdepl . Since both components
are in series, we obtain
CplateCdepl
Cp F : 4
Cplate Cdepl
The fringe capacitance can be modeled as a cylindrical wire [47] with the feed-
through thickness being the wire diameter. Separating the fringe field from the
parallel plate capacitance, the width of the latter must be reduced by half the
thickness of the dielectric. The interconnect capacitance per length can be written
as [47]
8 9
>
> >
>
>
> >
>
<w t 2p =
0 " ! #
Cplate e0 eSiO2 r F=m 5
>
> h 2h 2h t > >
>
> ln 1 1 1 >
>
: ;
t h
where eSiO2 is the relative dielectric constant of silicon dioxide. The depletion ca-
pacitance is a function of the depletion depth, which is primarly determined by a
possible bias voltage and the built-in potential [49]. The latter depends on the
doping level of the bulk silicon. The depletion capacitance per length without bias
voltage can be written as [49]
v
u 2
0 uq e0 eSi NB
Cdepl wu F=m 6
t NB
2kT ln
ni
where q represents the elementary charge. A possible bias voltage must be sub-
tracted from the built-in potential, and we obtain
v
u qe0 eSi NB
0 u
Cdepl wu F=m 7
t kT NB
2 ln U
q ni
NB: Bulk impurity density [cm–3]
ni: Intrinsic density [cm–3]
where U is the bias voltage. In order to give the parasitic capacitance per length,
we consider the bondpads separately. The size of one bondpad is 90 × 90 lm2 .
Using Equation (5) we calculate Cplate = 0.29 pF. The depletion capacitance is
22.6 pF according to Equation (6) (for NB = 4 × 1015 cm 3 , U = 0). According to
Equation (4) we obtain Cp = 0.286 pF. It turns out that the parasitic capacitance is
entirely given by the interconnect capacitance. Hence, it is sufficient to apply
Equation (5) to determine the feedthrough parasitic capacitance. Table 1.2-5 lists
the results for Cp0 for different feedthrough line widths and thicknesses. For the in-
terconnect line parameters used on the intermediate layer we obtain Cp = 1.737 pF
for l = 760 lm and Cp = 2.103 pF for l = 1 mm, respectively. Note that 0.58 pF has
been added in both cases to include two bondpads.
1.2.5.4.4 Self-inductance Ls
Analytical considerations of the self-inductance Ls of a wire interconnect is, in

general, not a straightforward task. The inductance is not a wire material parame-
ter but depends on the enclosed loop area and the relative permeability lr of the
material in which it is immersed. The self-inductance for any arbitrary closed
loop arrangement can be written as [50]
Table 1.2-5. Feedthrough parasitic capacitance per length (without bondpads). The bold
numbers are the default values and the respective parasitic capacitance per length
Cp0 (pF/mm) Thickness t (lm)
1 3 5
Width 30 1.142 1.182 1.200

w 40 1.487 1.523 1.545
(lm) 50 1.832 1.872 1.890
Figure 1.2-26. Different arrangements for interconnect and current return path. (a) Feed-
through interconnect on ground plane (bulk silicon); (b) two neighboring feedthrough inter-
connects; (c) two opposite feedthrough interconnects. The arrows indicate the current
through the feedthrough wire and the return path.
Ae
Ls l0 lr 8
w
where l0 is the permeability in air, Ae is the enclosed loop area [lm2], and lr is
the relative permeability of the enclosed medium. For simple wire arrangements,
formula sets exist which can directly be applied to determine the wire self-induc-
tance. In our case we can identify three loops of feedthrough interconnect and
current return path, which are shown in Figure 1.2-26:
(a) the current returns via the grounded bulk silicon;

(b) the current returns via a neighboring wire;
(c) the current returns via the opposite wire.
The first two arrangements are very simple, because wire and current return path
run parallel and can, therefore, be written as self-inductance per length, L0s . The
last one requires integration over the enclosed loop area.
Self-inductance of a Feedthrough on Ground Ls1 . According to [50], the self-in-

ductance per length of a wire and a ground plane is given by

ll h
L0s 0 SiO2 H=m 9
Kf w
where Kf is the so-called inductive fringe factor, l0 is the permeability in air and
lSiO2 is the relative permeability of silicon dioxide (Kf is dimensionless and de-
pends only on geometry. It is determined experimentally by measuring the charac-
teristic impedance Z0 of the loop [50]
r
1 0 h
Kf : 10
Z0er 1 e0 w
Table 1.2-6. Self-inductance per length of a feedthrough interconnect on grounded bulk

silicon. The bold numbers are the default width and the respective self-inductance per
length
Width w (lm)
30 40 50
L0s1 (pH/mm) 41.9 31.4 25.1
The respective numbers for Kf for a large range of h=w can be found in [50]).
The calculated numbers for L0s1 are listed in Table 1.2-6. The fringe factor Kf is
approximately 1 for all interconnect widths because of the small ratio h=w. The
self-inductances shown in Table 1.2-6 are very small because of the small en-
closed loop area (oxide thickness). The total self-inductances for our feedthrough
interconnects are in the range 23.9 pH for 760 lm and 31.4 pH for 1 mm line
length, respectively. The distance between feedthrough and current return path is
1 lm.
Self-inductance of Two Neighboring Feedthroughs, Ls2 . The self-inductance per

length of a loop consisting of two neighboring feedthrough interconnects is given
by [50]

0 lr l0 pd
Ls ln 1 H=m : 11
p wt
Here, besides the feedthrough width also its thickness affects L0s2 . Calculated val-
ues for L0s2 using Equation (11) are summarized in Table 1.2-7. Applying the geo-
metric dimensions of the feedthrough interconnects on the intermediate layer we
obtain 0.414 nH for the 760 lm wire and 0.546 nH for the 1 mm wire. The self-
inductance of two feedthrough wires is more than one order of magnitude larger
than that of a feedthrough wire on ground. The reason is the much larger distance
Table 1.2-7. Self-inductance per length of two adjacent feedthrough interconnects. The
distance is equal the wire width. The bold numbers are the default values and the respec-
tive self-inductance per length
L0s2 (nH/mm) Thickness t (lm)
1 3 5
Width 30 0.558 0.539 0.522

w 40 0.561 0.546 0.532
(lm) 50 0.562 0.550 0.540
Table 1.2-8. Self-inductance of two opposite feedthrough interconnects. The bold numbers
are the default width and the respective self-inductance
Width w (lm)
30 40 50
Ls3 (nH) 39.4 29.6 23.7
between the wire and the current return path (and, consequently, the enclosed
loop area), which for the arrangement in (a) is only 1 lm but for that in (b) is
30–50 lm.
Self-inductance of Two Opposite Feedthroughs, Ls3 . The enclosed loop area is giv-
en by the through-hole size, the wafer thickness, and the heights of the solder
bumps and the gold studs. The self-inductances for different wire widths were cal-
culated using Equation (8). The results are summarized in Table 1.2-8. This ar-
rangement yields the highest self-inductances of all three arrangements due to the
largest enclosed loop area.
1.2.5.4.5 Measurements
The wire series resistance Rs and the parasitic capacitance Cp have also been de-
termined experimentally. Both can strongly affect the performance of the inte-
grated microphone if not minimized according to the above specifications.
Series Resistance. For electroplated feedthroughs the actual (measured) series re-
sistance can deviate from the calculated value. There are several reasons for this.
First, the wire dimensions on the wafer can be different from those on the photo-
mask, which is mainly caused by diffraction effects, thick resist layers, and non-
optimized exposure conditions. Furthermore, if the interconnect wires have been
exposed to any oxygen plasma treatment, for example to remove resist residues, a
thick copper oxide might reduce the effective wire thickness. Another reason
might be differences in resistivity and/or density of the deposited metal compared
with those of the bulk material given in reference books. Metal electroplating
baths usually contain different additives which are co-deposited during electroplat-
ing. These additives optimize the composition/structure of the deposit with regard
to hardness, stress, brightness, etc. However, in most cases they exhibit a lower
conductivity than the actual metals to be deposited. Therefore, in cases where the
wire resistance is of crucial importance (as in our application), it is not sufficient
just to calculate the series resistance based on bulk material properties.
For the electrical measurements we used feedthrough test structures as shown
in Figure 1.2-27. These structures are designed for four-point measurements to
Figure 1.2-27. Feedthrough test structure for four-point measurements.
eliminate the contact resistances between the contact pads and the probes. We
used a Keithly 2000 Multimeter for the measurements. The test structures contain
four loops. The Cu thickness is about 3 lm. The total length is 3.9 mm. We used
three different wire widths of 30, 40, and 50 lm. For each of the three wire
widths we measured about 15 samples which were distributed over three wafers
from three different batches. The results are summarized in Table 1.2-9. The
resistivity of the electroplated Cu derived from the measured wire resistances
is slightly higher than that found in a reference book (1.8910 6 to
1.9810 6 X cm compared with 1.7710 6 X cm for un-annealed Cu [51]).
Based on these numbers, the real series resistances of the feedthrough inter-
connects on the intermediate layer are 0.138 X for a 760 lm wire and 0.182 X
for a 1 mm wire.
Parasitic Capacitance. The parasitic capacitance was determined indirectly by mea-

suring the capacitance between a large test structure and a feedthrough interconnect.
The capacitance of the test structure was determined analytically and experimentally,
Table 1.2-9. Average series resistance, standard deviation, and derived resistance per length
for electroplated Cu interconnects. The resistances were obtained by four-point measure-
ments. The bold numbers are the default width and the respective series resistance per
length
Width w (lm)
30 40 50
Rtest (mX) 912 712 573

SD ± 12 ± 22 ± 30
R0s (mX/mm) 234 182 147
yielding the same result of 70 pF. Since the parasitic capacitance of the feedthrough
wire is much smaller, the measured capacitance between a feedthrough interconnect
and a test structure is given entirely by the feedthrough capacitance. The measure-
ment device used was a HP 4280A 1 MHz C Meter/C-V Plotter. We measured
about 0.7 pF between the feedthrough interconnect (length 880 lm, width 40 lm)
and the test structure, which gives 0.7 pF for the feedthrough. The dielectric layer
(wet thermally grown SiO2 ) was 2 lm (test wafer) thick. The calculated capacitance
using the latter dimensions yields 0.84 pF. The two results are in fair agreement,
considering that the capacitance we are measuring is at the very low measurement
limit of the used device. Thus, even with proper correction for parasitic capacitances
a certain error must be taken into account.
1.2.5.4.6 Coupling
Coupling between adjacent interconnect wires is one of the most difficult prob-
lems in electrical design. We can distinguish two potential paths for coupling:
through the dielectric layer and through the air. Therefore, the impedance Zc be-
tween two adjacent wires can be written as
2ZSiO2 Zair
Zc 2ZSiO2 k Zair 12
2ZSiO2 Zair
assuming the bulk silicon to be loss-less. The impedance between wire and bulk
silicon is given by

1
ZSiO2 RSiO2 j xLs : 13
xCp
Ls and Cp for different wire geometries and arrangements are summarized above.
The calculation of the resistive loss RSiO2 between wire and bulk is very straight-
forward. The resistivity of wet thermal silicon dioxide is of the order of
3 1015 X cm and we obtain for RSiO2 approximately 1 PX for a 760 lm line and
0.75 PX for a 1 mm line.
The impedance in air between two wires is given by

1
Zair Rw j xLm 14
xCm
where Rw is the resistive loss in a possible condensed water film, Cm is the mu-
tual capacitance in air and Lm is the mutual inductance in air.
Resistance of Condensed Water Films. A possible condensed water film depends on

atmospheric conditions, such as relative humidity (RH), and also on surface condi-
tions and geometry. The RH describes the ratio of the partial water vapor pressure to
the saturated water vapor pressure [52]. The RH is a function of atmospheric pres-
sure and temperature. Consequently, the RH is not constant throughout a day but
changes according to these parameters, especially the temperature (for central Eu-
rope we find an RH between 95 and 20% for low and high day temperatures, respec-
tively). The saturated water vapor pressure increases with increasing temperature.
Inside the human ear, however, we find a constant temperature of about 37 8C. Con-
sequently, if the outside temperature is lower than 37 8C the RH inside the ear is
lower than that outside. If the temperature outside the ear is higher, the RH inside
the ear is higher. In addition to the atmospheric conditions, the enclosed volume
and the surface area inside the stack and also the surface conditions on the intermedi-
ate layer are of importance. The entire surface is covered by oxide, which means it is
hydrophilic (water attracking). Also, the ratio of enclosed volume-to-surface area
affects the thickness of the condensed water film. When this ratio increases, the
water film thickness increases and vice versa. The determination of the exact thick-
ness of the water film is an extremely difficult task (a point to start is to calculate the
number of monolayers of water according to [53]
NH2 O Vstack
b 15
Astack
Vstack is the enclosed inner stack volume [cm3] and Astack ist the enclosed inner
stack area [cm2]. One water molecule has a diameter of 3.85 Å [53]. The water
vapor concentration NH2 O can be derived from the partial water vapor pressure,
which is given by the RH). Moreover, it varies constantly by continuous adsorp-
tion and desorption (dynamic equilibrium) according to the atmospheric condi-
tions. Thus, for a rough estimation of the water film thickness it is more useful to
consider the borderline cases, which are:
(1) low RH (< 50%), less than one monolayer [54]; and
(2) high RH (> 90%), about 10 nm water film [55, 56].
Both values are for hydrophilic surfaces. In case (1) no conduction will take
place. Case (2), however, is much more severe. The resistivity of the condensed
water depends on the content of dissolved ions which can contribute to the con-
ductance process. Condensed water can be regarded as demineralized water,
which has a resistivity of approximately 8.3105 X cm (measured). The resulting
resistive loss Rw between two lines separated by 40 lm is then 4.4 GX (for a
10 nm water film). The thickness of 10 nm was observed on a flat silicon wafer
with infinite surrounding volume [55]. In our case the ratio of volume-to-surface
is much smaller, hence, the condensed water film would be much thinner. There-
fore, the resistance can be expected to be higher than the presented numbers.
Isolation resistance measurements were carried out using a HP 4140B pA meter/
DC voltage source. The measurement limit is in the higher (100s) fA range. The
temperature was about 20 8C. The RH was between 60% and 70%. All measurements
exceeded the above limit, which confirms an isolation resistance of the order of PX.
0
Mutual Capacitance. The mutual capacitance per length in air, Cm , is given by
[50]
0 p
Cm ereff e0 F=m 16
pd
ln 1
wt
where ereff is the effective relative dielectric constant, which accounts for non-
0
homogeneous dielectric surroundings. The results for Cm obtained using Equa-
tion (16) yield for all combinations of feedthrough widths and thicknesses ap-
proximately 20 fF/mm, and consequently 15 fF for a 760 lm wire. The effective
dielectric constant ereff was assumed to be 1 (this approximation is valid for
large ratios of wire-to-wire separation and substrate thickness ( 1). If this ratio
becomes small, ereff must be determined experimentally).
Mutual Inductance. The mutual inductance Lm is a measure of the flux introduced

into a closed loop 2 due to a current in a closed loop 1. For the mutual induc-
tance applies the same as for the self-inductance, that it is solely dependent on ge-
ometry and permeability. For non-trivial arrangements the Neumann equation has
to be solved [57]. In our case, however, we can make use of existing equation
sets again. The two loops are formed by two neighboring feedthrough intercon-
nects with the grounded bulk silicon as their respective current return path. The
distance between the two neighboring wires is constant and we can write for the
mutual inductance per length [50]
" 2 #
0 lr l0 h
Lm ln 1 : 17
4p d
The calculated numbers for L0m using Equation (17) are summarized in Table 1.2-10.
Results. Introducing the values for RSiO2 , Cp and Ls into Equation (13) we obtain
an impedance equal the resistive loss (ZSiO2 = RSiO2 ) for our frequency range,
which means 1 PX for a 760 lm wire and 0.75 PX for a 1 mm wire (w = 40 lm).
The impedance in air, Zair , is only of interest for high RH. Introducing the val-
ues for Rw, Cm , and Lm into Equation (14) we obtain Zair = 80 GX for f = 100 Hz
Table 1.2-10. Mutual inductance per length between two feedthrough interconnects on
grounded bulk silicon. The bold numbers are the default width and the respective mutual
inductance per length
Distance d (lm)
30 40 50
L0m (pH/mm) 0.11 0.06 0.04

A1.2.6 Summary and Future Outlook 63
and Zair = 4.4 GX for f = 20 kHz. The lower impedance for the higher frequency is
caused by a reduction of the capacitive loss.
For low RH the impedance between two adjacent feedthrough wires is equal
twice the impedance between wire and bulk silicon, Zc = 2 ZSiO2 . Thus, Zc is in the
range 1.5–2 PX. For high RH (10 nm condensed water film) the impedance in air,
Zair , is much lower than ZSiO2 and we obtain Zc = Zair . For our frequency range of
100 Hz–20 kHz the coupling impedance Zc varies between 80 and 4.4 GX. As
stated before, this is an extreme borderline case. Actual values for Zair can be ex-
pected to be much higher. This has to be proved by electrical measurements un-
der the same conditions which would occur inside a hearing aid instrument in a
human ear.
1.2.6 Summary and Future Outlook
The objective in the foregoing discussion was the development, realization, and
characterization of multiple wafer frontside to backside interconnects for MEMS
stacking applications. The interconnects are applied to an interconnect layer to be
utilized in an integrated microphone for hearing aid applications. This intercon-
nect layer, or intermediate layer, forms an essential part of the packaging concept.
The latter is based on stacking technologies in order to yield the smallest possible
volume size. Generally, stacking of different functionalities generates many chal-
lenges, which concern appropriate bonding techniques which are compatible with
all involved devices, and exchange of electrical and physical signals with the out-
side world. Comparing the results obtained with the requirements outlined at the
beginning of this chapter, we can say that the intermediate layer exhibits all nec-
essary functionalities.
Electrical connection through the intermediate layer is accomplished by multi-
ple Cu feedthroughs. The bondpads on either side of the intermediate layer are
provided with suitable metalizations for the respective bonding techniques. All
metalizations, except the plating base, are deposited by cost-effective electroplat-
ing processes. Electroplating is the only viable metal deposition technique that
can be used to optimize feedthrough interconnects in terms of series resistance
and parasitic capacitance. High deposition rates and controlled material consump-
tion make electroplating also a cost-effective deposition technique. Optimizing
electrical performance primarily concerns reducing the wire width and increasing
the wire thickness. The intermediate layer we used for the integrated microphone
exhibits wires with 40 lm width and 3 lm thickness. These dimensions yield
series resistances of the order of 0.1 X and parasitic capacitances of the order of
2 pF.
The coupling between two adjacent feedthrough interconnects has been investi-
gated analytically. The atmospheric conditions strongly affect the coupling. The
results obtained show low impedances between the wires for high relative humid-
ity due to a condensed water film. In order not to decrease the performance of the
microphone, an isolation resistance of the order of TX is required. Sensitivity
measurements before and after bonding of the interconnect layer to the micro-
phone showed identical results, proving sufficient isolation between the intercon-
nect wires.
In addition to the development and realization of a suitable integration and
packaging concept for the microphone, we devoted much attention to the general
applicability of our individual processes. As stated earlier, it is much more effi-
cient to develop simple and versatile (multi-purpose) packaging tools that can be
individually applied to a broad range of microsystems. We regard both the inter-
mediate layer and the feedthrough technology as such tools. The (eventually mod-
ified) intermediate layer can be used to protect any complicated micromechanical
device during subsequent processing. It adds negligible electrical parasitics. In
cases where stacking of different functionalities is demanded, the intermediate
layer can provide all necessary features to use optimum bonding techniques with-
out post-processing the active components.
We developed or optimized several EDPR processes for bulk micromachined
silicon wafers. In principle, these processes can be applied to any patterning pro-
cess on highly curved surfaces with inclined sidewalls.
Our feedthrough technology can be applied to any other device which is pro-
vided with anisotropically etched cavities or through-holes. The feedthrough pro-
cessing on active layers can be done either by integrating it into the device pro-
cessing or by add-on processing. It can, for example, readily be used for memory
stacks, as proposed in [9] (care has to be taken to clean the device wafer thor-
oughly after feedthrough processing from potassium ions which are present in the
Eagle 2005 Developer). The additional area consumption for the through-holes
can be reduced by arranging them (slot-like) at the chip edges.
Future work will mainly address reliability issues. This applies not only to the
feedthrough interconnects but also to the two bonding techniques used, CAB and
SBB. Although considerable progress has been achieved with both techniques,
they must still be considered to be at the development stage. For SBB this means
investigating solders other than pure tin. Especially electroplated Sn is prone to
disintegrate into a gray powder if exposed to temperatures below 13 8C [58]. This
process, also known as tin pest, is caused by the allotropic transformation of b-tin
into a-tin. Thereby, the volume is increased by *25%.
If corrosion of the Cu wires turns out to be a problem we have to modify our
metalization scheme or provide it with an overlay (passivation). The main criteria
for such an overlay are a low process temperature (to be compatible with the me-
talization) and good step coverage. Suitable candidates are, for example, PECVD
and APCVD (atmospheric pressure chemical vapor deposition) TEOS-O3 (Tetra-
ethyl orthosilicate/ozone) silicon dioxides, respectively.
In addition to reliability, which is most important, further activities could deal
with (more or less) novel metal deposition techniques, such as CVD Cu for the
feedthrough metalization. CVD TiN could be used as diffusion barrier and corro-
sion protection. Combined with the overlay, even multi-level feedthrough metal-
izations are conceivable.
A1.2.8 References 65
1.2.7 Acknowledgments
The work presented here was supported by the European collaboration project HI-
STACK (ESPRIT No. 25345) and the Danish collaboration project Microsystem
Center. We thank our project partners for their participation and fruitful discussions.
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List of Symbols and Abbreviations
Symbol Designation
C capacitance
Cp parasitic capacitance
f frequency
h thickness
Kf inductive fringe factor
l length
Ls self-inductance
NH2O water vapor concentration
RAC skin effect loss
RDC conductor loss
Rs series resistance
t thickness
Tg glass transition temperature
U bias voltage
weff effective wire width
Z impedance
a angle of incidence
b number of monolayers
Symbol Designation
d skin depth
e dielectric constant
l permeability
q resistivity
H Brewster angle
Abbreviation Explanation
ARC antiresistive coating
ASIC application-specific integrated circuit
CAB conductive adhesive bonding
CMOS complementary metal oxide semiconductor
CVD chemical vapor deposition
DRIE deep reactive ion etching
DUV deep ultraviolet
EDPR electrodepositable photoresist
IC integrated circuit
ISFET ion-selective field effect transistor
LOCOS local oxidation of silicon
LPCVD low-pressure chemical vapor deposition
MCM multichip module
MEMS microelectromechanical system
MPW multi-project wafer
PECVD plasma-enhanced chemical vapor deposition
RH relative humidity
RIE reactive ion etching
SBB solder bump bonding
SEM scanning electron microscopy
SIMS secondary ion mass spectroscopy
UBM under-bump metalization

Multiple Through-Wafer Interconnects For MEMS Applications

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1.

2 Multiple Through-wafer Interconnects

M. Heschel, Technical University of Denmark, Lyngby,

This chapter reports on the design and manufacturing of multiple

Keywords: Feedthroughs; Through-wafer interconnects; Stacking; In-

1.2.3 Stacking Approach for an Integrated Microphone . . . . . . . . . . . . . . . . 28

1.2.4 Intermediate Layer – Technical Aspects . . . . . . . . . . . . . . . . . . . . . . 34

1.2.5 Electroplated Through-wafer Interconnects . . . . . . . . . . . . . . . . . . . . 46

1.2.5.2 Electroplating Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

1.2.6 Summary and Future Outlook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

By most of the MEMS community, it is realized that packaging of microelectro-

1.2.2 Wafer Feedthrough Technologies

1.2.2.1 Backside Contacts

1.2.2.2 Single Feedthroughs

1.2.2.3 Multiple Feedthroughs

The major challenge in realizing multiple feedthroughs per through-hole is the

1.2.2.4 Buried Feedthroughs

1.2.3 Stacking Approach for an Integrated Microphone

As already shown in Figure 1.2-1, our approach for an integrated microphone is

Table 1.2-1. Feedthrough parameters seen from an electrical point of view

Interconnect Insulation Series Parasitic Application area Ref.

Backside contacts – wet etched holes

Table 1.2-2. Spatial feedthrough densities of selected technologies

Technology Feed- Substrate Wire Wire Ref. Normal-

Dry (RIE) Single 1000 14 1.4 n/a [17] 240

1.2.3.1 Topology Discussion

crophone and the backchamber. In addition to the worse electrical performance,

Figure 1.2-3. Schematic diagram of the chosen stacking topology.

1.2.3.2 Intermediate Layer

1.2.3.3 Interconnect Techniques

1.2.3.3.1 Solder Bump Bonding

Using solder bump bonding (SBB), it is possible to combine single interconnects

Figure 1.2-5. Metalization scheme of the intermediate layer.

1.2.3.3.2 Through-wafer Interconnects

1.2.3.3.3 Conductive Adhesive Bonding

1.2.4 Intermediate Layer – Technical Aspects

1.2.4.1 Bulk Micromachining

In our application, bulk micromachining means realizing both through-holes and

1.2.4.2 Bulk Contact

1.2.4.3 Eagle 2100 ED Electrodepositable Photoresist

Generally, an EDPR solution is made up of an emulsion working bath containing

1.2.4.3.1 Deposition Parameters

In addition to the bath composition, deposition temperature, voltage, and duration

Deposition time. At low bath temperatures, the deposition process is self-terminat-

Bath Composition Parameters. Controlling the bath composition means primarily

1.2.4.3.2 Baking Procedure

Already during electrodeposition coalescence of the resist film takes place by

1.2.4.4 Lithography on (111) Sidewalls

The main challenge in patterning multiple feedthroughs concerns the nonunifor-

Figure 1.2-15. Variation of exposure conditions along a feedthrough structure.

1.2.4.4.1 Light Reflections

upper part of the through-hole. The resulting feedthrough interconnects exhibit

1.2.4.4.2 Mask-Resist Distance

1.2.4.4.3 Relative Resist Thickness

1.2.4.5 Thin-film Feedthroughs

Etching as a patterning technique for multiple feedthroughs was described by

For multiple feedthroughs compatible with the bonding techniques described in

1.2.5 Electroplated Through-wafer Interconnects

1.2.5.1 Metalization Scheme and Processing

Feedthrough interconnects based on thin-film technologies always exhibit high se-

Figure 1.2-17. Simplified process sequence for electroplated feedthrough interconnects.

Stripping of mold 3 is not as straightforward as stripping of the other two

1.2.5.2 Electroplating Aspects