2022 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)

August 29 - 31, 2022, Busan, Korea

Two-stage CMOS/GaAs HBT Doherty Power

Amplifier Module for 5G Handsets
2022 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) | 978-1-6654-6649-3/22/$31.00 ©2022 IEEE | DOI: 10.1109/RFIT54256.2022.9882351

Hyeongjin Jeon Jongyun Na Hansik Oh Youngoo Yang

dept. Electrical and Computer dept. Electrical and Computer Samsung Electronics, Network dept. Electrical and Computer
Engineering Engineering Business Engineering
Sungkyunkwan university Sungkyunkwan university Suwon, Korea Sungkyunkwan university
Suwon, Korea Suwon, Korea hansik.oh@samsung.som Suwon, Korea
cnrrn89@skku.edu realiuz@skku.edu yang09@skku.edu
(corresponding)

Abstract—This paper presents a two-stage Doherty power Laminate

’Ƅ'
GaAs HBT

amplifier module (PAM) in CMOS SOI and GaAs HBT Impedance Post RF OUT
matching Carrier matching
technologies for 5G handsets. While the driver amplifier is RF IN
CMOS 0˚ Z0’ Ƅ network ZC,L’ Ƌ network

implemented using SOI CMOS for low cost, the carrier and
peaking amplifiers are implemented using InGaP/GaAs HBT for
high efficiency and linearity. The proposed Doherty PAM has a
differential driver whose two output terminals are connected to
the input ports of the carrier and peaking amplifiers, respectively.
For the 3.35 GHz continuous-wave (CW) signal, the proposed
PAM exhibited a power-added efficiency (PAE) of 30.3% and a
power gain of 29.8 dB at a peak output power of 32.2 dBm. Using
the 5G New Radio (NR) signal with a peak-to-average power ratio
(PAPR) of 9.7 dB and a signal bandwidth of 100 MHz, a linear
gain of more than 19.5 dB and a linear output power of more than
17 dBm in the range of from 3.15- to 4.15 GHz with a supply
voltage of 4.5 V.
Keywords— Power amplifier module, Doherty power
amplifier, SOI CMOS, InGaP/GaAs HBT, 5G NR handset.
I. INTRODUCTION
Most commercial PAMs for wireless handset applications
have been designed based on a two-stage class AB amplifier
using an InGaP/GaAs HBT technology, since. The GaAs-based
PAMs can deliver inherently higher efficiency and lower
distortion characteristics than other technologies such as
CMOS-based PAMs can. Since wireless communication
systems have required higher data rates using the modulated
signal with higher PAPR and wider signal bandwidth, power
amplifiers (PAs) are required to operate with high efficiency
especially with large output power back-off (OBO) regions. To
obtain high efficiency using the signals with high PAPR,
Doherty PA has been popularly adopted. Despite its simple
structure, the Doherty PAM can deliver high efficiency at large
OBO using load impedance modulation [1]-[4].
New PAM architectures to reduce the cost and size while
maintaining performance levels have been developed. Doherty
PAMs with a single driver [4]-[6] and a CMOS/GaAs hybrid
Doherty PAM [7]-[8] have been proposed. For the hybrid
approach using CMOS and GaAs technologies, the RF driver is
implemented using a CMOS process while the high power
Drive
’Ƅ' + 90 ˚
-180 ˚ Impedance
Peaking
Z0’ β
matching
network ZP,L’ Ƌ +90 ˚
Fig. 1. Diagram of the proposed Doherty PAM.
output stage is implemented using an InGaP/GaAs HBT
technology. Since the CMOS driver amplifier uses a differential
structure to obtain high power and efficiency, an issue of large
size due to the balun, the inter-stage matching network which
may include a Wilkinson power divider remains.
In this paper, a two-stage CMOS/GaAs hybrid Doherty
PAM presented. The proposed Doherty PAM has a differential
driver with two output terminals which are connected the input
ports of the carrier and peaking amplifiers, respectively. The
interstage matching network consists of offset line and
impedance matching networks without a Wilkinson power
divider or even a balun. Consequently, a small size and low cost
can be achieved. The measurement results of the implemented
Doherty PAM will be presented.
II. CIRCUIT DESIGN
Fig. 1 shows a diagram of the proposed Doherty PAM. The
module contains a CMOS differential driver IC, an InGaP/GaAs
HBT IC for the carrier and peaking amplifiers, and the interstage
and load networks on a laminate. The driver amplifier including
an input transformer is designed using SOI CMOS process for
low cost. The carrier and peaking amplifiers, and their input
matching networks are designed using GaAs HBT process for
high efficiency and linearity. The offset line at the interstage and
the load network are designed using 6-layer laminate.

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 bypass 4.5V
2.8V, 4.5V

1.93 nH
Bias 0.46 nH

Offset line Impedance matching network 2.3 pF

1.9 pF RF OU
1.1 pF 2.9 pF 18.2 pF
2 nH 2 nH 0.63 nH 0.12 nH
RF IN 250 fF
1.37 nH
1.05 nH
6.7 pF
4.5V
0.9 pF

250 fF 10 pF
Offset line Impedance matching network

0.97 nH 0.79 nH 31.5 pF

0.3 pF 0.3 pF 2.0 pF 0.17 nH

Bias : can be merged

4.5V
1.6~2V, 4.5V

Fig. 2. Schematic of the proposed Doherty PAM.

(a)

Bypass cap

Bypass cap

Load network

GaAs IC
2.5 mm

CMOS IC

Bypass cap
(b)

3 mm

Fig. 3. Photograph of the proposed Doherty PAM.

Fig. 2 shows a schematic of the proposed Doherty PAM.

Since the two differential output terminals of the CMOS driver
amplifier are directly connected to the main stage, the signals
have an initial phase difference of 180º. The interstage matching
network consists of offset lines and partial impedance matching
networks. The impedance matching networks at the inter-stage
have 2-section structures for broadband characteristics. The
offset lines are realized using lumped π-type network. Since two
components in parallel at the offset lines and the inter-stage
matching networks can be merged, the final structure can be
more compact with reduced loss. (c)
Fig. 4. Measured performances of the PAM using the 5G NR
signal with a bandwidth of 100 MHz and a PAPR of 9.7 dB:
III. IMPLEMENTATION AND MEASUREMENT RESULTS (a) gain and linear output power, (b) PAE, (c) ACLR.
The two-stage Doherty PAM was implemented on a 3 × 2.5
mm2 laminate as shown in Fig. 3. The CMOS driver IC
including the input transformer was fabricated using Global networks and the active bias circuits. All the capacitors at the
Foundries is 130-nm SOI process and has a size of 0.8 × 0.98 load network were integrated in the GaAs die except for only
mm2. The InGaP/GaAs HBT IC was fabricated using Winsemi’s two capacitors which are the series capacitor at the post
2-mm process and is based on the HBT power transistors with a matching network and the bypass capacitor. Measurements
total emitter area of 2200 mm2, the inter-stage matching using the 5G NR modulation signal, which has a modulation

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 TABLE I MEASUREMENT RESULTS COMPARED TO THE PREVIOUS STUDIES impedance matching networks without a Wilkinson power
Ref. [1] [3] This work divider or a balun. Consequently, a small size and low case can
be simultaneously achieved. The design driver amplifier IC and
Frequency main Doherty IC were fabricated using commercial SOI CMOS
3.75 2.45 3.15-4.15
(GHz)
and InGaP/GaAs HBT process, respectively. The implemented
Process
InGaP/GaAs InGaP/GaAs CMOS/InGaP/GaAs PAM was evaluated using the 5G NR modulated signal, which
HBT HBT HBT hybrid has a modulation bandwidth of 100 MHz with a PAPR of 9.7dB.
Technique DPA DPA DPA A linear gain of more than 19.5 dB and a linear output power of
more than 17 dBm at the relatively broad frequency range of
Vcc (V) 3.8 5 4.5 3.15-4.15 GHz with a supply voltage of 4.5 V were obtain.
Modulation 5G NR 64 QAM 5G NR
Bandwith
100 40 100 REFERENCES
[MHz]
PAPR [dB] 6.7 - 9.7 [1] K. Takenaka et al., “Parallel Plate Coupler Based Doherty Power
Amplifier Design for 5G NR Handset Applications,” in IEEE MTT-S Int.
Pout@Plinear Microw. Symp. Dig., Oct. 2021, pp. 523-526.
26 26 17
(dBm) [2] S. Imai et al., “Bandwidth optimization of Doherty power amplifier based
on source converters for 5G mobile handsets,” IEEE Trans. Microw.
PAE @
32 21 20 Theory Techn., vol. 70, no. 1, pp. 813-826, Jan. 2022.
Plinear (%)
[3] S. Wan et al., “A High-Efficiency Two-Stage GaAs HBT Doherty Power
Amplifier With Thermal Compensation for WLAN Application,” in IEEE
MTT-S Int. Wireless Symp. Dig., Aug. 2021, pp. 1-3.
bandwidth of 100 MHz with a PAPR of 9.7 dB were carried out.
The measurement results are shown in Fig. 4. The Doherty PAM [4] K. J. Chuang et al., “An Efficient and Linear 24.4 dBm Ka-Band GaAs
Power Amplifier for 5G Communication,” in IEEE MTT-S Radio Freq.
maintains the gain of more than 19.5 dB and the linear output Integr. Techn. Symp. Dig., Oct 2021, pp. 1-3.
power more of than 17 dBm throughout the frequency band of [5] A. Serhan et al., “A Broadband High-Efficiency SOI-CMOS PA Module
from 3.15 to 4.15 GHz. The PAE of above 26% and the adjacent- for LTE/LTE-A Handset Applications,” in Proc. IEEE Radio Freq. Integr.
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achieved at the linear output power level at the same frequency [6] C. H. Kim and B. Park, “Fully-integrated two-stage GaN MMIC Doherty
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TABLE I summarizes the measurement results compare to [7] D. Leipold et al., “A WCDMA 41% power efficiency direct DC coupled
the previous studies about Doherty PAM for handset hybrid CMOS/GaAs power amplifier with pre-distortion linearization,” in
applications. The proposed Doherty PAM in this work achieved Proc. IEEE Radio Freq. Integr. Circuits Symp. (RFIC), Jul. 2012, pp.
broader bandwidth than those of the previous works. 279–282.
[8] K. Kato et al., “A two-power-mode Si-CMOS/GaAs-HBT hybrid power
amplifier module for 0.9-GHz-band W-CDMA handsets applications,” in
Proc. IEEE Asia–Pacific Microw. Conf., Nov. 2014, pp. 668–670.
IV. CONCLUSION
The two-stage CMOS/GaAs hybrid Doherty PAM presented.
The interstage network only consists of offset lines and partial

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