CPE/EE 427, CPE 527 VLSI Design I Sequential Circuits: - Combinational Logic - Sequential Logic

CPE/EE 427, CPE 527 VLSI Design I Sequential Circuits
Department of Electrical and Computer Engineering University of Alabama in Huntsville

Aleksandar Milenkovic ( www.ece.uah.edu/~milenka )
Sequencing Combinational logic

output depends on current inputs
Sequential logic
output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline
clk in CL out CL CL clk clk clk
Finite State Machine
Pipeline
11/1/2006
VLSI Design I; A. Milenkovic
Sequencing Cont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable
Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses
This is called wave pipelining in circuits In most circuits, dispersion is high

Delay fast tokens so they dont catch slow ones.
11/1/2006 VLSI Design I; A. Milenkovic 3
Sequencing Overhead Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay
Called sequencing overhead
Some people call this clocking overhead

But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence
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Sequential Logic
Inputs Combinational Logic

State Registers
Outputs
Current State
Next State
clock
Timing Metrics
In D Q Out
clock
tsu thold
clock
time
In
data stable tc-q
time
output stable
Out
output stable
time
System Timing Constraints

Inputs Combinational Logic
State Registers
Outputs
Current State
Next State T (clock period)
clock tcdreg + tcdlogic thold

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T tc-q + tplogic + tsu

VLSI Design I; A. Milenkovic 7
Sequencing Elements Latch: Level sensitive

a.k.a. transparent latch, D latch
Flip-flop: edge triggered

A.k.a. master-slave flip-flop, D flip-flop, D register
Timing Diagrams
Transparent Opaque Edge-trigger
D
clk Latch Q D
clk Flop Q
clk D Q (latch) Q (flop)
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Sequencing Elements Latch: Level sensitive

a.k.a. transparent latch, D latch
Flip-flop: edge triggered

A.k.a. master-slave flip-flop, D flip-flop, D register
Timing Diagrams
Transparent Opaque Edge-trigger
D
clk Latch Q D
clk Flop Q
clk D Q (latch) Q (flop)
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Latch Design Pass Transistor Latch Pros

+ +
D
Cons

Latch Design Pass Transistor Latch Pros

+ Tiny + Low clock load
D
Cons

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Vt drop nonrestoring backdriving output noise sensitivity dynamic diffusion input

Used in 1970s
11
Latch Design Transmission gate

+ D Q
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12
Latch Design Transmission gate

+ No Vt drop - Requires inverted clock
D Q
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13
Latch Design Inverting buffer

+ + + Fixes either

D X Q Q
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14
Latch Design Inverting buffer

+ Restoring + No backdriving + Fixes either
Output noise sensitivity Or diffusion input
D X Q Q
Inverted output
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15
Latch Design Tristate feedback

+
D X Q
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Latch Design Tristate feedback

+ Static Backdriving risk
D X Q
Static latches are now essential
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17
Latch Design Buffered input

+ +
D X Q
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Latch Design Buffered input

+ Fixes diffusion input + Noninverting
D X Q
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19
Latch Design Buffered output

+
D X Q
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10
Latch Design Buffered output

+ No backdriving
D X Q
Widely used in standard cells

+ Very robust (most important) - Rather large - Rather slow (1.5 2 FO4 delays) - High clock loading
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Latch Design Datapath latch

+ D X Q
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11
Latch Design Datapath latch

+ Smaller, faster - unbuffered input
D X Q
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23
Flip-Flop Design Flip-flop is built as pair of back-to-back latches

D X Q
D X
Q Q
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12
Enable Enable: ignore clock when en = 0

Mux: increase latch D-Q delay Clock Gating: increase en setup time, skew
Symbol Multiplexer Design Clock Gating Design en Latch D Q 0 en 1 D Latch Q D Latch en Flop Q
en
Flop D Flop Q en D 1 0 Q D
en
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25
Reset Force output low when reset asserted Synchronous vs. asynchronous
Symbol Synchronous Reset Asynchronous Reset reset D reset D Latch D Q D Flop Q
reset Q reset D
reset Q Q
Q D
reset
reset
reset
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26
13
Set / Reset Set forces output high when enabled Flip-flop with asynchronous set and reset
set D reset reset Q
set
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Sequencing Methods Flip-flops 2-Phase Latches Pulsed Latches

Tc
Flop
Combinational Logic
1 tnonoverlap 2 1 Latch Combinational Logic Half-Cycle 1 Tc/2 2 Latch Combinational Logic Half-Cycle 1 1 Latch p Combinational Logic Latch tnonoverlap
tpw p Latch
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Flop
Flip-Flops 2-Phase Transparent Latches Pulsed Latches
clk clk clk
28
14
Timing Diagrams
Contamination and Propagation Delays

tpd tcd tpcq tccq tpdq tpcq tsetup thold
Logic Prop. Delay Logic Cont. Delay Latch/Flop Clk-Q Prop Delay Latch/Flop Clk-Q Cont. Delay Latch D-Q Prop Delay Latch D-Q Cont. Delay Latch/Flop Setup Time Latch/Flop Hold Time
A A Combinational Logic Y Y tcd
tpd
clk D Flop Q
clk D
tsetup
thold
tpcq Q tccq
clk Latch D Q
clk D
tsetup tccq tpcq tcdq tpdq
thold
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29
Max-Delay: Flip-Flops
F1
Combinational Logic Tc
clk Q1 D2
tpcq tpd
tsetup
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F2
t pd Tc ( ) 14 244 4 3
sequencing overhead
clk Q1 D2
clk
30
15
Max-Delay: Flip-Flops
F1
sequencing overhead
Combinational Logic Tc
clk Q1 D2
tpcq tpd
tsetup
11/1/2006
F2
t pd Tc ( tsetup + t pcq ) 14 24 3
clk Q1 D2
clk
31
Max Delay: 2-Phase Latches
L1
L2
sequencing overhead
1 2 Tc D1 Q1 D2 Q2 D3 tpdq1 tpd1 tpdq2 tpd2
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L3
t pd = t pd 1 + t pd 2 Tc ( ) 14 244 4 3
1 D1 Q1 Combinational Logic 1 D2
2 Q2 Combinational Logic 2 D3
1 Q3
32
16
Max Delay: 2-Phase Latches
t pd = t pd 1 + t pd 2 Tc
sequencing overhead
2t (123)
pdq
1 L1 D1 Q1 Combinational Logic 1 D2
2 L2 Q2 Combinational Logic 2 D3
1 L3 Q3
1 2 Tc D1 Q1 D2 Q2 D3 tpdq1 tpd1 tpdq2 tpd2
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33
Max Delay: Pulsed Latches
t pd Tc max ( ) 3 1444 24444 4

sequencing overhead
p L1 D1 Q1 Combinational Logic Tc D1 tpdq tpd D2
p L2 Q2
(a) tpw > tsetup
Q1 D2 p tpcq Q1
Tc tpd
tpw tsetup
(b) tpw < tsetup D2
11/1/2006
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17
Max Delay: Pulsed Latches
t pd Tc max ( t pdq , t pcq + tsetup t pw ) 14444 24444 3

sequencing overhead
p L1 D1 Q1 Combinational Logic Tc D1 tpdq tpd D2
p L2 Q2
(a) tpw > tsetup
Q1 D2 p tpcq Q1
Tc tpd
tpw tsetup
(b) tpw < tsetup D2
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35
Min-Delay: Flip-Flops
clk
tcd
F1
Q1
CL
clk F2 clk Q1 tccq D2 tcd thold D2
11/1/2006
36
18
Min-Delay: Flip-Flops
clk
tcd thold tccq
F1
Q1
CL
clk F2 clk Q1 tccq D2 tcd thold D2
11/1/2006
37
Min-Delay: 2-Phase Latches
L1
tcd 1,tcd 2
1 Q1 CL
Hold time reduced by nonoverlap Paradox: hold applies twice each cycle, vs. only once for flops. But a flop is made of two latches!
2 L2 tnonoverlap D2
1 2
tccq
Q1 D2 thold
tcd
11/1/2006
38
19
Min-Delay: 2-Phase Latches
L1
tcd 1,tcd 2 thold tccq tnonoverlap
1 Q1 CL
Hold time reduced by nonoverlap Paradox: hold applies twice each cycle, vs. only once for flops. But a flop is made of two latches!
2 L2 tnonoverlap D2
1 2
tccq
Q1 D2 thold
tcd
11/1/2006
39
Min-Delay: Pulsed Latches
p L1
tcd
Q1
CL
Hold time increased by pulse width
p L2 tpw thold Q1 tccq D2 tcd D2
11/1/2006
40
20
Min-Delay: Pulsed Latches
p L1
tcd thold tccq + t pw
Q1
CL
Hold time increased by pulse width
p L2 tpw thold Q1 tccq D2 tcd D2
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Time Borrowing In a flop-based system:

Data launches on one rising edge Must setup before next rising edge If it arrives late, system fails If it arrives early, time is wasted Flops have hard edges
In a latch-based system
Data can pass through latch while transparent Long cycle of logic can borrow time into next As long as each loop completes in one cycle
11/1/2006
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21
Time Borrowing Example

1 2 1 Latch (a) Combinational Logic 2 Latch Combinational Logic 1 Latch
Borrowing time across half-cycle boundary 1 Latch (b) Combinational Logic 2 Latch
Borrowing time across pipeline stage boundary
Combinational Logic
Loops may borrow time internally but must complete within the cycle
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43
How Much Borrowing?
2-Phase Latches
tborrow Tc ( tsetup + tnonoverlap ) 2
D1
2 L2 Q2
Pulsed Latches
tborrow t pw tsetup
tnonoverlap Tc Tc/2 Nominal Half-Cycle 1 Delay tborrow tsetup
D2
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22
Clock Skew We have assumed zero clock skew Clocks really have uncertainty in arrival time
Decreases maximum propagation delay Increases minimum contamination delay Decreases time borrowing
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45
Skew: Flip-Flops
clk clk Combinational Logic Tc clk tpcq Q1 D2 clk F1 Q1 CL tpdq tsetup tskew F2 Q1 D2
t pd Tc ( t pcq + tsetup + tskew ) 144 2444 4 3

sequencing overhead
tcd thold tccq + tskew
F2 tskew thold tcd
D2
clk Q1 tccq D2
11/1/2006
F1 clk
46
23
Skew: Latches
2-Phase Latches
t pd Tc
sequencing overhead
1 L1 D1 Q1 Combinational Logic 1 D2
1 L3 Q3
2t (123)
pdq
1 2
tcd 1 , tcd 2 thold tccq tnonoverlap + tskew tborrow Tc ( tsetup + tnonoverlap + tskew ) 2
Pulsed Latches
t pd Tc max ( t pdq , t pcq + tsetup t pw + tskew ) 1444442444443

sequencing overhead
tcd thold + t pw tccq + tskew tborrow t pw ( tsetup + tskew )

Two-Phase Clocking If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speed In this class, working chips are most important
No tools to analyze clock skew
An easy way to guarantee hold times is to use 2phase latches with big nonoverlap times Call these clocks 1, 2 (ph1, ph2)
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48
24
Safe Flip-Flop In class, use flip-flop with nonoverlapping clocks

Very slow nonoverlap adds to setup time But no hold times
In industry, use a better timing analyzer

Add buffers to slow signals if hold time is at risk
2 D 2 X 2 1 1 1 Q Q
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Summary Flip-Flops:
Very easy to use, supported by all tools
2-Phase Transparent Latches:

Lots of skew tolerance and time borrowing
Pulsed Latches:
Fast, some skew tol & borrow, hold time risk
11/1/2006
50
25

CPE/EE 427, CPE 527 VLSI Design I Sequential Circuits: - Combinational Logic - Sequential Logic

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CPE/EE 427, CPE 527 VLSI Design I Sequential Circuits: - Combinational Logic - Sequential Logic

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CPE/EE 427, CPE 527 VLSI Design I Sequential Circuits

Department of Electrical and Computer Engineering University of Alabama in Huntsville

Sequencing Combinational logic

Finite State Machine

VLSI Design I; A. Milenkovic

VLSI Design I; A. Milenkovic

This is called wave pipelining in circuits In most circuits, dispersion is high

Some people call this clocking overhead

VLSI Design I; A. Milenkovic

VLSI Design I; A. Milenkovic

Inputs Combinational Logic

data stable tc-q

VLSI Design I; A. Milenkovic

System Timing Constraints

Next State T (clock period)

clock tcdreg + tcdlogic thold

T tc-q + tplogic + tsu

Sequencing Elements Latch: Level sensitive

Flip-flop: edge triggered

clk D Q (latch) Q (flop)

VLSI Design I; A. Milenkovic

VLSI Design I; A. Milenkovic

Sequencing Elements Latch: Level sensitive

Flip-flop: edge triggered

clk D Q (latch) Q (flop)

VLSI Design I; A. Milenkovic

Latch Design Pass Transistor Latch Pros

VLSI Design I; A. Milenkovic

Latch Design Pass Transistor Latch Pros

Vt drop nonrestoring backdriving output noise sensitivity dynamic diffusion input

Latch Design Transmission gate

VLSI Design I; A. Milenkovic

VLSI Design I; A. Milenkovic

Latch Design Transmission gate

VLSI Design I; A. Milenkovic

Latch Design Inverting buffer

VLSI Design I; A. Milenkovic

VLSI Design I; A. Milenkovic

Latch Design Inverting buffer

VLSI Design I; A. Milenkovic

Latch Design Tristate feedback

VLSI Design I; A. Milenkovic

VLSI Design I; A. Milenkovic

Latch Design Tristate feedback

Static latches are now essential

VLSI Design I; A. Milenkovic

Latch Design Buffered input

VLSI Design I; A. Milenkovic

VLSI Design I; A. Milenkovic

Latch Design Buffered input

VLSI Design I; A. Milenkovic

Latch Design Buffered output

VLSI Design I; A. Milenkovic

VLSI Design I; A. Milenkovic

Latch Design Buffered output

Widely used in standard cells

VLSI Design I; A. Milenkovic

Latch Design Datapath latch

VLSI Design I; A. Milenkovic

VLSI Design I; A. Milenkovic

Latch Design Datapath latch

VLSI Design I; A. Milenkovic