Integrated Circuits

ECE481
Fall 2021
M2: Interconnects
Lecture 1
Interconnect Parasitics
DiaaEldin Khalil
Ain Shams University
Integrated Circuits Laboratory

D. Khalil ECE481 – M2 Lecture 1 1

Outline
• Introduction
• Parasitic Capacitance
– Parallel Plate Capacitance
– Fringe Capacitance
– Coupling Capacitance
– Coupling Capacitance Effects
– Capacitance Tables
– Modeling Capacitance
• Parasitic Resistance
– Parasitic Wire Resistance
– Skin Effect
– Parasitic Contact Resistance
• Parasitic Inductance
– Parasitic Inductance
– When to Consider Inductance
• Wire Scaling

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 Introduction

• IC wiring uses multiple layers of metal

patterned to create lines, vias vertically
connect lines across adjacent layers
• The number of metal layers keeps increasing
• Thickness, width, and spacing are not equal:
– Bottom (lower) layers: thin, narrow, and short
Within cells and between close cells
– Mid layers: thicker, wider, and longer
Between macros and far cells Intel 90nm
– Top layers: thickest, widest, and longest
Mainly for supplies, clocks, and global signals
• IC wiring suffers from parasitic resistance,
capacitance, and inductance
• IC wiring must be modeled to include the
effects of parasitics in simulations
Intel 45nm
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Outline
• Introduction
• Parasitic Capacitance
– Parallel Plate Capacitance
– Fringe Capacitance
– Coupling Capacitance
– Coupling Capacitance Effects
– Capacitance Tables
– Modeling Capacitance
• Parasitic Resistance
– Parasitic Wire Resistance
– Skin Effect
– Parasitic Contact Resistance
• Parasitic Inductance
– Parasitic Inductance
– When to Consider Inductance
• Wire Scaling

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 Parasitic Capacitance
• Parasitic capacitance of metal line
is related to electric field to nearby
metal structures and can be divided
into 3 components:
– Parallel plate capacitance
– Fringe capacitance
– Coupling (inter-wire) capacitance

• Parasitic capacitance is proportional to the length of the wires

and is a function of the fan-out from the driving gate and the
number of fan-out gates.

transmitters receivers

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Parallel Plate Capacitance

• Capacitance to area lying directly below and above the line

• In dense routing cases (typical), the bottom and top metal layers
are considered as plates
• Modeled as capacitance to ground

Cpp /dL = W/td

d : dielectric constant
(3.9 for SiO2)
L : interconnect length

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 Fringe Capacitance

• Capacitance to areas lying not directly below and above the line
• Mainly from sidewalls
• Modeled as capacitance to ground as well

Cf /dL = 1.4*(H/td)0.222
d : dielectric constant
(3.9 for SiO2)
L : interconnect length

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Fringe Capacitance

• Cpp is proportional to W, while Cf is proportional to H

• For large W/H, Ctotal approaches Cpp
• For W/H < 1.5, Cf dominates Cpp
• Because of Cf , Ctotal is nearly
constant for W < td C pp+2Cf

• Increasing WH lowers H/td = 1

parasitic resistance, while
decreasing W improves H/td = 0.5
integration density Cpp
 In modern process,
W/H<1
• Cannot neglect
fringe capacitance
1.5

W/td
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 Coupling Capacitance

• Capacitance to adjacent metal lines

• Mainly from sidewalls
• Accurately modeled as capacitance to the adjacent line
• Sometimes approximated as capacitance to ground (not good)

Cc /dL = H/S
d : dielectric constant
(3.9 for SiO2)
L : interconnect length

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Coupling Capacitance

• Cpp is proportional to W, while Cc is proportional to H

• For large W/H, Ctotal approaches Cpp
• For W/H < 1.75, Cc dominates Cpp
• Because of Cc , Ctotal starts
increasing for W/H < 1.75

• Increasing WH lowers

parasitic resistance, while
decreasing W improves
integration density
 In modern process,
W/H<1
• Cannot neglect
coupling capacitance

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 Capacitance Tables
Parallel plate and fringe capacitances for typical 0.25um process
Field Active Poly Al1 Al2 Al3 Al4
Poly 88 cpp in aF/m2
54 2cf in aF/m
Al1 30 41 57 (row: top plate & column: bottom plate)
40 47 54
Al2 13 15 17 36
25 27 29 45
Al3 8.9 9.4 10 15 41
18 19 20 27 49
Al4 6.5 6.8 7 8.9 15 35
14 15 15 18 27 45
Al5 5.2 5.4 5.4 6.6 9.1 14 38
12 12 12 14 19 27 52
Coupling capacitance for typical 0.25um process
Poly Al1 Al2 Al3 Al4 Al5
cc in aF/m
40 95 85 85 85 115 (for min-spaced wires)

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Modeling Capacitance

Several ways to model parasitic capacitance:

• Rapid (rough) calculations using equations
• More accurate calculations using capacitance tables
• Capacitance extraction using CAD tools
– Determine a set of common geometries
with different wire widths, spacings, and upper/lower neighbors
– Run 2D or 3D field solver for these geometries
– Use interpolation and extrapolation for similar geometries
• Capacitance modeling using field solver
– Most accurate
– Computational cost is huge
(cannot be used for large number of nets)

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 Coupling Capacitance Effects

• Coupling capacitance is a little tricky to handle in delay and power

calculations since the other end is connected to a node and not
connected to ground
• For node A, the effective capacitance to ground corresponding
to coupling capacitance Cc depends on the activity on node B
• If A switches & B steady
– Cc can be considered easily
• If A & B switch in same direction
– Cc is neglected as it suffers
no change in potential
• If A & B switch in opposite direction
– Cc suffers twice the change in potential
• Relative switching time adds more complexity
• Incorrect handling can have significant effects on delay and power

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Coupling Capacitance Effects

• Coupling capacitance causes (crosstalk) where a switching wire

(aggressor) causes noise on one or more coupled wires (victims)

• If crosstalk is less than victim (Cc = Cgnd-v = Cgnd-a)

fan-out gate noise margin,
nothing happens
• If crosstalk is more, circuit
operation can be affected
depending on duration

• Static CMOS logic is immune, eventually settle to correct output

However, delay and power increase
• Dynamic CMOS logic is not immune, cannot recover
• Charge or level sensitive circuits (like memories) can be affected
• Need to check and quantify (using simulations)

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 Outline
• Introduction
• Parasitic Capacitance
– Parallel Plate Capacitance
– Fringe Capacitance
– Coupling Capacitance
– Coupling Capacitance Effects
– Capacitance Tables
– Modeling Capacitance
• Parasitic Resistance
– Parasitic Wire Resistance
– Skin Effect
– Parasitic Contact Resistance
• Parasitic Inductance
– Parasitic Inductance
– When to Consider Inductance
• Wire Scaling

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Parasitic Wire Resistance

rL r L
• Resistance R is given by: R= =
A HW
• Since H is constant for a metal layer, Rsheet
Sheet resistance (Rsheet or R ) r/H L
is also constant for that metal layer
H
• Sheet resistance is a very useful definition
• Sheet resistance unit is / W
• Using Rsheet, R is calculated knowing just L/W
• Since we use L/W, R of = R of =R

• This is equivalent to simply treating wire resistance as squares

(each of value R ) connected in series
• EG: In the figure, L/W = 4 squares  R = 4 R
• Note: L, T, and + wire sections need special treatment
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 Parasitic Wire Resistance
Material Sheet Res. (/ )
Material (-m)
n, p well diffusion 1000 to 1500
Silver (Ag) 1.6 x 10-8 n+, p+ diffusion 50 to 150
Copper (Cu) 1.7 x 10-8 n+, p+ diffusion with silicide 3 to 5
Gold (Au) 2.2 x 10-8 polysilicon 150 to 200
Aluminum (Al) 2.7 x 10-8 polysilicon with silicide 4 to 5
Tungsten (W) 5.5 x 10-8 Aluminum 0.05 to 0.1

Resistivity Sheet Resistance

• Al was initially used for low cost and easier process

• Cu is now mainly used by modern process for superior conductivity
• Poly should only be used for short wires
• Diffusion should not be used except for extremely short distance
• Poly and diffusion are also used to create integrated resistors

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Skin Effect

• Skin effect is an issue where, at high frequency, current flows

primarily on conductor surface with current density falling off
exponentially with depth into conductor
• Skin effect is an issue for large wires carrying high frequency
signals such as clock
• At skin depth d, current is equal to e-1 its nominal value
• Skin effect starts at frequency fs , where skin depth d is equal to
half the smallest dimension of the wire
W EG:
ρ
δ For Al at 1GHz,
πfμ
H d = 2.6m
fs = 4 r / (  (min(W,H))2)
where  = 4 x 10-7 H/m
Overall cross section is ~ 2(W+H)d

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 Skin Effect
1000
Al wires

Resistance Increase (%)

H = 0.7um
100

10

1 W = 1 um
W = 10 um
W = 20 um
0,1
1E8 1E9 1E10
Frequency (Hz)
• Resistance increases more for wider wires
• 30% resistance increase for 20m wide wire at 1GHz
• Less than 2% resistance increase for 1m wire at 1GHz

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Parasitic Contact Resistance

• Resistance of contacts or vias connecting adjacent metal layers

• Contacts and vias typically have single size, multiple contacts or
vias are used in parallel for better connection and lower resistance

M2

Via

M1
Poly
Diffusion

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 Outline
• Introduction
• Parasitic Capacitance
– Parallel Plate Capacitance
– Fringe Capacitance
– Coupling Capacitance
– Coupling Capacitance Effects
– Capacitance Tables
– Modeling Capacitance
• Parasitic Resistance
– Parasitic Wire Resistance
– Skin Effect
– Parasitic Contact Resistance
• Parasitic Inductance
– Parasitic Inductance
– When to Consider Inductance
• Wire Scaling

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Parasitic Inductance
• Parasitic inductance of metal line is related to magnetic field
induced by the changing current in the line or nearby lines and
can be divided into 2 components:
– Self inductance
– Mutual inductance (inductive coupling)
• Parasitic self inductance is related to the rate of change of the
current in the same metal line
• Mutual inductance is related to the rate of change of the current
in another metal line
• All are modeled as series inductors
• For a system of K wires, K
din
the induced voltage vm in wire m is given by: vm   Lm ,n
dt
where Lm,n is an element in the inductance matrix n 1

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 Parasitic Inductance
• Parasetic inductance calculation from geometry is complicated
• Simple formulae  l   2l  1   l   2l  d 
Lself  log  Lmutual  log     1
2   w  h  2 
  2   d  l 
l : length, w : width, h : height, d : center-to-center distance
µ : dielectric permeability, for l >> w,h
• More accurate calculations use loop inductance concept, where
current return path is taken into account to estimate magnetic
filed and hence inductance
• Lossless electromagnetic wave propagation depends on
capacitance and inductance per unit length; L and C
l l
– Propagation speed v 
LC 
L
– Characteristic impedance Z o 
C

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Parasitic Inductance
• This indicates that, even if metal line resistance is zero,
electromagnetic wave propagation determines signal delay
• Signal moves along the metal line with wave propagation speed,
hence, propagation delay is given by the time of flight
l
tp   LC
v
• For wires with low resistance and high switching frequency,
inductance starts playing a role in signal propagation and the
wire must be treated as a transmission line where signal
propagates as a wave rather than RC relaxation

• Inductance effects on signal propagation

include: longer delays, sharper rise/fall,
overshoot, ringing, reflections, and
inductive coupling noise

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 When to Consider Inductance
• Inductance must be considered for wires with both:
– Low resistance
– Rapid transition times
tr
l
• Both conditions can be translated
l (log) 2.5 lwcw
into bounds on wire length l RC delay
dominates
Rise time & RC
tr 5 lw
l  dominate
2.5 lw cw rw cw
Inductance 5 lw
Transition time Resistance matters l
rw cw
limit limit
Rise time
dominates

tr (log)

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Outline
• Introduction
• Parasitic Capacitance
– Parallel Plate Capacitance
– Fringe Capacitance
– Coupling Capacitance
– Coupling Capacitance Effects
– Capacitance Tables
– Modeling Capacitance
• Parasitic Resistance
– Parasitic Wire Resistance
– Skin Effect
– Parasitic Contact Resistance
• Parasitic Inductance
– Parasitic Inductance
– When to Consider Inductance
• Wire Scaling

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 Wire Scaling
• To benefit from transistor scaling, wire width and spacing must scale.
• By default, short (local) wire length scales equally as transistors get closer.
• Die area grows (processors went from 4mm2 in 1960s to 4cm2 in 2000s).
• Must consider different scaling factor for long (global) wires.
• Early wire scaling was “ideal”, all dimensions scaled equally.
• However, ideal wire scaling increases wire resistance.
• Currently, constant-resistance wire scaling is used.
W, S, td: 0.7
H: 1
L: 0.7 for local wires, x1 for constant L wires
R: L/WH = 1 for local wires, 1.43 for constant L wires
Cpp: LW/ td = 0.7 for local wires, 1 for constant L wires
RCpp: = 0.7 for local wires, 1.43 for constant L wires
• A growing gap exists between wire delay and gate delay.
– Circuit solutions, such as: interconnect repeater insertion.
– Technology solutions, such as: low-k dielectric and 3D integration.

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References

• Rabaey, chapter 4
• T. Sakurai & K. Tamaru, Simple formulas for 2D & 3D
capacitances, TED ,1983

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