Integrated Circuits

ECE481
Fall 2021
M3: Digital IC Design
Lecture 2
Design Flow
DiaaEldin Khalil
Ain Shams University
Integrated Circuits Laboratory

D. Khalil ECE481 – M3 Lecture 2 1

Outline

• System Design Flow

• Digital Abstraction Levels
• ASIC Design Flow Details
• FPGA Design Flow Details
• Designer-Fab Relationship
• Designer-FPGA Relationship
• Integrated Circuits Industry

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 General System Design Flow
System Architecture
System design System analysis
& Specifications

System breakdown

Analog Arch Digital Arch Software Arch

Schematic
RTL design Design &
design
coding
Schematics Simulation RTL RTL simulation Code Testing &
Layout Logical validation
design synthesis
Layout Physical verification Gate-Level GL simulation
Parasitics extraction
Physical
Post-layout simulation
synthesis
Layout Physical verification
Parasitics extraction
System integration Post-layout simulation
Iteration loops are Physical verification
Integrated System
omitted for simplicity Co-simulation
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Digital Abstraction Levels

• Typical more compact level of abstraction got 3 levels
below the architecture level
• An upper/lower level can be created from a given level
• Design is done from top-to-bottom
• Verification is done at each level to confirm correctness

Behavioral View
Logical
Abstraction (RTL)
Synthesis

Structural View
(Gate-Level Netlist)
Physical
Extraction Synthesis
Physical View
(Layout)

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 Outline

• System Design Flow

• Digital Abstraction Levels
• ASIC Design Flow Details
• FPGA Design Flow Details
• Designer-Fab Relationship
• Designer-FPGA Relationship
• Integrated Circuits Industry

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ASIC Design Flow

RTL Design Behavioral View RTL Verification

(RTL)

Formal Logical Synthesis

Abstracted View
Verification
Abstraction Structural View Gate-Level
(Gate-Level Netlist) Simulation
Post-Layout
Simulation Extracted Netlist Physical Synthesis

ERC (Electrical
Parasitics Physical View Rules Check)
Extraction (Layout) DRC (Design
Rules Check)
GDSII Generation
LVS (Layout vs.
Iteration loops are omitted for simplicity Fab Schematics)
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 RTL Design
• Input:
– Design specs
• Output:
– RTL behavioral description
• Tools:
– Manual writing.
– Automated HDL generation tools like HDL Designer
– Automated behavioral synthesis

Register Transfer Level (RTL)

– Written using a HDL
– Describe operation of synchronous circuit in terms of the flow of signals
(or transfer of data) between registers and the logical operations
performed on those signals

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RTL Verification
• Goal:
– Check that behavioral RTL functions as specs

• Tools:
Depend on design complexity
– Logic simulation
– FPGA Prototyping
– Emulation

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 RTL Verification
• Logic simulation: Use logic simulator like Modelsim (optionally use a System
Verilog verification methodology like Open V. M. (OVM) & Unified V. M. (UVM)
– Easy, accurate, flexible, and low cost
– However, not fast enough for large designs
– Too slow to run application software against the hardware design
• FPGA prototyping: Put design on FPGA and test in lab
– Fast and inexpensive
– Long time required to implement a large design
– Little debugging capability
• Emulation: Use Emulator (special hardware of many FPGAs and
dedicated software for real-time verification)
– Improves greatly on the long time of FPGA prototyping
– Provides comprehensive and efficient debugging capability
– Test application (software + hardware debug environment)
– Most expensive

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Logical Synthesis

• Input:
– RTL behavioral description

• Output:
– Gate-level netlist (using specific technology library)

• Tools:
– Automated logical synthesis tools
like Design Compiler and Leonardo Spectrum

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 Physical Synthesis (Design)

• Input:
– Gate-level netlist (using specific technology library)

• Output:
– Layout with specific constraints like: area, signal delays,
interconnection area, power, cross-talk

• Tools:
– Automated logical synthesis tools
like Encounter and Olympus-SoC

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Physical Design – Floorplanning

• Determines sizes and locations of all blocks
• Keeps highly connected blocks physically close to each other

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 Physical Design – Placement
• Determines the location of all logic cells and interconnection
areas within the flexible blocks

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Physical Design – Routing

• Divided into global routing and detailed routing.
• Global routing determines the location of all interconnections
• Detailed routing completely connects all signals on the chip

Global Routing Detailed Routing

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 Electrical/Design Rules Check (ERC/DRC)
• ERC checks layout to ensure that it meets fabrication electrical rules
• DRC checks layout to ensure that it meets fabrication design rules

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Layout vs. Schematic (LVS)

• Checks that the layout devices and connectivity have a one-to-one
correspondence with the gate-level netlist
Extracted Netlist

Extract

Layout

Yes
Compare End

No
Netlist
Debug

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 Parasitics Extraction & Post-Layout Simulation
• Parasitics Extraction (PEX) generates an extracted netlist that
includes interconnect parasitics
• Post-layout simulation checks that the extracted netlist performs
correctly compared to the original netlist
Extracted Netlist + Parasitics (RC)

Extract

Layout
Simulate

Yes
Simulate Compare End

No
Netlist
Debug
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Abstraction & Formal Verification

• Abstraction generates a model that symbolically describe
behavioral operation of the design
• Formal verification checks the abstracted view model against
the design specs Abstracted model

Abstraction

Netlist
Simulate

Yes
Design Specs Compare End

No
Debug

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 Outline

• System Design Flow

• Digital Abstraction Levels
• ASIC Design Flow Details
• FPGA Design Flow Details
• Designer-Fab Relationship
• Designer-FPGA Relationship
• Integrated Circuits Industry

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FPGA Design Flow

Same as ASIC design flow

RTL Design Behavioral View RTL Verification

(RTL)

Formal Logical Synthesis

Abstracted View
Verification
Abstraction Structural View Gate-Level
(Gate-Level Netlist) Simulation
Timing Mapping
New simplified steps

Simulation Delays Placement

Routing
FPGA
Back-Annotation Physical View

Bit-stream Generation
& FPGA Programming
Iteration loops are omitted for simplicity FPGA
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 Physical Design – Mapping
• Transforms the logic gates into FPGA technology specific logic
blocks (LUTs & FFs). Also optimizes the total number of logic
blocks required (area optimization) or the number of logic blocks
in time-critical paths (delay optimization).

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Physical Design – Placement

• Determines the specific location for each logic block in the
FPGA fabric, while trying to optimize routing to avoid
congestions and minimize wire delays.

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 Physical Design – Routing
• Routing can be done as one-step.
• Determines the wiring channels capacity and performs detailed
routing to completely connects all signals on the FPGA using the
connect and switch boxes.

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Back-Annotation & Timing Simulation

• Back-annotation generates timing information (delays, setup,
hold, clock edge) from physical design post routing.
• Timing simulation includes the back-annotated netlist to simulate
and check functionality and timing.
Netlist + Delays

FPGA Back-
Generate Annotate
Physical
Delays Netlist
View

Simulate

Yes
Simulate Compare End

No
Netlist
Debug
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 Outline

• System Design Flow

• Digital Abstraction Levels
• ASIC Design Flow Details
• FPGA Design Flow Details
• Designer-Fab Relationship
• Designer-FPGA Relationship
• Integrated Circuits Industry

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Designer-Fab Relationship

• In order to fabricate a chip, the designer has to choose

– An appropriate technology with required speed
– A fabrication house (Fab)
– The CAD tools to use

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 Designer-Fab Relationship

• Design Libraries
CAD Tools • Process Design Kit (PDK)

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Designer-Fab Relationship

Layout Masks

• Design Libraries
CAD Tools • Process Design Kit (PDK)

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 Designer-Fab Relationship

Layout Masks

(Packaged) Chips

• Design Libraries
CAD Tools • Process Design Kit (PDK)

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Outline

• System Design Flow

• Digital Abstraction Levels
• ASIC Design Flow Details
• FPGA Design Flow Details
• Designer-Fab Relationship
• Designer-FPGA Relationship
• Integrated Circuits Industry

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 Designer-FPGA Relationship

• FPGA development kit

• FPGA design tools FPGA Vendor

• In order to implement on FPGA, the designer has to choose

– An appropriate FPGA with required embedded-blocks, capacity, and
speed
– An appropriate development board with required peripherals (for system
development).
• The designer then completes the flow and programs the FPGA

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Outline

• System Design Flow

• Digital Abstraction Levels
• ASIC Design Flow Details
• FPGA Design Flow Details
• Designer-Fab Relationship
• Designer-FPGA Relationship
• Integrated Circuits Industry

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 ICs Business Models

• Integrated Device Manufacturer (IDM)

– Have in-house IC design and manufacturing Fabs
– Intel, IBM, Sony, TI, Toshiba, Samsung, Philips, …
• Fabless Design House
– Only focus on IC design of products and IPs
– Broadcom, Marvell, Xilinx, nVidia, Qualcomm, …
• IP Vendor
– ARM, Virage, Artisan, Denali, MIPS, Synopsys, …
• Design Services
– Wipro, TATA Elxsi, HCL Technologies, …
• Electronic Design Automation Vendor (CAD tools)
– Synopsys, Mentor Graphics, Cadence, …

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ICs Business Models

• Fab
– Only focus on IC manufacturing, mainly for the fabless companies
– TSMC, GlobalFoundries, SMIC, …
• Fab Equipment Vendor
– ASML, Applied Material, Novellus, Hitachi, …
• Wafer Supplier
– NOVA, Wafer World, SVM, …
• Assembly (Packaging) & Testing
– Amkor, Siliconware Precision, Advanced Semi Engineering, …

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 ICs in Egypt
ICs related careers in Egypt:
• Digital RTL design, physical design, verification
• Analog & mixed-signal design, layout, verification
• MEMS design, layout, verification
• Embedded systems & DSP design, verification, implementation
• System integration and development
• CAD development, consultation
ICs related companies in Egypt: (Alphabetical)
• Analog Devices • Mixel
• Axxcelera • Pearl
• Consultix • SilMinds
• Goodix • Si-Vision
• ICpedia • Si-Ware Systems
• MEMS-Vision • ST
• Mentor (Siemens EDA) • Vidatronics
• Microchip • …(there are more)
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References

• Rabaey, inserts F & G

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