Integrated Circuits

ECE481
Fall 2021
M3: Digital IC Design
Lecture 5
Design Verification
DiaaEldin Khalil
Ain Shams University
Integrated Circuits Laboratory

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Outline

• Verification Using UVM

• UVM Structure & Features

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 Verification Using UVM
• Functional verification (simulation) of a design needs test-bench
modules to control inputs of the design-under-test (DUT) and
inspect its outputs behavior.
• Test-benches provide limited abilities and rely on experience to
design input patterns and inspect outputs to verify correct
operation. Not really suitable for complex modern designs.
• SystemVerilog language is used to easily create verification
components for stimulus generation, output checking, and
coverage collection.
• Test-benches evolved into advanced verification environments
composed of generic components within a defined methodology.
• Latest version is the Universal Verification Methodology (UVM).
• This allowed creation of scalable and reusable verification
environments and verification intellectual property (VIP)
developed to provide robust verification of designs that target
specific applications/standards like USB, PCI, ….
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Verification Test Coverage

• To start, a verification plan is created to specify the detailed
function of the DUT broken down into specific features and
a plan how to test all these features with good test coverage.
• In addition, automated test pattern generation, functional
checking, bugs reporting, and coverage collection and analysis
are developed as part of the verification methodology.
• In modern complex designs, it is impossible to run enough test
vectors to exhaustively test all possible states of the design.
Test coverage is the amount of design states covered by test.
• To improve test coverage at good level of automation,
constrained random pattern generation is developed. Random
stimuli are easily generated and allow finding unexpected bugs.
Constrained random stimuli carry the same benefits yet direct
the tests to cover all key features of the design.

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 Verification Reuse
UVM improves verification productivity in 2 ways:
• It facilitates the construction of verification environments through
a generic library of SystemVerilog classes and components that
provide standardized functions, as well as, a set of guidelines
for best practice coding. This also ensures the uniformity and
cross-compatibility of the code.
• It facilitates the reuse of environments and components by
having modular and layered environment, where components at
all layers can be easily configured to their target roles.

D. Khalil ECE481 – M3 Lecture 5 5

Outline

• Verification Using UVM

• UVM Structure & Features

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 UVM Structure
• UVM rearranges the major components of a test-bench into a
modular hierarchical organization.

• UVM is based on object-oriented SystemVerilog and have class

hierarchy that is used to create all parts of the environment.
• The main two categories are:
– Components: static parts performing specific functions of the test
– Transactions: dynamic parts representing data moving between
components
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UVM Structure
Detailed structure of UVM

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 UVM Structure
• Top Module
Contains all components.
• Interface
Provides the communication
between test and DUT.
• Test
Contains all testing components to
test a specific feature of DUT.
• Sequence
Container for set of test vectors for a specific test scenario.
• Environment
Contains one or more agents to test specific functions a common
scoreboard and coverage collector.
• Scoreboard
Contains automated checkers to validate DUT outputs vs test
vector and keeps track of such checks to verify DUT functionality.
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UVM Structure
• Coverage Collector (Subscriber)
Collects and analyze data to
determine functional coverage.
Can be in environment or agents.
• Virtual Sequencer
Can be optionally used to provide
control over all agent sequencers.
• Agent
Contains components to test specific function of DUT. Active agent
has sequencer, driver, and monitor. Passive agent only has monitor.
• Sequencer
Generates test vector transactions for driver to execute on DUT.
• Driver
Converts transactions into timed stimuli to DUT interface.
• Monitor
Converts signals from DUT interface into transactions for scoreboard.
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 UVM Features
• Factory
This is a feature that allows UVM to modify and substitute a class
without having to modify all class instantiations. This is useful when
updating a test with new feature by substituting the modified class
in all test instead of going manually throughout the code.
• Transaction Level Modeling (TLM)
This is a feature that allows data moving between components to
be represented as high level abstracted transactions rather than
actual signals. Such transactions are much less complicated and
are simple to understand, verify, and debug.
• Sequence Libraries
Sequence items (test vectors) are organized to make up sequences
to perform a specific test scenario. Complex designs will need
hundreds of sequences. UVM allows organization of sequences in
libraries and the ability to combine sequences and randomly call
sequences to perform constrained random testing.

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References

• Doulos UVM tutorial

www.doulos.com/knowhow/sysverilog/uvm/tutorial_0/
• Chip Verify UVM tutorial
www.chipverify.com/uvm/uvm-tutorial
• Learn UVM Verification Blog
www.learnuvmverification.com/index.php/2015/05/14/uvm-
environment-components/

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