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Test Type Module Test Test Code Verilog SET 3_2019-

20
Verilog & FPGA
Subject Duration 2hrs Total Marks 100 Marks

INSTRUCTIONS: (Please read before answering)

1. Do not write on the question paper. Write / Answer only in the answer sheet provided
2. No additional time will be provided to complete the test
3. Your answer sheet will not be evaluated if the instructions are not followed.
I. Answer in one word (15 x 1 = 15)

1. The FPGA refers to ____________

a) First programmable Gate Array b) Field Programmable Gate Array

c) First Program Gate Array d) Field Program Gate Array

1. Which of the following language can describe the hardware?___________

a) C b) C++ c) JAVA d) VHDL 3)Verilog

2. In a multiplexer the output depends on its ________________

a) Data inputs b) Select inputs c) Select outputs b) Enable Pin

3. Most demultiplexers facilitate which type of conversion?_________________

a) Decimal-to-hexadecimal b) Single input, multiple outputs

c) AC to DC d) Odd parity to even parity

4) The sequential circuit is also called ___________

a) Flip-flop b) Latch c) Strobe d) Adder

5) How many possible outputs would a decoder have with a 6-bit binary input?_________

a) 32 b) 64 c) 128 d) 16

6) 2. Total number of inputs in a half adder is __________

a) 2 b) 3 c) 4 d) 1

7) 5. A decimal counter has ______ states.

a) 5 b) 10 c) 15 d) 20

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8) 1. Any signed negative binary number is recognized by its ________

a) MSB b) LSBc) Byte d) Nibble

9) Represent signed number -3 in bit/hex format. Consider bitwidth as 32

_______________________

10) 3. In a combinational circuit, the output at any time depends only on the _______ at that
time.

a) Voltage b) Intermediate values c) Input values d) Clock pulses

11. Maximum Clock Frequency of the RTL code is determined by

a) its Fastest Path c) Its Critical path b) Its Slowest pathd) all the above

12. Micro blaze uses what interface to communicate with peripherals

a) UART c) GPIO

b) SPI d) Memory Mapped

13. TheVHDL refers to ____________

a) Very High Signal Integration Circuit Hardware Description Language

b) Very High Signal Integrated Circuit Hardware Design Language

c) Very High Speed Integration Circuit Hardware Description Language

d) Very High signal Hardware Description Language

14. Total number of inputs in a half adder is __________

a) 2 b) 3 c) 4 d) 1

15. Any signed negative binary number is recognized by its ________

a) MSB b) LSBc) Byte d) Nibble

II. Answer the following (5 x 7 = 30)

1) draw a 8:1 mux using 2:1 mux

2) Write any VHDL/Verilog HDL code for an Asynchronous Reset D Flip Flop

3) Draw the Basic Internal Architecture for an FPGA

4) What is the difference between a Flop and a latch

5. From the below diagram tell the equivalent logic

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Circuit Gate Circuit Gate Circuit Gate

Circuit Gate Circuit Gate Circuit Gate

6. If a Behavioral simulation works , is it guaranteed that It will work on board

a) No it is not guaranteed, give reason: c) Yes it is guaranteed, give reason:

7.Name any 5 special function present in FPGA

III. Explain the following ( 10x 5 = 50)

1. Draw IO Pin diagram for a Dual Port RAM and a FIFO

2.what is the difference between a controller and FPGA.

3) Draw a detailed microarchitecture circuit for 24h Digital Clock Circuit assuming input clock
is 10Mhz.

4) Write the Verilog code for the architecture drawn.

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5) Draw the MOORE FSM for following sequence detection “101011” for both overlap and non-
overlap sequence and write the HDL code,

Note: code the states using one hot encoding (HDL coding for any of the one i.e overlapping
sequence or non-overlapping sequence).

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