IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO.
10, OCTOBER 2013
A 4-Path 42.8-to-49.5 GHz LO Generation
With Automatic Phase Tuning for 60 GHz
Phased-Array Receivers
Liang Wu, Alvin Li, and Howard C. Luong, Senior Member, IEEE
Abstract—This paper presents a 4-path LO generation system
with automatic phase tuning for 60 GHz phased-array receivers.
Each path employs a linear phase-shift generation chain composed
of an injection-locked-oscillator-based phase shifter cascaded with
an injection-locked frequency tripler. The frequency tripler with
a proposed locking-range enhancement technique is employed to
relax both the frequency and the phase shift of the phase shifter for
high linearity and low power. Finally, a novel successive-approxi-
mation algorithm is proposed to perform automatic phase detec-
tion and tuning. Fabricated in a 65 nm CMOS process and occu-
pying a core area of 1.4 2.0 mm², the proposed 4-path LO gener-
ation system measures linear phase shift range larger than ±90°,
amplitude variation within ±0.4 dB, phase resolution of 22.5°, and
maximum phase errors of 22.0° and 1.5° before and after auto-
matic phase calibration while drawing a current of 85 mA from a
1-V supply.
Index Terms—Injection locked, LO, millimeter wave, multiplier,
phased array, phase detection, phase shift, phase tuning, 60 GHz,
successive approximation, tripler.
I. INTRODUCTION
H IGH-DATA-RATE wireless communication is highly
desired for many emerging applications such as high-def-
inition video links and wireless personal area networks. The
ultra-wide bandwidth requirement has driven the operation
frequency of transceivers from several-GHz range up to mil-
limeter-wave (mmW) region. Conventionally, III-V compound
semiconductor technology is employed for implementing
mmW transceiver ICs due to its superior performance [1] in
terms of transition frequency and output power despite its
typically high cost and low levels of integration. On the other
hand, as CMOS technologies are aggressively scaled down,
RF, analog, and digital circuits can all be integrated on a single
chip to enable the implementation of mmW transceivers with
higher integration level and thus lower cost and more compact
solution. However, there are still major challenges regarding
Manuscript received November 29, 2012; revised May 01, 2013; accepted
May 30, 2013. Date of publication July 19, 2013; date of current version
September 20, 2013. This work was jointly supported by the TSMC University
Program and the Hong Kong Innovation and Technology Funding ITS/087/10.
This paper was approved by Associate Editor Brian Floyd.
The authors are with the Department of Electronics and Computer Engi-
neering, The Hong Kong University of Science and Technology, Clear Water
Bay, Kowloon, Hong Kong (e-mail: eewuliang@ee.ust.hk; eeluong@ee.ust.hk).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2013.2269855
0018-9200 © 2013 IEEE
2309
the limited output power and nonlinearity of CMOS power
amplifiers as well as limited gain and high noise figure of
CMOS low noise amplifiers. Such challenges make it difficult
for CMOS mmW transceivers to meet the link budget require-
ments considering the high path loss of up to 68 dB around
60 GHz which is calculated from the Friis transmission formula
for a 1-m link in free-space.
By imitating the behavior of a directional high-gain antenna,
phased-array systems can help address these challenges effec-
tively. More specifically, the extra gain obtained from spatial
power combining of the array can compensate for the path loss.
In addition, the beam direction can be steered electrically to
suppress unwanted signals and thus to improve the receiver’s
linearity. The beam steering also allows the same spectrum
to be used by multiple users, resulting in better spectrum
efficiency as compared with omnidirectional communications.
In a phased-array receiver, variable phase shifters are the most
essential building blocks required to compensate for the time
differences between adjacent elements which is a function of
the angle of the incident signals [2]. The variable phase range
determines the steerable beam direction range, and both the
phase accuracy and amplitude variations affect the peak-to-null
ratio of the array pattern.
Both passive and active phase shifters have been proposed
for on-chip phased-array receivers. Traditional passive types are
mainly based on distributed transmission line networks [3], [4]
and thus require large chip area. The migration from the dis-
tributed approaches to the lumped-element solutions, such as
synthetic transmission lines with capacitors and inductors [5]
and hybrid coupler with reflective loads [6], [7], could reduce
the physical dimension, but the chip area is still significant. In
addition, passive phase shifters suffer from other critical draw-
backs such as large insertion loss and amplitude variations. On
the other hand, most of the existing active phase shifters gen-
erate the required phase shift by interpolating two orthogonal
signals with amplitude weighting control [8]–[11]. They feature
a much smaller area, smaller insertion loss, and smaller ampli-
tude variations at the expense of larger power consumption and
requiring of quadrature inputs as compared to passive solutions.
In a phased-array receiver, the phase shifters need to be
tuned to rotate the beam direction. A common approach to
set the phase shifters is through the use of look-up tables [6],
[12], which are generally obtained by exhaustively searching
through and storing all possible combinations of the phase
shifter controls to achieve the best performance in terms of
peak-to-null ratio for different beam angles. As the element
2310
number increases, the number of combinations and the required
time grow exponentially. Due to the process variations and
different operation conditions, each chip would need its own
look-up table thus requiring long overall setup time, which
inevitably increases the total system cost. Gradient estimation
approach such as zero-knowledge beam-forming algorithm can
adjust the phase shifts on-the-fly, but the complicated calcu-
lations would require a complex and power-hungry processor
[13].
This work presents a novel 4-path LO generation scheme with
automatic phase tuning for 60 GHz phased-array receivers in
65 nm CMOS technology. The proposed phase shift chain com-
posed of a phase shifter cascaded with a frequency tripler fea-
tures linear phase shift, small output amplitude variations, and
low power consumption. Moreover, the error of the phase shift
of each path can be detected and compensated with a proposed
successive-approximation algorithm that significantly reduces
the calibration setup time.
The paper is organized as follows. Section II introduces the
proposed phased-array receiver system and describes the phase
shifters’ performance specifications in detail. In Section III, the
proposed variable phase shift chain and LO generation system
are presented and followed by design considerations and circuit
implementation of critical building blocks. In Section IV, the
proposed successive-approximation algorithm for phase shift
detection and tuning is discussed and illustrated. Section V
presents the experimental results, and the conclusion is given
in Section VI.
II. SYSTEM ARCHITECTURE
The variable phase shifters of a phased-array receiver can be
placed at various locations within the receiver chain resulting
in different phase-shifting architectures, including RF-path,
LO-path, IF-path, or baseband. RF-path phase-shifting con-
figuration features low power consumption and small chip
area [14], [15] because only one mixer and one LO signal are
required. Moreover, the linearity requirement of the mixer is
relaxed since the interferers and the jammers are removed after
the combiner and before the mixer. However, since the phase
shifters and the combiner are placed directly in the RF signal
paths and operated at the RF frequencies, the system budgets
would become more stringent, and all the blocks in the receiver
front-end (including the LNAs, the phase shifters, the com-
biner, and the mixer) would need to be carefully and optimally
designed to trade off the system performance in terms of gain,
noise figure, linearity, and power. In contrast, IF or baseband
phase-shifting configurations [16] relax the design of the phase
shifters due to much lower operating frequency at the expense
of many more RF and other building blocks. A major issue is
that the phase shifter in each of the IF or baseband paths would
need to have a much larger fractional bandwidth than their
RF counterparts. On the other hand, LO-path phase-shifting
topology avoids manipulation of the signal directly in the signal
path [9], [11]. If designed properly, the system performance
can be relatively insensitive to the phase shifters. The main
challenge with LO-path phase shifting is the generation and
the distribution of multiple LO signals with accurate phases
at mmW frequencies. Typically large LO signals could not
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013
only interfere and cause phase coherence problems among the
channels but also couple to the RF signal paths and induce
spurious tones, which would further result in signal distortion
by intermodulation. These issues could become more severe
as the array size increases. As a result, phased-array receivers
with more than 10 elements are mostly based on the RF
phase-shifting configuration [14], [15]. For a receiver with as
few channels as 4, LO phase shifting configuration is more
preferred [9], [11].
Fig. 1 shows the block diagram of the proposed 4-element
60 GHz phased-array receiver. Dual-conversion zero-IF archi-
tecture is employed not only to minimize the LO frequencies
but also to eliminate the problems with LO feed-through, LO
pulling, and DC offset. The first LO frequency is designed to be
three times of the second LO frequency. Therefore, the first LO
is located at 43.74/45.36/46.98/48.60 GHz while the second LO
is at 14.58/15.12/15.66/16.20 GHz corresponding to the 4 re-
quired RF channels centered at 58.32/60.48/62.64/64.80 GHz,
respectively, according to the IEEE 802.15.3c standard [17].
The image signal locates around 30-GHz far away from the de-
sired RF signal such that it would be significantly attenuated by
the band-pass filtering characteristics of the antennas and the RF
building blocks. To avoid directly manipulating the signal path
and thus not to make the overall system design and optimiza-
tion complicated as discussed above, the phase shifts are imple-
mented in the first LO path. The RF signals are phase-shifted and
down-converted to IF and combined before further down-con-
verted to baseband. Ideally, the output peak-to-null ratio is in-
finitely large, but in practice it is mainly limited by the phase
and amplitude mismatches of the phase-shifted signals. In this
proposed phased-array receiver, the amplitude mismatches are
negligibly affected by the LO, and the phase mismatches are
mainly contributed by the phase errors of the phase shifters.
At the same time, the output amplitude variations of the phase
shifters would also induce phase mismatches due to AM-to-PM
conversion. With assumption that the transmitter is located 3 m
away from the receiver while the interference is 10 cm away,
the desired signal would be around 30 dB weaker than the in-
terference signal. To achieve a peak-to-null ratio of 30 dB and
thus to sufficiently suppress the unwanted signal, system-level
simulation shows that the phase error and amplitude variation of
the phase shifts should be smaller than 2 and within 1.5 dB,
respectively. In addition, to allow the beam to be steered in all
the directions, the phase shift of the phase shifter should cover
a phase range of at least from 0 to 360 .
III. PROPOSED LO PHASE SHIFT GENERATION SYSTEM
A. Proposed Variable Linear Phase-Shift Chain
When an oscillator is injection-locked by an input signal, its
output frequency tracks the input frequency, and the phase dif-
ference between input and output can be tuned by changing its
self-oscillation frequency. Therefore, an injection-locked oscil-
lator can be utilized to generate a variable phase shift [18]. Ap-
proximately, the relationship between the phase shift and the
self-oscillation frequency is an arcsine function [19]:
(1)
WU et al.: A 4-PATH 42.8-to-49.5 GHz LO GENERATION WITH AUTOMATIC PHASE TUNING FOR 60 GHz PHASED-ARRAY RECEIVERS 2311

Fig. 1. Phased-array receiver architecture with the proposed LO-path phase shifting.

Fig. 2. Phase shift characteristic curves: (a) a typical injection-locked-oscillator-based phase shifter, and (b) the proposed linear-phase-shift generation chain.

where is the phase shift between output and input while
and are input frequency, self-oscillation frequency,
and one-sided frequency locking range, respectively. As plotted
in Fig. 2(a), the phase shift of an injection-locked oscillator is
quite non-linear outside the range of 30 , which would make
the close-loop design for automatically tuning the phase shift
complicated. Fortunately, within the range from 30 to 30 ,
the phase shift is quite linear.
This work proposes to implement the phase shifters by cas-
cading an injection-locked-oscillator-based phase shifter with
an injection-locked frequency tripler as shown in Fig. 2(b). As
the frequency tripler triples both the frequency and the phase
shift, the phase shifter only needs to operate at 1/3 of the output
frequency and to linearly tune from 30 to 30 to achieve an
effective linear phase range from 90 to 90 at the tripler’s
output. This much smaller phase range helps eliminate the prob-
2312
Fig. 3. Block diagram of the proposed LO generation scheme with automatic phase tuning.
lems with nonlinearity and high sensitivity in the existing
injection-locked phase shifters which need to operate over the
whole phase range from 90 to 90 [18]. In addition, the in-
jection-locked tripler is insensitive to input amplitude variations
since its output amplitude is dominated by its self-oscillation
current and voltage swing. This implementation also eliminates
the output amplitude variations over the tunable phase range in
conventional phase shifters due to their gain variations at dif-
ferent phase shift settings [21]. Overall, the proposed phase shift
chain has a very linear phase shift range from 90 to 90 with
very small amplitude variations. Lastly, a full linear phase range
from 180 to 180 for the system can be obtained simply by
flipping the outputs.
B. Proposed LO Generation System
Utilizing the proposed variable linear-phase-shift chain, the
proposed 4-path LO generation scheme for 60-GHz phased-
array receiver is constructed as shown in Fig. 3. Off-chip single-
ended LO input signals at 14.58/15.12/15.66/16.20 GHz are
symmetrically routed to the inputs of 4 on-chip baluns and con-
verted to differential signals. With each balun driving one path,
the phase error of the differential LO signals for each path solely
depends on its respective balun. As the differential signals pass
through their respective phase shifter, a phase shift of
is introduced depending on the control signals and
, which are for digitally coarse tuning and analog fine
tuning, respectively. The signals are then fed into injection-
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013
locked frequency triplers, through which both their frequen-
cies and phase shifts are tripled. Two-stage buffers are then em-
ployed to increase the driving capability of each path.
To measure the phases accurately, the 4-path outputs are
down-converted to 20 MHz with four on-chip mixers so that
time-domain measurement can be performed with an oscil-
loscope. The down-conversion mixers are divided into two
groups, each of which is driven by a balun that converts an
external single-ended signal to differential signals for testing.
The 4-paths outputs are also used to drive an on-chip phase
detection circuitry followed by off-chip control-signal genera-
tion blocks to form a closed-loop system for automatic phase
detection and tuning. The on-chip part is composed of two phase
detectors with low-pass filters and an error amplifier. Driven by
a multiplex (MUX), each input of the phase detectors can be
configured to be connected to one of the 4-path LO outputs. The
off-chip part is implemented with an FPGA development board
consists of a finite-state machine (FSM) followed by registers
(REGs) and digital-to-analog converters (DACs). Registers are
used to set the digital controls, such as phase shifters’ coarse-
tuning and input selection of the MUXs ,
while the DACs convert the digital control signal from FSM
to analog for the phase shifters’ fine-tuning . In this
closed-loop system, the FSM can select the desired signals for
detection and tune the phase shifter automatically according
to the proposed successive-approximation algorithm to be dis-
cussed in detail in Section IV. After the phase tuning process
is completed and the optimal settings are stored, the phase de-
tection and the tuning circuitries are turned off. By doing so, the
WU et al.: A 4-PATH 42.8-to-49.5 GHz LO GENERATION WITH AUTOMATIC PHASE TUNING FOR 60 GHz PHASED-ARRAY RECEIVERS 2313

By representing the loss of the LC tank as a parallel resistance

of , the output voltage amplitude can be derived as

(6)

As the phase shift ranges from 30 to 30 , the ratio of the

maximum amplitude to the minimum amplitude is within 1.05.
For the LC tank, the inductance is implemented by a differen-
tial coil with a center tap to save area and improve quality factor
while 7-bit switched-capacitor arrays (SCAs) and varactors are
used for digitally coarse tuning and analog fine tuning of the
self-oscillation frequency. To simplify the layout by reducing
the number of capacitors, the 7-bit SCA in this work is divided
into two groups, ( to ) and ( to , with unit capacitance
of and , respectively. is sized slightly
larger than 1/16 of to ensure a continuous resonant fre-
quency range and thus guarantee overlapping of the phase shift.
2) Injection-Locked Frequency Tripler (ILFT): At mmW
frequencies, LC-based injection-locked frequency triplers are
preferred due to their high operation frequencies and low power
Fig. 4. Schematic of the proposed phase shifter based on an injection-locked consumption even though their achievable locking range is
oscillator.
very limited. The schematic of a conventional injection-locked
frequency tripler is shown in Fig. 5(a) which can be modeled
phase noise would not be degraded, and the power consumption as a feedback loop composed of an LC band-pass filter (BPF)
is saved. centered at and two single-balanced mixers, as shown
in Fig. 5(b). Self-oscillation is sustained by feeding back to the
C. Circuit Design and Implementation
input a clean 3rd-order harmonic tone from the tripler’s output
1) Phase Shifter: The schematic of the proposed injection- to mix with the DC current to generate a current injection
locked-oscillator-based phase shifter is shown in Fig. 4. Self-os- component of . Frequency tracking is achieved
cillation is achieved through a negative transconductance imple- by mixing the input voltage with through nonlinear
mented by the cross-coupled transistors with a tail current switching devices to generate an injection current component
source while current injection is achieved through the dif- of . The two branches of current are injected
ferential pair biased with current tail . To minimize to the LC tank which filters out all harmonics except those near
power consumption while ensuring a sufficient locking range, and can be written as
the injection devices are sized to be 1/2 of the self-oscillation (7)
devices. When locked, the input frequency is typically in and
vicinity of the self-resonant frequency of the LC tank
(8)
(2) where and are corresponding
conversion coefficients.
where is small. Assuming the input and output voltage swings
Proper operation of the injection-locked frequency tripler re-
are large enough that the transistors are hard-switching,
quires that the total phase shift around the loop be 0 and that the
the one-sided locking range can be approximated [9]–[20] as
open-loop gain should be larger than unity which is easily satis-
fied as long as it can self-oscillate. The phase condition is ana-
(3)
lyzed by the phasor diagram in Fig. 5(c). The phase contributed
by the LC tank at frequency should be compensated by the
phase angle between the current component
Therefore, the phase shift can be derived from (1), (2), and (3) and the total summed current . Similar to the analysis in
as [19], [20], the angular frequency locking range can be de-
rived as
(4)
(9)

As long as is small, the above equation can be further simpli-

fied by approximation: (10)

(5) where is the quality factor of the LC tank and is de-

fined as the injection ratio. To maximize the locking range,
2314 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013

Fig. 5. Conventional injection-locked frequency tripler ILFT: (a) schematic, (b) behavioral model, and (c) phasor diagram.

Fig. 6. Proposed injection-locked frequency tripler ILFT: (a) schematic, (b) behavioral model, and (c) phasor diagram.

is generally designed to be the minimum value
required to sustain self-oscillation. Therefore, besides tuning
the resonant frequency , the locking range can be improved
by increasing . However, a larger would
require larger injection devices, which is typically not desired
not only because of increase of loading to the previous stage
but also because of larger power consumption drawn by the
injection branch and degradation of LC tank. Alternatively,
the conversion coefficient could be boosted by
operating the input transistors in the sub-threshold region, but
WU et al.: A 4-PATH 42.8-to-49.5 GHz LO GENERATION WITH AUTOMATIC PHASE TUNING FOR 60 GHz PHASED-ARRAY RECEIVERS 2315

Fig. 8. Schematic of the proposed highly symmetric phase detector.

Fig. 7. Simulated phase noise of the phase shifter, the ILFT and the phase-shift
chain while free-running and locking.

the coefficient is still very limited even with such an operation.

As a result, the locking range of a conventional frequency
tripler is quite narrow.
Since the generation of a 3rd-order harmonic from the tran-
sistor’s nonlinearities alone is inefficient, this work proposes
to boost the conversion efficiency from the input fundamental
to 3rd-order harmonic by using frequency mixing. Instead of
grounding the differential pair’s common-mode node CM, an
inductor is added to resonate with the parasitic capacitance
at , as shown in Fig. 6(a). As such, a 2nd-order harmonic
tone at Node CM mixes with the input fundamental
tone to generate a 3rd-order harmonic tone .
At the same time, the previous tone remains
the same since the common-mode node is virtual ground for
odd-order harmonics. The corresponding behavioral model and
phasor diagram are shown in Fig. 6(b) and (c), respectively. The
maximum achievable angle becomes significantly larger, re- Fig. 9. Proposed IQ calibration scheme: (a) phase detection and tuning loop,
and (b) input/output characteristic of phase detector.
sulting in a much larger locking range
(11)
input phase noise [20]. As shown in Fig. 7, the differences of the
simulated phase noise between the input and the phase shifter
(12)
output and between the input and the phase-shift chain output
are around 0 dB and 9.5 dB, respectively, which is theoretically
Regarding the performance improvement of the proposed expected because the output frequency is 3 times of the phase
ILFT, simulations in SprectreRF show that the injection ratio shifter frequency, which is the same as the input frequency.
is significantly boosted from 0.0019 to 0.16, which results 3) Phase Detector With Low-Pass Filter: The phase de-
in locking range enhancement from 200 MHz to 2 GHz. tector is implemented by a mixer, in which two Gilbert cells
Overall, the proposed injection-locked frequency tripler im- are combined with cross-connected inputs [22], resulting in
proves the locking range by more than 10 times without a highly symmetrical input loading, as shown in Fig. 8. The
adding extra loading to the previous stage or consuming extra output loading is composed of a low-pass RC network to filter
power. For the phase noise, the simulated result shows that the out unwanted tones and to pass only the desired DC signals to
proposed ILFT with exhibits only 0.05 dB degradation com- the output.
pared to the conventional ILFT without during free-running,
as shown in Fig. 7. The negligibly small degradation shows IV. AUTOMATIC PHASE TUNING
that the high-impedance node CM at made by has little
effect on the phase noise. A. Successive-Approximation Algorithm
Under locking, the output phase of the whole injection-locked Directly measuring the phase difference of two mmW sig-
phase-shift chain follows closely the phase of the input signals. nals with good accuracy is quite difficult. Instead, the phase
Provided the phase shifter and the ILFT operate far away from difference is converted to a voltage by a phase detector which
the locking boundary, the output phase noise is dominated by the is implemented by an analog mixer or multiplier, as shown in
2316 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013

Fig. 10. Proposed successive-approximation algorithm: (a) block diagram, and (b) automatic phase tuning of .

Fig. 11. Proposed port swapping and averaging: (a) input sequence without Fig. 12. Chip micrograph of the proposed LO generation.
swapping, (b) input sequence with swapping, and (c) Monte-Carlo simulation
results.

The output of the phase detector, after mixing and low-pass fil-
tering, can be derived as
Fig. 9(a). Assuming that the two inputs are sinusoidal waves
with the same frequency and the same amplitude but with dif-
ferent phases
(15)
(13)
(14) (16)
WU et al.: A 4-PATH 42.8-to-49.5 GHz LO GENERATION WITH AUTOMATIC PHASE TUNING FOR 60 GHz PHASED-ARRAY RECEIVERS 2317

Fig. 13. Measured phase tuning curves.

Fig. 14. Measured amplitude variations as a function of phase shift.

Fig. 15. Measured input and output phase noise of the proposed linear phase-
shift chain.
As expected, the phase detector’s output DC voltage is propor-
tional to the cosine of the input phase difference, as plotted in
Fig. 9(b). The absolute voltage reaches the maximum and By tuning the phases and thus making the same as
minimum point when the phase difference is 0/180 and 90 , is equal to . Furthermore, a phase
respectively. Therefore, I/Q calibration [22], [23] can be imple- of can be obtained if both and are
mented by a simple close-loop shown in Fig. 9(a). By setting known and . This is the key idea of the proposed
the reference voltage to be 0 and tuning the phases of the successive-approximation algorithm, whose implementation
input signals until the output voltage of the phase detector is shown in Fig. 10(a). and and are inputs to
equals to , which corresponds to a 0-V output of the error phase detectors (PDs) x and y, respectively. With MUXs, each
amplifier, a 90 phase difference can be achieved. However, of them can be configured to be any output of the 4-paths, i.e.,
the I/Q calibration loop is not suitable for detecting and cali- . After the phase detectors with low-pass filters, the
brating the phase shifts other than 90 because directly gener- DC signals and are proportional to the cosine of the
ating a precise reference voltage corresponding to other phase difference of the input phases. The comparator’s inputs,
shifts is really difficult. and , can then be selected to be either or 0.
Fortunately, the required reference voltage can be provided Starting from I/Q calibration, any phase of 90 / can be
by another phase detector whose inputs are and with obtained by successively detecting and tuning 90 / , with i
respective phase of and , as shown below: starting from . An example of achieving a 22.5 dif-
ference between neighboring paths is illustrated in Fig. 10(b).
(17) The first step is to obtain 90 . Similar
2318 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013

Fig. 16. Measured transient waveforms: (a) before automatic tuning, and (b) after automatic tuning.

Fig. 17. Measured frequency tuning curves of the 4 phase shifters.

to the traditional IQ calibration, is used as a 0 ref- B. Port Swapping and Averaging

erence while is tuned until 0. In Step II, both
and are now used as references such that Theoretically, any phase of 90 / can be tuned. However,
and are configured to be proportional to in reality, mismatches and offset errors in the phase detectors
and 90 respectively. By tuning until limit the minimum detectable phase. To simplify the analysis,
is set to 45 . After two more similar the equivalent phase error is modeled at the inputs as two
steps, , and can be tuned to be parts, phase independent part and phase dependent part, as
0 22.5 45 , and 67.5 , respectively. shown in Fig. 11(a). With and respectively feeding
WU et al.: A 4-PATH 42.8-to-49.5 GHz LO GENERATION WITH AUTOMATIC PHASE TUNING FOR 60 GHz PHASED-ARRAY RECEIVERS 2319

Fig. 18. (a) Simulated phase tuning curves, and (b) simulated maximum phase errors of the phase detector.

TABLE I
MEASURED PERFORMANCE SUMMARY AND COMPARISON WITH OTHER LO GENERATION SYSTEM FOR PHASED-ARRAYS

Port 1 and Port 2 of the phase detector, the output voltage is As shown in Fig. 11(b), by swapping the ports, which means
written as Port 1 and Port 2 are fed with and respectively, the new
output voltage can be derived as

(20)
(18)
Since and , by averaging the control signals
where and are the phase independent part and the phase and thus the phase, the phase difference becomes
dependent part of equivalent input phase error.
(21)
For I/Q calibration
The above equation shows that the phase independent part
(19) is completely cancelled and thus the phase error gets reduced,
2320
TABLE II
MEASURED PERFORMANCE SUMMARY AND COMPARISON WITH OTHER PHASE-SHIFTING CONFIGURATIONS
assuming the phase dependent part is not dominant. Monte-
Carlo simulations have been performed to verify the effective-
ness on the phase error. Simulation results of 90 phase detec-
tion plotted in Fig. 11(b) show that the standard phase deviation
and maximum phase error without port swapping are 1.5 and
4.4 , which are reduced to 0.3 and 0.91 with port swapping
and averaging, respectively.
V. EXPERIMENTAL RESULT
The entire LO generation system shown in Fig. 3 is fabri-
cated in a low-power 65 nm CMOS process with one poly and
six metal layers. Fig. 12 shows the chip micrograph, which oc-
cupies a core area of 2.0 1.4 mm . Highly symmetrical layout
is implemented by placing the 4 LO generation chain in the 4
corners while the phase detection is located at the center. The
phase shifts from the buffer outputs to the MUX inputs are laid
out to be ideally symmetrical among the 4 paths. As such, the
phase offset introduced by the MUX and routing wires of each
path is the same and thus the phase difference of the MUX in-
puts is equal to that of the buffer output. Any residual phase
errors due to mismatches can be further detected and fine-tuned
by the baseband in a phased-array system depending on specific
applications and requirements. In addition, it is worthwhile to
mention that the proposed 4-path LO generation scheme can be
potentially expanded to a larger system with more paths by di-
viding them into multiple 4-path sub-arrays.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013
Fig. 13 shows the measured phase tuning curves, which verify
that the phase shift range is larger than 90 90 for all the
4 channels of IEEE 802.15.3c standard. The non-monotonicity
is merely due to the overlapping of the two SCA groups, which
should not be a problem by properly selecting the digital control
words in the FSM. The amplitude variation, shown in Fig. 14, is
smaller than 0.35 dB thanks to the injection locking topologies
utilized in both the phase shifters and the frequency triplers.
To further verify the correct operation of the linear phase-shift
generation, its phase noise values at the input and the output are
measured with the phase calibration being turned off. As shown
in Fig. 15, the output phase noise closely follows the input phase
noise. Compared with input, the output phase noise is approxi-
mately degraded by 9.5 dB, which is consistent with simulation
results discussed above and theoretically expected because the
output frequency is three times of the input frequency.
Fig. 16 shows the down-converted output transient wave-
forms. Using the proposed automatic tuning followed by
exhaustively tuning for a 22.5 phase difference between
adjacent paths, an RMS phase error of 0.93 of each path is
measured, comparing with 13.12 before tuning. The maximum
phase error is reduced from 21.93 to 1.32 .
To characterize the mismatch among four different paths, the
phase shifters located farthest from each other are enabled to
be self-oscillating one at a time while the LO input centered at
15 GHz from an off-chip signal source is disabled. The digital
WU et al.: A 4-PATH 42.8-to-49.5 GHz LO GENERATION WITH AUTOMATIC PHASE TUNING FOR 60 GHz PHASED-ARRAY RECEIVERS
signal for coarse tuning is set to a minimum or max-
imum value while the analog signal for fine tuning is
varied from 0 to 1 V. The frequency tuning curves of the phase
shifters in the 4 paths are shown in Fig. 17. Statistically, the min-
imum, average and maximum absolute frequency mismatches
are 0.007%, 0.074%, and 0.181%, respectively. The maximum
frequency mismatch among the phase shifters is much smaller
than the locking range of the phase shifters which is around 10%
such that its effect on the phase shift characteristics is negligibly
small.
The temperature robustness of the proposed LO generation
system is mainly attributed to the temperature sensitivity of the
phase shifters and the phase detector. For the phase shifters, the
phase shift and the self-oscillation frequency mostly depend
on the tank inductance, the tank capacitance, and the parasitic
capacitance from the active devices, which from simulations
vary only 0.9%, 0.2%, and 0.7%, respectively, over a temper-
ature range from 0 C to 125 C. As such, the output phase shift
should be not sensitive to temperature. As shown in Fig. 18(a),
the simulated phase tuning curve at 43.74 GHz is shifted by
10 corresponding to a digital control word of 2, which is
much smaller than the total range of 33 for phase shift from
101 to 115 at the room temperature. Moreover, for the phase
detector, as the temperature changes from 0 C to 125 C, the
Monte-Carlo simulations show that the maximum phase errors
for 90 detection vary only from 0.89 to 0.99 as plotted
in Fig. 18(b), which indicates the variation is much smaller than
the absolute error at the room temperature. In summary, the de-
sign margins of the phase errors are more than sufficient to cover
the change due to the temperature variations.
Tables I and II summarize the measured performance and
compare with recently published state-of-the-art LO phase-shift
generation and phase-shifting configurations for phased-arrays,
respectively. The proposed LO generation system covers a fre-
quency range from 42.75 to 49.5 GHz with amplitude mismatch
within 0.35 dB, phase resolution of 22.5 , and maximum
phase error of 1.5 . With 1.0-V supply, the LO generation
core consumes a current of 55 mA while the automatic phase
detection and tuning part draws a current of 30 mA.
VI. CONCLUSION
An LO generation system for phased-array receivers com-
pliant to the IEEE 802.15.3c standard with automatic phase
tuning has been developed and successfully demonstrated
in a low-power 65 nm CMOS technology. The design con-
siderations and circuit implementation of the key building
blocks including the phase shifter, the injection-locked fre-
quency tripler, and the phase detector were discussed. With the
proposed variable linear phase-shift chain and successive-ap-
proximation algorithm, linear phase-shift with automatic tuning
has been achieved for all of the four desired channels with
phase shift range larger than 90 90 , phase resolution of
22.5 , maximum phase error of 1.5 , and amplitude variation
within 0.4 dB.
2321
REFERENCES
[1] S. E. Gunnarsson et al., “60 GHz single-chip front-end MMICs and
systems for multi-Gb/s wireless communication,” IEEE J. Solid-State
Circuits, vol. 42, no. 5, pp. 1143–1157, May 2007.
[2] J. Roderick et al., “Silicon-based ultra-wideband beam-forming,” IEEE
J. Solid-State Circuits, vol. 41, no. 8, pp. 1726–1739, Aug. 2006.
[3] F. L. Opp and W. F. Hoffman, “Design of digital loaded-line phase shift
networks for microwave thin-film applications,” IEEE J. Solid-State
Circuits, vol. SSC-3, pp. 124–180, Jun. 1968.
[4] M. E. Davis, “Integrated diode phase-shifter elements for an X-band
phased-array antenna,” IEEE Trans. Microw. Theory Tech., vol.
MTT-23, pp. 1080–1084, Dec. 1975.
[5] F. Ellinger, H. Jackel, and W. Bachtold, “Varactor-loaded transmis-
sion-line phase shifter at C-band using lumped elements,” IEEE Trans.
Microw. Theory Tech., vol. 51, no. 4, pp. 1135–1140, Apr. 2003.
[6] F. Ellinger, R. Vogt, and W. Bachtold, “Ultracompact reflective-type
phase shifter MMIC at C-band with 360 phase-control range for smart
antenna combing,” IEEE J. Solid-State Circuits, vol. 37, no. 4, pp.
481–486, Apr. 2002.
[7] A. Valdes-Garcia et al., “A fully-integrated 16-element phased-array
transmitter in SiGe BiCMOS for 60-GHz communications,” IEEE J.
Solid-State Circuits, vol. 45, no. 12, pp. 2757–2773, Dec. 2010.
[8] K.-J. Koh and G. M. Rebeiz, “0.13- m CMOS phase shifters for X-,
Ku-, and K-band phased arrays,” IEEE J. Solid-State Circuits, vol. 42,
no. 11, pp. 2535–2546, Nov. 2007.
[9] H. Wang and A. Hajimiri, “A wideband CMOS linear digital phase
rotator,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep.
2007, pp. 671–674.
[10] S. Gueorguiev, S. Lindfors, and T. Larsen, “A 5.2 GHz CMOS I/Q
modulator with integrated phase shifter for beamforming,” IEEE J.
Solid-State Circuits, vol. 42, no. 9, pp. 1953–1962, Sep. 2007.
[11] A. Natarajan et al., “A 77-GHz phased-array transceiver with on-chip
antennas in silicon: Transmitter and local LO-path phase shifting,”
IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2807–2819, Dec.
2006.
[12] C. T. Charles and D. J. Allstot, “A calibrated phase and amplitude con-
trol system for a 1.9 GHz phased-array transmitter element,” IEEE
Trans. Circuits Syst. I: Reg. Papers, vol. 56, no. 12, pp. 2728–2737,
Dec. 2009.
[13] M. Fakharzadeh et al., “CMOS phased array transceiver technology for
60 GHz wireless applications,” IEEE Trans. Antennas Propag., vol. 58,
pp. 1093–11104, Apr. 2010.
[14] A. Natarajan et al., “A fully-integrated 16-element phased-array re-
ceiver in SiGe BiCMOS for 60-GHz communications,” IEEE J. Solid-
State Circuits, vol. 46, no. 5, pp. 1059–1075, May 2011.
[15] S. Emami et al., “A 60 GHz CMOS phased-array transceiver pair for
multi-Gb/s wireless communications,” in IEEE ISSCC Dig. Tech. Pa-
pers, Feb. 2011, pp. 164–165.
[16] M. Tabesh et al., “A 65 nm CMOS 4-element sub-34 mW/element 60
GHz phased-array transceiver,” IEEE J. Solid-State Circuits, vol. 46,
no. 12, pp. 3018–3032, Dec. 2011.
[17] Part 15.3: Wireless Medium Access Control (MAC) and Physical Layer
(PHY) Specifications for High Rate Wireless Personal Area Networks
(WPANs) Amendment 2: Millimeter-Wave-Based Alternative Physical
Layer Extension, IEEE Standard 802.15.3c-2009 (Amendment to IEEE
Std. 802.15.3-2003), Oct. 2009.
[18] S. Patnaik, N. Sanka, and R. Harjani, “A dual-mode architecture for a
phased-array receiver base on injection locking in 0.13 m CMOS,” in
IEEE ISSCC Dig. Tech Papers, Feb. 2009, pp. 28–29.
[19] R. Adler, “A study of locking phenomena in oscillators,” Proc. IRE,
vol. 34, pp. 351–357, Jun. 1946.
[20] B. Razavi, “A study of injection locking and pulling in oscillators,”
IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1415–1424, Sep. 2004.
[21] K. Scheir et al., “A 52 GHz phased-array receiver front-end in 90
nm digital CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 12, pp.
2651–2659, Dec. 2008.
[22] A. Navid et al., “Level-locked loop, a technique for broadband quadra-
ture signal generation,” in Proc. IEEE Custom Integrated Circuits
Conf. (CICC), Sep. 1997, pp. 411–414.
[23] A. Y. Valero-Lopez, S. T. Moon, and E. Sánchez-Sinencio, “Self-cal-
ibrated quadrature generator for WLAN multistandard frequency syn-
thesizer,” IEEE J. Solid-State Circuits, vol. 41, no. 5, pp. 1031–1041,
May 2006.
[24] H. Hashemi, X. Guan, A. Komijani, and A. Hajimiri, “A 24-GHz SiGe
phased-array receiver—LO phase-shifting approach,” IEEE Trans. Mi-
crow. Theory Tech., vol. 53, pp. 614–626, Feb. 2005.
2322
[25] W. L. Chan, J. R. Long, M. Spirito, and J. J. Pekarik, “A 60-GHz-band
2x2 phased-array transmitter in 65 nm CMOS,” in IEEE ISSCC Dig.
Tech Papers, Feb. 2010, pp. 42–43.
[26] Y. Yu et al., “A 60 GHz phase shifter integrated with LNA and PA in
65 nm CMOS for phased array systems,” IEEE J. Solid-State Circuits,
vol. 45, no. 9, pp. 1697–1709, Sep. 2010.
[27] M. Tsai and A. Natarajan, “60 GHz passive and active RF-path phase
shifters in silicon,” in IEEE Radio Frequency Integrated Circuits Symp.
(RFIC) Dig., Jun. 2009, pp. 223–226.
Liang Wu received the B.S. and M.S. degrees in
materials science from Fudan University, China, in
2004 and 2007, respectively, and the Ph.D. degree in
electronic and computer engineering from the Hong
Kong University of Science and Technology in 2012.
In March 2013, he joined the Department of Elec-
tronic and Computer Engineering at the Hong Kong
University of Science and Technology as a visiting
assistant professor. His research interests include
CMOS RF/millimeter-wave integrated circuits,
phased-array for 60 GHz wireless communications,
and visible light communication systems.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 10, OCTOBER 2013
Alvin Li received the B.Eng. degree in engineering
physics from McMaster University, Ontario, Canada,
in 2007, and the M.Sc. degree in electronic and com-
puter engineering from the Hong Kong University
of Science and Technology (HKUST) in 2009. He
is currently working towards the Ph.D. degree at
HKUST.
His research interests include RF and mm-wave
frequency synthesis for wireless communication and
wireless sensing systems.
Howard C. Luong (SM’02) received the B.S.,
M.S., and Ph.D. degrees in electrical engineering
and computer sciences (EECS) from University of
California at Berkeley, CA, USA, in 1988, 1990, and
1994, respectively.
Since September 1994, he has been with the EEE
faculty at the Hong Kong University of Science and
Technology where he is currently a Professor. His re-
search interests are in analog, RF, and mm-Wave inte-
grated circuits and systems for wireless and portable
applications. He was a co-author of the books Low-
Voltage RF CMOS Frequency Synthesizers (Cambridge University Press, Au-
gust 2004) and Design of Low-Voltage CMOS Switched-Opamp Switched-Ca-
pacitor Systems (Kluwer Academic Publishers, July 2003).
Prof. Luong is currently serving as an IEEE Solid-State Circuits Society
Distinguished Lecturer, an Associate Editor for IEEE Virtual Journal on RFIC,
a Guest Editor for Journal of Emerging Technologies on Circuits and Systems
(JETCAS), and a technical program committee member of many conferences,
including IEEE Custom Integrated Circuits Conference (CICC), European
Solid-State Circuits Conference (ESSCIRC), Asian Solid-State Circuits Con-
ference (A-SSCC), and IEEE International Symposium on Radio-Frequency
Integration Technology (RFIT).