LAB RECORD 8

Name – Amit Prajapati

Roll no. – BT20ECE102
Course – HDL
Semester – 4th

Using Verilog Do the following:-

a) 8:1 MUX
b) 1:8 DEMUX
c) 8:3 Encoder
d) 3:8 Decoder

a) 8:1 MUX

Code
module mux_8to1(x_1,sel,out1);
input [7:0]x_1; //8 bit input
input [2:0]sel; //3 bit select lines
output out1; //1 bit output
assign out1 = x_1[sel]; //logic statement
endmodule

Flowchart
Graph
 b) 1:8 DEMUX
Code

module demux_1to8(x_1,sel,y_1);
input x_1; //1 bit input
input [2:0]sel; //3 bit select lines
output [7:0]y_1; //8 bit output
reg [7:0]y_1; //data type
always @ (sel) begin
case (sel)
3'b000 : begin y_1[0] = x_1; y_1[7:1] = 0;
end
3'b001 : begin y_1[1] = x_1; y_1[0] = 0;
end
3'b010 : begin y_1[2] = x_1; y_1[1:0] = 0;
end
3'b011 : begin y_1[3] = x_1; y_1[2:0] = 0;
end
3'b100 : begin y_1[4] = x_1; y_1[3:0] = 0;
end
 3'b101 : begin y_1[5] = x_1; y_1[4:0] = 0;
end
3'b110 : begin y_1[6] = x_1; y_1[5:0] = 0;
end
3'b111 : begin y_1[7] = x_1; y_1[6:0] = 0;
end
default : y_1[7:0] = 0;
endcase
end
endmodule
Flowchart
 Graph

c) 8:3 Encoder

Code
module encoder_8to3(x_1,y);
input [7:0]x_1; //8 bit input
output [2:0]y; //3 bit output
reg [2:0]y; //data type
always @ (x_1) begin
case (x_1)
8'b00000001 : begin y = 3'b000; end
8'b00000010 : begin y = 3'b001; end
8'b00000100 : begin y = 3'b010; end
8'b00001000 : begin y = 3'b011; end
8'b00010000 : begin y = 3'b100; end
8'b00100000 : begin y = 3'b101; end
 8'b01000000 : begin y = 3'b110; end
8'b10000000 : begin y = 3'b111; end
endcase
end
endmodule
Flowchart
Graph
d) 3:8 Decoder

Code
module decoder_3to8(x_1,y);
input [2:0]x_1; //3 bit input
output [7:0]y; //8 bit output
reg [7:0]y; //data type
always @ (x_1) begin
case (x_1)
3'b000 : begin y = 8'b00000001; end
3'b001 : begin y = 8'b00000010; end
3'b010 : begin y = 8'b00000100; end
3'b011 : begin y = 8'b00001000; end
3'b100 : begin y = 8'b00010000; end
3'b101 : begin y = 8'b00100000; end
3'b110 : begin y = 8'b01000000; end
3'b111 : begin y = 8'b10000000; end

endcase

end

endmodule
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Graph