Integrated System Design: UEC859

Topic: RTL Combinational circuit:

Dr. Sujit K Patel

Assistant Professor, ECED
Lecture : 6
 Concurrent Statements

VHDL provides four different types of concurrent statements

namely:
 Simple Signal Assignments

• The simple signal assignment looks like this

Sum <= A + B;

Where, sum  is a signal of integer type

A, B  Ports of IN mode integer type
 Conditional Signal Assignments

• Conditional signal assignments are signal assignments with

more than one source expression, where one of the source
expressions is chosen by a control condition.

• The simplest form of the conditional signal assignment has only

one condition:

Sum <= A + B when SEL = ‘1’ else A - B;

• The hardware mapping of the conditional signal assignment is a

multiplexer that selects between the source expressions and
that is controlled by the condition expression.
 Cont’d…

Hardware mapping of conditional signal assignment

 Cont’d…

Example: Multiple-branch conditional signal assignment

Multi-way conditional signal assignment

 Cont’d…

Each condition in a conditional signal assignment is assumed to

be independent of the others when mapping onto hardware.
 Selected Signal Assignments

• Selected signal assignments is like conditional signal

assignments.

• The difference is that a selected signal assignment uses a

single condition to select one from many branches.

• Example:
 Selected Signal Assignments Cont’d…

• Selected signal assignments is like conditional signal

assignments.

• The difference is that a selected signal assignment uses a

single condition to select one from many branches.

• Example:
 Block Statement
• Block Statement is a Concurrent VHDL Construct Which is
Used Within an Architectural Body to Group (Bind) a Set of
Concurrent Statements.

• There are two kinds of BLOCK statements:

– Simple
– Guarded

• Simple block statement allows a set of concurrent

statements to be clustered into a BLOCK, with the purpose of
turning the overall code more readable and more
Manageable.
 Block Syntax (Simple)

• A Guard Condition May be Associated with a Block Statement to Allow

Enabling/Disabling of Certain Signal Assignment Statements.

• The Guard Condition Defines an Implicit Signal Called GUARD.

• Blocks Can Be Nested.

Notes
1. If Guard Condition (Clk=`1`) is TRUE, Guarded Statements within block are Enabled
(Made Active)
2. Guarded Statements (e.g., I_State) execute when
– Guard Condition Becomes True, AND
– While Guard Condition is True, a Signal on the RHS Changes Value
3. UnGuarded Signal Targets (e.g., Q, QB) are independent of the Guard Condition
Arch2
Architecture DF1_Block of DFF is
Doesn’t Work
Signal I_State: Std_Logic:='1';
begin
D_Blk: Block(Clk='1' and Clk'Event)
Begin
Q <= Guarded D after Tdel;
QB <= Guarded not D after Tdel;
End Block;
End DF1_Block ;

Arch3
Architecture DF2_Block of DFF is
Signal I_State: Std_Logic:='1';
begin Works Fine
D_Blk: Block(Clk='1' and not Clk'Stable)
Begin
Q <= Guarded D after Tdel;
QB <= Guarded not D after Tdel;
End Block;
End DF2_Block ;