Performance Evaluation and Design Considerations of 2D Semiconductor Based FETs
for Sub-10 nm VLSI
Wei Cao, Jiahao Kang, Deblina Sarkar, Wei Liu and Kaustav Banerjee+
Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA, 93106-9560, USA
+Contact e-mail: kaustav@ece.ucsb.edu
Abstract
Two-dimensional (2D) crystal semiconductors, such as the
well-known molybdenum disulfide (MoS2), are witnessing an
explosion in research activities due to their apparent potential for
various electronic and optoelectronic applications. In this paper,
dissipative quantum transport simulations using non-equilibrium
Green’s function (NEGF) formalism are performed to rigorously
evaluate the scalability and performance of monolayer/multilayer
2D semiconductor based FETs for sub-10 nm node VLSI
technologies. Device design considerations in terms of the choice of
prospective 2D materials/structure/technology to fulfill the sub-10
nm ITRS requirements are analyzed for the first time. Firstly, it is
found that MoS2 FETs can meet high-performance (HP) requirement
up to 6.6 nm node by employing bilayer MoS2 as the channel
material, while low-standby-power (LSTP) requirements present
significant challenges for all sub-10 nm nodes. Secondly, by
studying the effects of underlap (UL) FET structures, scattering
strength and carrier effective mass, it is found that the high mobility
and suitably low effective mass of tungsten diselenide (WSe2), aided
by UL, enable 2D FETs for both HP and LSTP applications at the
smallest foreseeable (5.9 nm) node. Finally, possible solutions for
sub-5 nm nodes are also proposed based on the effects of critical
parameters on device performance.
I. Introduction
Compared to graphene, 2D semiconductors such as MoS2 and
other transition metal dichalcogenides (TMDs), are considered to be
more suitable for VLSI applications, due to their intrinsically
uniform and non-zero band gaps that significantly lower the device
leakage and static power consumption [1]-[5]. The atomic scale
thicknesses of these 2D semiconductors offer high scalability to
field-effect transistors (FETs) in which they are used as channel
materials. Ballistic transport simulations were performed in [2],[3]
to evaluate the scalability of monolayer/multilayer TMD FETs based
on a semiconductor-on-insulator (SOI) FET topology. However, it
has been recently reported that MoS2 suffers from remote phonon
scattering in high-k dielectric environment and has an intrinsic
phonon limited mobility of only ~ 60 cm2/V·s [4]. Moreover, Liu et
al. [5] reported, by considering phonon scattering, that the
performance of monolayer MoS2 FET is far from “ballistic” even at
sub-10 nm nodes. Additionally, till date, the reported scaling
analyses [2],[3],[5] seem generally negative in terms of meeting the
ITRS requirements, and no efforts have been made to provide
possible solutions for overcoming the apparent challenges.
Therefore, a comprehensive performance/scalability evaluation of
monolayer/multilayer TMD- and other 2D- FETs based on
dissipative transport theory, along with practical solutions to meet
the ITRS requirements is highly desirable. We present such an
evaluation platform and propose solutions for sub-10 nm 2D FETs.
II. Methodology
Fig. 1(a) shows the schematic of an n-type double-gated (DG)
2D FET used in the simulations. HfO2 is used as both top and
bottom gate dielectric. Poisson’s equation and transport equations
are iteratively solved to obtain self-consistent values of parameters,
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as shown in Fig. 1(b). The coupling term in the effective mass
Hamiltonian is set to be zero for multilayer devices, due to the weak
interlayer interaction [3]. In the transport equations, scattering
events are modeled by “Büttiker Probes” (Fig. 1(c)) within the
NEGF formalism [6]. For each probe (i.e., a scatter), scattering
strength or equivalently probe self-energy ∑P is mapped from
experimentally measured or theoretically predicted low-field
mobility, which allows us to take into account all types of
non-negligible scattering events, such as acoustic/optical phonon
scattering from lattice vibrations, remote surface phonon scattering
from gate dielectric, and Coulomb scattering from charged defect
and/or ionized impurities, etc. [4],[5], in a computationally
affordable manner. Fundamentally, scattering events only
perturb/change the momentum and energy of mobile carriers, they
do not absorb or generate carriers, i.e., the total number of carriers is
required to be conserved. This requirement can be achieved by
adjusting the probe Fermi level µP (assigned to each scatter) to
ensure that the net current (including in-scattering and out-scattering
currents [6]) through each scatter is zero, i.e., current continuity
condition. Detailed information about this approach can be found in
[6]. Figs. 2(a) and (b) show the electron density color map obtained
with ballistic transport simulation as well as dissipative transport
simulation used in this work, respectively. The difference in
essential physics can be clearly observed from the fact that the
electrons keep relaxing energy during dissipative transport from
source to drain, compared to the conserved energy during ballistic
transport. On the other hand, drain current and output resistance
(Rout) predicted by ballistic and dissipative transport simulations are
also different even for gate length as small as 8 nm, as shown in
Figs. 2(c) and (d), indicating the necessity of dissipative transport
simulation in accurately evaluating the performance of MoS 2 FET
and other 2D FETs. MoS2, as the most studied 2D semiconductor, is
taken as a representative 2D channel material in this study.
Whenever MoS2 is unable to meet the ITRS requirements, study is
extended to other 2D semiconductors by changing critical
parameters that affect device performance. Relevant parameters
dependent on the number of layers of MoS2 [1],[3],[4],[7] are listed
in Table I. Theoretical mobility limits in this table are used for
MoS2, while an optimistic mobility of 200 cm2/V·s is used for Si
device in the simulations. A high source/drain doping of 6.5×1013
cm-2 is used to ensure ohmic source/drain contacts [8].
III. Results and Discussion
Device Electrostatics Evaluation: In ultra-short channel FETs,
fringing electric field at the two edges of the gate is usually
detrimental to device electrostatics. Therefore, the effect of spacer
(beside the gate dielectric, as schematically shown in Fig. 1(a)) with
different dielectric constants is studied at first. Fig. 3(a) shows
improved subthreshold characteristics with low-k spacer, which is
attributed to the fact that fringing electric fields are suppressed by
low-k spacer, as shown in Figs. 3(b) and (c). The red dashed lines in
the insets of Figs. 3(b)-(c) represent the locations where x and y
components of the fringing electric field are extracted, respectively.
In Figs. 4(a),(b), subthreshold swing (SS) and
drain-induced-barrier-lowing (DIBL) are evaluated for both DG and
30.5.1 IEDM14-729
 SOI structures from monolayer (1L) to 3 layer- (3L) MoS2 as well
as Si based ultra-thin-body (UTB) DG FETs. Values for parameters
such as effective-oxide-thickness (EOT), supply voltage Vdd, body
thickness (only for Si device) at each node (or gate length Lg) are
adapted from ITRS [9] and used throughout this work. It is shown
that MoS2 FETs have much better electrostatics than Si devices. On
the other hand, SOI topology can only sustain good electrostatics for
1L MoS2, while DG topology can do so for up to 3L.
ON-Current and Output Resistance Evaluation: Fig. 5(a)
shows the obtained ON-current (Ion) for 1L-3L MoS2 FETs for both
HP and LSTP applications. It is found that, for HP, 2L case provides
the highest Ion, and can meet the requirement up to 6.6 nm node. In
contrast, for LSTP, 1L is the closest to, although still lower than, the
requirement. This is due to the fact that HP relies more on
super-threshold performance (current drive capability), while LSTP
relies more on the subthreshold performance (electrostatics), as
schematically illustrated in Fig. 5(b). Compared to 1L, 2L and 3L
have more available states for conduction and higher “mobility” [10]
(an extended concept to conveniently quantify the “scattering rate”
in sub-10 nm scale, and not identical to the conventional definition
for long-channel devices), and thus higher current drive capability,
so they have higher Ion for HP. 3L shows lower Ion than 2L, because
its worse electrostatics begins to degrade Ion for HP. Therefore, > 3L
must be avoided for sub-10 nm nodes. 1L has the best electrostatics,
and thus the highest Ion for LSTP. The degree of current saturation
that can be quantified by Rout, is critical for circuit metrics such as
noise margin and voltage gain. Fig. 6 shows the Rout at different
nodes. It can be observed that device with smaller channel thickness
(better electrostatics) displays higher Rout or better saturation.
Design Considerations for ITRS: Given the inability of MoS2
FETs in fulfilling the HP requirement at the smallest 5.9 nm node,
and LSTP requirement for all sub-10 nm nodes, natural tendencies
are to improve the device electrostatics and increase the “mobility”.
The underlap (UL) structure could be a choice for the former goal.
As shown in the upper three subplots of Fig. 7, 2L and 3L cases can
derive more benefits in lowering SS, compared to the 1L case,
because of their larger room for improving electrostatics. Although
UL improves device electrostatics by reducing
source/drain-to-channel coupling, i.e., lowers SS, it degrades drive
current by introducing extra series resistance Rseries, as shown in the
lower three subplots of Fig. 7. Therefore, the length of UL should be
optimized to maximize Ion. Fig. 8 shows the effect of varying UL on
Ion for 1L-3L MoS2 FETs. It is found that UL can help 2L and 3L
MoS2 FETs achieve higher Ion at small nodes for both HP and LSTP,
due to greatly reduced SS (see Fig. 5(b)). However, it does not help
or even degrades 1L MoS2 FET, because the effect of increasing
Rseries prevails over that of reduced SS for 1L. Although the obtained
Ion values are still lower than the requirement, UL design is
demonstrated to be helpful. Based on the results in Figs. 7 and 8, it
can be observed that 1L MoS2 with 1 nm UL should be used for
LSTP, and 2L MoS2 with 0-1 nm UL should be used for HP.
To estimate how much the increased “mobility” can help,
ballistic transport simulation (UL is not used) is performed to obtain
Ion as shown in Fig. 9. It can be observed that the HP requirement of
all the nodes in the road map can be met, while LSTP requirement
beyond 7 nm node cannot, indicating that HP requires high
“mobility”, while only high “mobility” is not sufficient for LSTP
below 7.4 nm nodes. Subsequently, the combined effects of UL and
increased “mobility” are studied for the smallest 5.9 nm node in
Figs. 10(a) and (b), respectively. Note that when varying the
“mobility”, only scattering rate is changed, effective mass remains
the same. For HP, 2L aided by 1 nm UL requires a “mobility” of 138.
In comparison, 1L without UL requires a “mobility” of 174. The
former is expected to be much easier to achieve than the latter since
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carriers in 2L would experience less scattering compared to that in
1L. Such mobility boost can be achieved by engineering the
dielectric environment, such as inserting h-BN buffer layer between
high-k dielectric and TMD channel [11]. The other solution is to
employ high-mobility 2D semiconductors. In fact, 1L WSe2 has
been found to exhibit mobility as large as 200 cm2/V·s [12], and
thus, is more promising than MoS2 for HP applications. In contrast,
increased “mobility” aided by UL, although helpful, is still not
sufficient for LSTP. In order to look for solutions for LSTP, the
effect of effective mass aided by 1 nm UL (0 nm UL case is also
shown for comparison) and increased “mobility” is studied as shown
in Figs. 11(a) and (b). It can be observed that smaller effective mass
offers higher Ion due to higher carrier velocity, but aggressively
small effective mass also leads to source-to-drain (S-to-D) tunneling
leakage (Fig. 11(c)) and thus to severely degraded SS and Ion. With
the help of UL, devices are more immune to S-to-D tunneling
leakage, and thus can derive more benefit from reduced effective
mass. For 2D materials with 1 nm UL and an effective mass of 0.3
m0, the LSTP requirement can be met if 1L “mobility” can reach 190.
Fig. 12 collects currently available experimental/calculation data in
the literature [1],[7],[12]˗[15] for various 2D materials, where WSe2
is shown to have the desired values. Note that graphene, germanene,
and silicene are not included here because of their zero or small
band gaps, which make them unsuitable for logic applications.
Possible Solutions for Sub-5 nm Nodes: It has been shown
above how hard it is to fulfill the ITRS requirements at the 5.9 nm
node. Hence, requirements for sub-5 nm nodes are significantly
harder, and the most stringent scaling constraint should be identified
to allow appropriate compromise. Fig. 13 shows the obtained Ion
from 1L MoS2 FETs (UL=0) with and without Vdd scaling. It can be
found that if Vdd is not scaled, ITRS requirement can be easily met
at all nodes in the current roadmap, indicating that for ultra-short
channels, such as sub-5 nm nodes, the constraint on Vdd can be
suitably relaxed to achieve a balance between power consumption
and speed. The other direction is to resort to steeper turn-on devices
such as tunnel FETs that provide sub-kT/q operation (SS < 60
mV/decade) and thus able to conquer the Vdd “barrier” [16].
Alternatively, 3D IC integration with 2D materials [17] could
provide an alternative pathway to scaling beyond the 5 nm node.
IV. Summary
Performance and scalability of 2D FETs are comprehensively
evaluated for sub-10 nm nodes, through rigorous dissipative
quantum transport simulations. As summarized in Table II,
solutions based on the proper choice of
materials/structure/technology for 2D FETs to fulfill the ITRS
requirements up to the year 2026 are identified for the first time.
Acknowledgment: This work is being supported by the AFOSR
under Grant A9550-14-1-0268 (R18641).
References
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Yoon, et al., Nano Lett. vol. 11, no. 9, pp. 3768, 2011. [3] V. Mishra, et al.,
IEEE IEDM Tech. Dig., pp. 136, 2013. [4] N. Ma, et al., Phys. Rev. X, vol. 4,
no. 1, pp. 011043, 2014. [5] L. Liu, et al., IEEE Trans. Elect. Dev., vol. 60,
no. 12, pp. 4133, 2013. [6] R. Venugopal, et al., J. Appl. Phys., vol. 93, no. 9,
pp. 5613, 2003. [7] W. Liu, et al., IEEE IEDM Tech. Dig., pp. 499, 2013.
[8] J. Kang, et al., Phys. Rev. X, vol. 4, no. 3, pp. 031005, 2014. [9] Table
PIDS 2 and 4, ITRS 2012 update, online. [10] J. Kang, et al., Appl. Phys.
Lett., vol. 104, no. 9, pp. 093106, 2014. [11] J. Kang, et al., 45th IEEE SISC,
San Diego, CA, Dec 10-13, 2014. [12] W. Liu, et al., Nano Lett., vol. 13,
no. 5, pp. 1983, 2013. [13] J. Qiao, et al., Nature Comm., vol. 5, no. 8, pp.
4475, 2014. [14] J. Song, et al., ACS Nano, vol. 7, no. 12, pp. 11333, 2013.
[15] S. Larentis, et al., Appl. Phys. Lett., vol. 101, no. 22, pp. 223104, 2012.
[16] W. Cao, et al., AIP Adv., vol. 4, pp. 067141, 2014. [17] J. Kang, et al.,
Proc. SPIE, vol. 9038, pp. 908305, 2014.
30.5.2
 Table I: Parameter dependence on number of MoS2 layers [1],[3],[4],[7].

Fig. 1: (a) A schematic of 2D FET with double-gated topology. (b) The

self-consistent NEGF-Poisson simulation scheme. U, n, and I are
self-consistent potential, electron density, and current, respectively. (c)
Illustration of the concept of “Büttiker probes” to model scattering events
along the 2D channel material between Source and Drain contacts. The
probe Fermi levels µP1, µP2……. µPN, are adjusted to ensure zero net current at
each scatter. ∑P represent the corresponding probe self-energies.

Fig. 4: (a) Subthreshold swing (SS) and (b) Drain-induced-barrier-lowering

(DIBL) with gate length scaling for 1L-3L MoS2 FETs, and Si based
ultra-thin-body double gated (Si UTB DG) FETs (only SS shown). “DG” and
“SOI” represent double-gate and semiconductor-on-insulator structures,
respectively. DG has a symmetrical top and bottom gate dielectric, while in
SOI the bottom dielectric is 50 nm thick SiO2 and bottom gate is grounded.

Fig. 2: Energy resolved electron density (brighter color indicates higher

density) shows that in (a) ballistic transport, electron wave propagates
without energy relaxation (flat color contour in the channel), while in (b)
dissipative transport, carriers keep relaxing energy (bent color contour in the
channel); (c) Transfer characteristics in linear scale (right) and log scale
(left) show that drain current is overestimated by ballistic simulation even
for gate length as small as 8 nm; (d) Output characteristics show that output
resistance (Rout) is overestimated by ballistic simulation.

Fig. 5: (a) ON-current (Ion) versus gate length for 1L-3L MoS2 FETs, and Si
UTB DG FETs. Black dashed lines represent the ITRS requirement for Ion.
“HP” and “LSTP” represent high-performance and low-standby-power
technologies, respectively; (b) A schematic illustration showing the method
used for obtaining Ion and the design priorities for LSTP and HP technologies.

Fig. 3: (a) Transfer characteristics show improved subthreshold

characteristics by using low-k spacer. εspacer is the dielectric constant of the
spacer material. (b) The parallel component ξx (along x direction) of electric
field at the source/channel junction; (c) the vertical component ξy (along y
direction) of electric field at the gate dielectric/channel interface. The insets
in (b) and (c) show the cross sectional view of the device topology being
studied. The dashed red lines in the insets indicate the locations where
electric fields are extracted.
Fig. 6: Output resistance Rout extracted from the output characteristics
(the method has been explained in Fig. 2(d)) for 1L-3L MoS2 FETs and
Si UTB DG FETs. MoS2 FETs show much higher Rout compared to Si
devices, indicating that they exhibit better saturation characteristics. The
general observation is that the smaller the channel thickness, the better
the electrostatics, and higher the Rout.

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 Fig. 7: SS improvement and extra series resistance introduced by using
underlap (UL) structure for 1L-3L MoS2 FETs. The inset in the subplot for
2L is a schematic illustration of the UL structure.
Fig. 11: The effective mass is varied to meet the LSTP requirement at 5.9 nm
node in the case of (a) UL= 0 nm and (b) UL= 1 nm. (c) Id-Vg curves with
different effective mass. Comparing (a) and (b), it can be found that with the
aid of UL, materials with effective mass around 0.3m0, and “mobility” higher
than 190 cm2/V·s can meet the LSTP requirement. The reason is that with
smaller effective mass, carrier velocity is higher, and thus Ion can be higher.
However, aggressively small effective mass will lead to increased
source-to-drain (S-to-D) tunneling leakage as shown in (c), and significantly
degrade Ion, which can be observed in (a) and (b). UL can help suppress
S-to-D tunneling and derive more benefits from reduced effective mass.

Fig. 8: Top: Ion versus gate length for 1L-3L MoS2 FETs. 2L MoS2 with 0-1
nm UL can meet the HP requirement except for the smallest 5.9 nm node.
Bottom: 1L MoS2 with 1 nm UL is closest to the LSTP requirement. The
best choice is 2L with 1 nm UL for HP, and 1L with 1 nm UL for LSTP.

Fig. 12: Collected data of mobility
(experiment) and effective mass
(first principle calculation) for
various 2D semiconductors (1L-2L).
Green block is the required range of
values for HP, and blue block is for
LSTP. Since experimental data is still
lacking for the mobility of 1L-2L
black phosphorus, a dashed-line
error bar is used for an estimation
according to an effective mass based
rough calculation [13].
Fig. 13: Ion versus gate length in the
case of scaled and unscaled supply
voltage Vdd. Without scaling Vdd, both
HP and LSTP requirement can be
easily met, which indicates that we
need to consider relaxing constraint
on Vdd scaling or turn to sub-kT/q
devices such as tunnel FETs for below
5 nm nodes. Alternatively, 3D IC
integration with 2D materials could
provide an alternative pathway to
scaling beyond the 5 nm node.

Table II: A summary of possible material/structure/technology choices for

sub-10 nm HP and LSTP VLSI applications.

Fig. 9: Ion versus gate length for
1L-3L MoS2 FETs obtained by
ballistic simulation. HP
requirement can be met, while
LSTP requirement for below 7 nm
nodes cannot, indicating that only
improving “mobility” is not
enough for LSTP.
Fig. 10: The “mobility” is varied to
meet (a) HP and (b) LSTP requirements
at the 5.9 nm node. “2L, UL=1nm” only
requires a “mobility” of 138 for HP,
which has been experimentally
achieved in 1L WSe2 [12]. Improved
“mobility” with the aid of UL is not
enough to meet LSTP requirement.

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