Module - 1

8051 - Microcontroller
Module – 1
8051 Microcontroller
Microprocessor vs Microcontroller:
General-purpose microprocessors:
Must add RAM, ROM, I/O ports, and timers externally to make them functional.
Make the system bulkier and much more expensive.
Have the advantage of versatility on the amount of RAM, ROM, and I/O ports.
Microcontroller:
The fixed amount of on-chip ROM, RAM, and number of I/O ports makes them ideal
for many applications in which cost and space are critical.
In many applications, the space it takes, the power it consumes, and the price per unit
are much more critical considerations than the computing power
Fig. 1. General-Purpose Microprocessors Fig. 2. Microcontroller
Dept. Of ECE CMR Institute of Technology Bengaluru 1

Microprocessor Microcontroller
Microprocessor contains ALU, General Microcontroller contains the circuitry of
purpose registers, stack pointer, program microprocessor, and in addition it has built in
counter, clock timing circuit, interrupt circuit ROM, RAM, I/O Devices, Timers/Counters
etc.
It has many instructions to move data between It has few instructions to move data between
memory and CPU memory and CPU
Few bit handling instruction It has many bit handling instructions
Less number of pins are multifunctional More number of pins are multifunctional
Single memory map for data and code Separate memory map for data and code
(program) (program)
Access time for memory and IO are more Less access time for built in memory and IO.
Microprocessor based system requires It requires less additional hardware
additional hardware
More flexible in the design point of view Less flexible since the additional circuits which
is residing inside the microcontroller is fixed for
a particular microcontroller
Large number of instructions with flexible Limited number of instructions with few
addressing modes addressing modes
Microcontroller has
 The fixed amount of on-chip ROM, RAM, and number of I/O ports makes
them ideal for many applications in which cost and space are critical.
 In many applications, the space it takes, the power it consumes, and the
price per unit are much more critical considerations than the computing
power.
An embedded product uses a microprocessor (or microcontroller) to do one task
and one task only. There is only one application software that is typically burned
into ROM.

A PC, in contrast with the embedded system, can be used for any number of
applications:
 It has RAM memory and an operating system that loads a variety of
applications into RAM and lets the CPU run them.
 PC contains or is connected to various embedded products. Each one
peripheral has a microcontroller inside it that performs only one task.
Examples for embedded systems are:

 Home:
Appliances, intercom, telephones, security systems, garage door openers,
answering machines, fax machines, home computers, TVs, cable TV
tuner, VCR, camcorder, remote controls, video games, cellular phones,
musical instruments, sewing machines, lighting control, paging, camera,
pinball machines, toys, exercise equipment
 Office:
Telephones, computers, security systems, fax machines, microwave,
copier, laser printer, color printer, paging
 Auto:
Trip computer, engine control, air bag, ABS, instrumentation, security
system, transmission control, entertainment, climate control,
cellular phone, keyless entry
Choosing a Microcontroller:
In market microcontroller are available with different
sizes. Ex:
Popular 8-bit microcontrollers are
· Motorola’s 6811
· Intel’s 8051
· Zilog’s Z8
· Microchip’s PIC
There are also 16-bit and 32-bit Microcontrollers made by various chip makers.

Criteria for Choosing a Microcontroller:
 Meeting the computing needs of the task at hand efficiently and cost
effectively
o Speed
o Packaging
o Power consumption
o The amount of RAM and ROM on chip
o The number of I/O pins and the timer on chip
o How easy to upgrade to higher performance or lower power-consumption
versions
o Cost per unit
 Availability of software development tools, such as compilers, assemblers,
and debuggers
 Wide availability and reliable sources of the microcontroller
 The 8051 family has the largest number of diversified (multiple source)
suppliers
o Intel (original)
o Atmel
o Philips/Signetics
o AMD
o Infineon (formerly Siemens)
o Matra
o Dallas Semiconductor/Maxim

8051 Microcontroller Architecture:
The 8051 has an 8-bit processor. The CPU can work on only 8 bits of data at a time.
Salient features of 8051 microcontroller are given below,
 Eight bit CPU

 On chip clock oscillator
 4Kbytes of internal program memory (code memory) [ROM]
 128 bytes of internal data memory [RAM]
 64 Kbytes of external program memory address space.
 64 Kbytes of external data memory address space.
 32 bi directional I/O lines (can be used as four 8 bit ports or 32
individually addressable I/O lines)
 Two 16 Bit Timer/Counter :T0, T1
 Full Duplex serial data receiver/transmitter
 Four Register banks with 8 registers in each bank.
 Sixteen bit Program counter (PC) and a data pointer (DPTR)
 8 Bit Program Status Word (PSW)
 8 Bit Stack Pointer
 Five vector interrupt structure (RESET not considered as an interrupt.)
 8051 CPU consists of 8 bit ALU with associated registers like
accumulator ‘A’, B register, PSW, SP, 16 bit program counter, 8- bit
stack pointer.
 ALU can perform arithmetic and logic functions on 8 bit variables.
 8051 has 128 bytes of internal RAM which is divided into
o Working registers [00 – 1F]
o Bit addressable memory area [20 – 2F]
o General purpose memory area (Scratch pad memory) [30-7F]
The 8051 became widely popular after allowing other manufactures to make
and market any flavor of the 8051, but remaining code-compatible

Architecture of 8051

Architecture or Block Diagram of 8051
The above figure shows the usual CPU components: program counter, ALU,
working registers, and clock circuits.
 8051 has 4 K Bytes of internal ROM. The address space is from 0000 to
0FFFh. If the program size is more than 4 K Bytes 8051 will fetch the code
automatically from external memory.
 Accumulator is an 8 bit register widely used for all arithmetic and logical
operations. Accumulator is also used to transfer data between external
memory. B register is used along with Accumulator for multiplication and
division. A and B registers together is also called MATH registers.
 PSW (Program Status Word). This is an 8 bit register which contains the
arithmetic status of ALU and the bank select bits of register banks.
 A and B CPU Registers
• The 8051 contains 34 general-purpose, or working, registers. Two of
these, registers A and B.
• The other 32 are arranged as part of internal RAM in four banks, BO-
B3, of eight registers each, named RO to R7.
 Stack Pointer (SP) – It is an 8-bit register.It contains the address of the data
item on the top of the stack. Stack may reside anywhere on the internal
RAM. On reset, SP is initialized to 07H so that the default stack will start
from address 08 onwards.
 Data Pointer (DPTR) – DPH (Data pointer higher byte), DPL (Data pointer
lower byte)-This is a 16 bit register which is used to furnish address
information for internal and external program memory and for external data
memory. 
 Program Counter (PC) – 16 bit PC contains the address of next instruction
to be executed. On reset PC will set to 0000. After fetching every
instruction PC will increment by one automatically.
 8051 has four 8-bit I/O ports P0, P1, P2 and P3. All the ports upon RESET
are configured as input, ready to be used as input ports.
 Port 0 can be used as input or output and also designated as AD0-AD7,
allowing it to be used for both address and data.

 Port 1 can be used as input or output only

 Port 2 can be used as input or output and Port 2 is also designated as A8 –
A15, indicating its dual function
 Port 3 can be used as input or output and also has the additional function of
providing some extremely important signals for serial communication,
external interrupt, timer inputs and external RAM access.
 8051 has 128 bytes of Internal RAM which is divided into three different
groups as follows:
 A total of 32 bytes from locations 00 to 1F hex are set aside for register
banks and the stack.
 A total of 16 bytes from locations 20H to 2FH are set aside for bit
addressable read/write memory.
 A total of 80 bytes from locations 30H to 7FH are used for read and
write storage, called scratch pad.
Register Set of 8051:

Register are used to store information temporarily, while the information could be,
- A byte of data to be processed, or
- An address pointing to the data to be fetched
The vast majority of 8051 register are 8-bit registers.
The 8 bits of a register are shown from MSB D7 to the LSB D0. With an 8-bit data
type, any data larger than 8 bits must be broken into 8-bit chunks before it is
processed.

The most widely used registers are

 (Accumulator) for all arithmetic and logic instructions.
 B, R0, R1, R2, R3, R4, R5, R6, R7
 DPTR (data pointer), and PC (program counter)
Register Set of 8051
The Programming Model of 8051 Microcontroller:

The programming model of the 8051 shows the collection of 8- and 16-bit registers
and 8- bit memory locations. These registers and memory locations can be made to
operate using the software instructions that are incorporated as part of the design.
• The A (accumulator) register is used for many operations, including

addition, subtraction, integer multiplication and division, and Boolean
bit manipulations.
• The A register is also used for all data transfers between the 8051
and any external memory.
• The B register is used with the A register for multiplication and division
operations.
Program Counter (PC) and Data Pointer (DPTR)

• Program instruction bytes are fetched from locations in memory that are
addressed by the PC.
• The PC is automatically incremented after every instruction byte is
fetched and may also be altered by certain instructions.
• The PC is the only register that does not have an internal address.
• The DPTR register is made up of two 8-bit registers, named DPH and DPL
• Are used to furnish memory addresses for internal and external code
access and external data access.
• The DPTR is under the control of program instructions
• Can be specified by its 16-bit name, DPTR, or by each individual byte name,
DPH and DPL.
• DPTR does not have a single internal address; DPH and DPL are each
assigned an address.

Flags and the Program Status Word (PSW) of 8051:

• PSW is an 8-bit register. It is also called the “Flag register”, as it mainly
contains the status flags. These flags indicate status of the current result.
• They are changed by the ALU after every arithmetic or logic operation. The
flags can also be changed by the programmer.
• PSW is a bit addressable register. Each bit can be individually set or reset by
the programmer. The bits can be referred to by their bit numbers (PSW.4) or
by their name (RS1).
• Other instructions can test the condition of the flags and make decisions
based upon the flag states.
Program status word of 8051
CY - CARRY FLAG:
This flag is set whenever there is a carry out of MSB bit that is from D7 th bit. This
flag bit is affected after an 8-bit addition or subtraction.
If CY = 1 : There was a carry out of the MSB
If CY = 0 : There was no carry out of the MSB
This carry flag bit can be set 1 or 0 directly by an instruction such as "SETB C" (set
bit carry) and "CLR C" (clear carry.

AC – AUXILIARY CARRY FLAG:

It indicates the carry from lower nibble (4-bits) to higher nibble.
If the 8 bits are numbered Bit 7 --- Bit 0, this is the carry from Bit 3 to Bit 4.
If AC = 1 : There was an auxiliary carry
If AC = 0 : There was no auxiliary carry
Note: It is particularly useful in an operation called DA A (Decimal Adjust after
Addition).
OVR - OVERFLOW FLAG:

This flag is set whenever the result of signed number operation is too large, causing
the higher-order bit to overflow into the sign bit. The overflow flag is used to detect
errors in signed arithmetic operations.
An 8-bit signed number has the range -80H… ,-01H,00H,… +7FH (Decimal -128
…,-01,00,….+127). Any result, out of this range causes an overflow.
If OVR = 1 : There was an overflow in the result
If OVR = 0 : There was no overflow in the result
Overflow is determined by doing an Ex-Or between the 2nd last carry (C6) and the
last carry (C7)
Note: After an overflow, the Sign (MSB) of the result becomes wrong.
P - PARITY FLAG:
The parity flag reflects the number of 1's in A (accumulator) register only.It indicates
the Parity of the result.
If PF = 1 : The register ‘A’ has ODD number of 1’s
If PF = 0 : The register ‘A’ has EVEN number of 1’s
F0 – USER DEFINED FLAG:

This flag is available to the programmer.
It can be used by us to store any user defined information.
For example: In an Air Conditioning unit, programmer can use this flag indicate
whether the compressor is ON or OFF (1 or 0). This flag can be changed by simple
instructions like SETB and CLR.
SETB PSW.5; This makes F0 bit = 1

CLR PSW.5; This makes F0 bit = 0
RS1, RS0 – REGISTER BANK SELECT:

The initial 32 locations (bytes) of the Internal RAM are available to the programmer
as registers.
Having so many registers makes programming easier and faster.
Naming R0… R31, would tremendously increase the number of opcodes.
Hence the registers are divided into 4 banks: Bank0… Bank3.
Each bank has 8 registers named R0… R7.
At a time, only one register bank is active out of the four register banks.
RS1 and RS0 are used by the programmer to select the active bank as shown in the
table below.

The result 86H is out of range for a “Signed” Number as it has become greater than
+7FH. Such an event is called a “Signed Overflow”. In such a case the MSB of the
result gives a wrong sign. Though the result is +ve (+86H) the MSB is “1” indicating
that the result is –ve. Overflow is determined by doing an Ex-Or between the 2nd last
Carry and the last Carry. Here the 2nd last Carry (the one coming into the MSB) is
“1”. The final carry (The one going out of the MSB) is “0”. As “1” Ex-Or “0” = “1”,
the Overflow flag is “1”.

Pin Diagram 0f 8051:
Pin Description:
8051 has 40 pins. The function of these pins is briefly explained as follows.
XTAL1 These are connected to the crystal oscillator. The typical operating frequency is 12
& MHz. In Serial communication based applications, the operating frequency is
XTAL2 chosen to be 11.0592 MHz, in order to derive the standard universal baud rates.
This will be discussed in detail in the further chapters.
It is used to reset the 8051 microcontroller.
RESET A logic one on this pin disables the microcontroller and clears the contents of most
registers. In other words, the positive voltage on this pin resets the microcontroller.
By applying logic zero to this pin, the program starts execution from the beginning that
is PC becomes 0000H. This address is called the reset vector address. From here,
8051 executes the BIOS program also called the Booting program or the monitor
program.

ALE It is used to enable the latching of the address. The address and data buses are
multiplexed. This is done to reduce the number of pins on the 8051 IC.
(Address
Latch Once out of the chip, address and data have to be separated that is called
Enable)
de-multiplexing. This is done by a latch, with the help of ALE signal.
ALE is “1” when the bus carries address and “0” when the bus carries data.
This informs the latch, when the bus is carrying address so that the latch captures
only address and not the data.
EA It decides whether the first 4 KB of program memory space (0000H… 0FFFH)
(Enable
will be assigned to internal ROM or External ROM.
External
Access) If EA = 0, the External ROM begins from 0000H. In this case the Internal ROM
is discarded (means not used). 8051 now uses only External ROM.
If EA = 1, the External ROM begins from 1000H. In this case the Internal ROM
is used. It occupies the space 0000H… 0FFFH.
In modern FLASH ROM versions, this pin also acts as VPP (12 Volt
programming voltage) to write into the FLASH ROM.
 This should allow 8051 to access 64 KB of external ROM Memory as 216 = 64
PSEN KB.
(Program  Interestingly though, 8051 can access 64 KB of External ROM and 64 KB of
Store External RAM, making a total of 128 KB.
Enable):  Both have the same address range 0000H to FFFFH.
 This does not lead to any confusion because there are separate control signals
 for External RAM and External ROM.
 RD and WR are control signals for External RAM.
 PSEN is the READ signal for External ROM.
 It is called Program Store Enable as it allows reading from ROM also known
as Program Memory.
Vcc & GND These are power supply pins. 8051 works at +5V / 0V power supply.
Port 0  These are 8 pins of Port 0. We can perform a byte operation (8-bit) on the
P0.0… P0.7
whole port 0. We can also access every bit of port 0 individually by
performing bit operations like set, clear, complement etc.
 The bits are called P0.0… P0.7. Additionally, Port 0 also has an alternate
function. It carries the multiplexed address data lines. A0-A7 (the lower 8 bits
of address) and D0-D7 (8 bits of data) are multiplexed into AD0-AD7.

 In any operation address and data are not issued simultaneously. First, address
is given, then data is transferred. Using a common bus for both, reduces the
number of pins.
 To identify if the bus is carrying address or data, we look at the ALE signal.
If ALE = 1, the bus carries address, If ALE = 0, the bus carries data.
Port 1 These are 8 pins of Port 1. We can perform a byte operation (8-bit) on the whole
P1.0… P1.7
port 1. We can also access every bit of port 1 individually by performing bit
operations like set, clear, complement etc. on P1.0… P1.7.
Port 1 also has NO alternate function.
P2.0… P2.7
port 2. We can also access every bit of port 2 individually by performing bit
operations like set, clear, complement etc. on P2.0… P2.7.
Additionally, Port 2 also has an alternate function. It carries the higher order
address lines A8-A15.
P3.0… P3.7
port 3. We can also access every bit of port 3 individually. The bits are called
P3.0… P3.7. The various pins of Port 3 have a lot of alternate functions.
P3.0 (RXD) They are used to receive and transmit serial data. This forms the serial port of
and
8051.
P3.1 (TXD)
P3.2( ∫ 0 ) They are external hardware interrupts of 8051.
and If they occur simultaneously, INT0 is by default higher priority.
P3.3 ( ∫ 1)
P3.4 (T0) They are used timer clock inputs.
and
They provide external clock inputs to Timer 0 and Timer 1
P3.5 (T1)
P3.6 ( WR ) They are used as control signals for External RAM.
and
8051 can access 64 KB External RAM from 0000H to FFFFH.
P3.7 ( RD )

The 8051 Oscillator and Clock:

• Clock is used to synchronize all operations.
• Pins XTAL1 and XTAL2 connects to resonant circuit to form an oscillator.
• 8051 designs can run at maximum and minimum frequencies.
• Typically 1MHz to 16MHz.
• Internal memories are dynamic and must always operate above
minimum frequency.
• Ceramic resonators are used as a low cost alternative to crystal resonators.
• Clock frequency (f), with smallest interval of time within microcontroller
called the pulse (P).
C ×12 d
• Tinst =
crystal frequency
• C= number clock cycles per instruction
• Typically 11.0592 MHz crystal is used to generate baudrates of 19200,
9600, 4800, 2400, 1200.
• Internal counters must divide the basic clock rate to yield standard
communication bit per second rates(Baud rates).

Memory organization of 8051:

8051 operates with 4 different memories:
Internal RAM
External RAM
Internal ROM
External ROM
Internal RAM of 8051: (Data Memory)
Structure of internal RAM of 8051
Note: Write any one diagram for internal RAM

Structure of internal RAM of 8051
8051 has a 128 Bytes of internal RAM. These are 128 locations of 1 Byte each. The
address range is 00H… 7FH. This RAM is used for storing data. It is divided into
three main parts: Register Banks, Bit addressable area and a general purpose area.
A. Register Banks:
 The first 32 locations (Bytes) of the Internal RAM from 00H… 1FH, are used
by the programmer as general purpose registers. Having so many general
purpose registers makes programming easier and faster.
 These 32 registers are divided into 4 banks, each having 8 Registers R0… R7.
 The first 8 locations 00H… 07H are registers R0… R7 of bank 0. Similarly
locations 08H… 0FH are registers R0… R7 of bank 1 and so on. A register can
be addressed using its name, or by its address.
Eg: Location 00H can be accessed as R0, if Bank 0 is the active bank.
MOV A, R0 ; “A” register gets data from register R0.
It can also be accessed as Location 00H.
MOV A, 00H; “A” register gets data from Location 00H.

 The appropriate bank is selected by the RS1, RS0 bits of PSW. Since PSW is
available to the programmer, any Bank can be selected at run-time. Bank 0 is
selected by default, on reset.
B. Bit Addressable RAM: 20h to 2Fh:

 The next 16-bytes of RAM, from 20H… 2FH, is available as Bit Addressable
Area.
 We can perform ordinary byte operations on these locations, as well as bit
operations.
 As each location has 8-bits, we have a total of 16 × 8 = 128 Addressable Bits.
 These bits can be addressed using their individual address 00H … 7FH.
SETB 00H ; Will store a “1” on the LSB of location 20H
CLR 07H ; Will store a “0” on the MSB of location 20H
 Normal “BYTE” operations can also be performed at the addresses: 20H …
2FH.
MOV 20H, #00H ; Will store a “0” on all 8-bits of location 20H.
 The entire internal RAM is of 128 bytes so the byte address range is 00H…
7FH.
 The bit addressable area has 128 bits so its bit addresses are also 00h… 7FH.
 This means every address 00H… 7FH can have two meanings, it could be a
byte address or a bit address. This does not lead to any confusion, because the
instruction in which we use the address, will clearly indicate whether it is a bit
operation or a byte operations.
SETB, CLR etc. are bit operations whereas ADD, SUB etc. are byte
operations.
SETB 00H ; This is a bit operation. It will make Bit location 00H
; contain a value “1”.
MOV A, 00H ; This is a byte operation. “A” register will get 8-bit data
; from byte location 00H.
 Addressable bits are useful when the program need only remember a binary event
(switch on, light off, etc.).

C. General Purpose RAM: 30H to 7FH.

 A general-purpose RAM area above the bit area, from 30H to 7FH, addressable
as bytes.
 Even if 80 bytes of Internal RAM memory are available for general-purpose
data storage, user should take care while using the memory location from 00 -
2Fh since these locations are also the default register space, stack space, and
bit addressable space.
 It is a good practice to use general purpose memory from 30 – 7Fh. The
general purpose RAM can be accessed using direct or indirect addressing
modes.
External RAM:
 External RAM (data) memory is read or write memory.
 64 KB of External RAM can be connected with 8051 microcontroller.
 All addresses from 0000H… FFFFH will be accessed from External RAM.
 Since external RAM memory is indirectly accessed through a data pointer
register, DPTR (which must be loaded with an address), it is a slower process
compared to accessing the internal RAM memory.
 The 8051 is organized so that data memory and program code memory can be
in two entirely different physical memory entities; each has the same address
ranges.

ROM Organization / Code Memory / Program Memory:

We can implement ROM in three different ways in 8051. The following diagram
illustrates the ROM organization in 8051.
1. Only Internal ROM:

 8051 has 4 KB internal ROM.
 In many cases this size is sufficient and there is no need for connecting
External ROM.
 Such systems use only Internal ROM of 8051.
 Internal ROM, occupies code address space 0000H to 0FFFH.
 Any address beyond that will be invalid.
 The PC is ordinarily used to address program code bytes from addresses
0000H to 0FFFH.
 In such systems EA will be “1” as Internal ROM is being used.

2. Internal And External ROM:

 8051 has 4 KB internal ROM.
 In many cases this size is may not be insufficient and we may need to add
some External ROM.
 Such systems use a combination of Internal ROM and External ROM.
 The total ROM that can be accessed is 64 KB.
 Since we are using the Internal ROM of 4 KB, the maximum amount of
External ROM that can be connected is 60 KB.
 All addresses from 0000H… 0FFFH will be accessed from Internal ROM.
 Addresses 1000H… FFFH will be accessed from External ROM.
 In such systems EA will be “1” as Internal ROM is being used.
3. Only External ROM:

 Though 8051 has 4 KB of Internal ROM, the user may choose to discard it
and connect only External ROM.
 This may happen due to several reasons. The program stored in the Internal
ROM may have become invalid or outdated, or the system may need to be
upgraded etc.
 Such systems use only External ROM, and the Internal ROM is discarded.
 Here we can connect up to 64 KB of External ROM.
 All addresses from 0000H… FFFFH will be accessed from External ROM.
 But do keep in mind, that the Internal ROM is still present in 8051.
 We need to clearly indicate to 8051 that the Internal ROM must be ignored
and every address from 0000H… FFFFH must be accessed externally. This is
indicated by us to 8051 using EA .
 By making EA = 0, we inform 8051 that the Internal ROM must be discarded
and all ROM must be accessed externally

SFR registers and their addressees:

 Among the registers that we have discussed so far, R0 - R7 are part of the
128 bytes of RAM memory.
 In 8051, register A, B, PSW, DPTR etc., are part of the group of registers
commonly referred to as SFR(special function registers).
 The SFR can be accessed by their names or by their addresses.
 The SFR registers have addresses between 80H and FFH.
Notice how the following pairs of instructions mean the same thing
MOV 0E0H,#55H ;is the same as
MOV A,#55h ;load 55H into A
MOV 0F0H,R0 ;is the same as

MOV B,R0 ;copy R0 into B
 Not all the address space of 80H to FFH is used by SFR . The unused
locations 80H to FFH are reserved and must not be used by the 8051
programmer.
 While all of the SFR registers are byte addressable, some of them are also
bitaddressable.
 Only registers A, B, PSW, IP, IE, ACC, SCON, and TCON , P0, P1, P2, P3
are bit-addressable.
 Ex. SETB P1.5 sets bit 5 of port 1 high.

The SFR's of 8051 are listed in the table below,


Memory Address Decoding:

The CPU provides the address of the data desired, but it is the job of the decoding
circuitry to locate the selected memory block.
 Memory chips have one or more pins called CS (chip select), which must be
activated for the memory’s contents to be accessed.
 Sometimes the chip select is also referred to as chip enable (CE )
In connecting a memory chip to the CPU, note the following points,
 The data bus of the CPU is connected directly to the data pins of the memory chip
 Control signals RD . (read) and WR (memory write) from the CPU are connected
to the OE (output enable) and WE (write enable) pins of the memory chip.
 In the case of the address buses, while the lower bits of the address from the
CPU go directly to the memory chip address pins, the upper ones are used to
activate the CS pin of the memory chip.
 Usually CS pin of the memory block is active low and is activated by the output
of memory address decoder.
 Normally memories are divided into blocks and the output of the decoder selects
a given memory block,
 Using simple logic gates.
 Using the 74LS138 decoder.
 Use of simple logic gate as address decoder:

Example: Use NAND gate as an address decoder for 4KB memory block. Use the
addresses from 3000H for memory block.
Solution:
No. Of address lines required to interface 4KB memory block is calculated as follows,
Size of memory chip = 2n
where n = no. of address lines required to uniquely address all locations in memory
chip.
Therefore, 4KB = 4 x 210 Bytes = 22 x 210 = 212
A11 - A0 address lines are connected to the memory block for selecting the memory
locations and remaining address line A15 - A12 are used for selecting the chip select
pin CS .

Memory Mapping:
Starting Address: 3000 H
Ending address: 3FFF H
A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A4 A3 A2 A1 A0
Start Address 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
4KB Memory Block
End Address 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Note:
For 4KB memory size required address lines are 12 and to find the end address add twelve 1’s to
the start address. That is in hexadecimal form for start address add FFFH.
For example: If start address is 0000H then end address will be 0FFFH for 4KB memory block.
And if the start address is 3000H then end address is 3FFFh.
Based on the above memory map table we can write the memory block interfacing as
follows,
Fig. Showing the use of simple NAND gate as address decoder.
 Memory address decoding using 74LS138, 3 - 8 decoder.

 74LS138 decoder have 3 inputs A, B, and C and generate 8 active low outputs Y 0
– Y 7. Each Y output is connected to CS pin of a memory chip, allowing control of
8 memory blocks by a single 74LS138
 In the 74LS138, where A, B, and C select which output is activated, and it has three
enable inputs, G 2 A , G 2 B and G1.
 If any one of the inputs G1, G 2 A , G 2 B are not connected to an address signal,
they must be activated permanently either by Vcc or ground, depending on the
activation level.
Ex: Use of 74LS138 decoder as an memory address decoder for 4KB memory block.
Use the addresses from 3000H for memory block.
Memory Map:
Starting Address: 3000 H and Ending address: 3FFFH
Start Address 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
4KB Memory Block
End Address 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A14 A13 A12 = 011 are given as 3 inputs to the decoder, then Y3 output of decoder
gets activated.
This Y 3 output of decoder should be connected to CS pin of memory block.
A15 = 0 can be connected to enable pin G 2 A active low pin.
G 2 B enable pin is connected to GND. And
G1 which is active high enable pin hence connected to Vcc, as shown in the Fig.
below.

Fig. Showing use of simple 74LS138 decoder as memory address decoder.
In the 8051, port 0 and port 2 provide the 16-bit address to access external memory,
 P0 provides the lower 8-bit address A0 – A7, and
 P2 provides the upper 8-bit address A8 – A15
 P0 is also used to provide the 8-bit data bus D0 – D7
 P0.0 – P0.7 are used for both the address and data paths (address/data
multiplexing).
ALE (address latch enable) pin is an output pin for 8051:

 If ALE = 0, P0 is used for data path
 If ALE = 1, P0 is used for address path
To extract the address from the P0 pins, we connect P0 to a 74LS373 latch and use the
ALE pin to latch the address.
 Normally ALE = 0, and P0 is used as a data bus, sending data out or bringing
data in towards microcontroller.
 Whenever the 8051 wants to use P0 as an address bus, it puts the addresses A0
– A7 on the P0 pins and activates ALE = 1
Following diagram depicts, how the 74LS373 latch can be used to demultiplex the
address and the data from the port 0 pins of 8051 microcontrollers.

Fig. Illustrates the demultiplexing of the address and the data from the port 0 pins of 8051
microcontroller.
External Memory (ROM & RAM) interfacing with 8051

Microcontroller:
1. Interface 8KB ROM chip with 8051?
Solution: Starting address for ROM should be always 0000H.
8KB = 8 x 210 Bytes = 23 x 210 = 213
locations and remaining address line A15 - A13 are used for selecting the chip select
pin CS .
Memory Mapping for ROM:
Starting Address: 0000 H and Ending address: 1FFFH
Start Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8KB ROM Memory
End Address 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
PSEN (program store enable) signal is an output signal for the 8051 microcontroller
and must be connected to the OE pin of a ROM containing the program code.
It is important to emphasize the role of EA and PSEN when connecting the 8051 to
external ROM. When the EA pin is connected to GND, the 8051 fetches opcode
from external ROM by using PSEN .

Below two interfacing diagrams are shown, where in the first design simple NAND
gate is used as address decoder. And
In second design 74LS138 decoder is used as address decoder to generate chip select
signal CS for ROM chip. (Here enable pins G1 which is active high hence connected
to Vcc , G 2 A and G 2 B are active low hence grounded).
Fig. Showing Interfacing of 8KB ROM with 8051 Microcontroller using NAND gate as
address Decoder
Fig. Showing Interfacing of 8KB ROM with 8051 Microcontroller using 74LS138, 3 to 8
decoder as address Decoder.
Note: Any one of the above design can be written for the given question.

2. Interface 4KB RAM chip with 8051 microcontroller. Take RAM starting
address at 8000H. Show the design using a 74LS138 as the address
decoder.
Solution: 4KB = 4 x 210 Bytes = 22 x 210 = 212

locations.
Memory Mapping for RAM:
Starting Address: 8000 H and
Ending address: 8000 + 0FFFH = 8FFFH
(End address can be calculated by adding size of chip i.e., no. of memory locations in the chip. It can
be found by adding twelve 1’s to starting address in binary)
Start Address 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4KB RAM Memory
End Address 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Address line A14, A13, A12 are given as input to 3-8 decoder, the output Y0 is
activated and is connected for chip select pin CS .
A15 =1 and can be connected to enable ‘G1’ pin which is active high pin of the
decoder.
G 2 A and G 2 B can be grounded.
RD and WR are control signals for External RAM and are connected to OE and WE
pins of RAM chip.

3. Interface 4KB ROM and 4KB RAM chip with 8051 microcontroller.
Solution:
 For 4KB memory chip number of address lines required are 12, i.e., A11 – A0.
 For ROM memory chip start address is 0000H and end address is 0FFFH.
 For RAM memory chip start address can be considered as immediate next
memory address after ROM end address.
 Hence for RAM chip start address is 1000H and end address is 1FFFH.
Memory Mapping:
Start Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4KB ROM Memory
End Address 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Start Address 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
4KB RAM Memory
End Address 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

Since the ROM and RAM chips are of 4KB in size, 12 address lines A11 – A0 are
connected to them from 8051 P0 and P2 pins.
To select the ROM and RAM chips uniquely, remaining address lines can be utilized.
If we observe A14, A13, A12 address lines from the above table, these 3 address lines
can be given as input to 74LS138, 3-8 decoder and ROM and RAM chips can be
selected uniquely as given below,
If A14, A13, A12 = 0, 0, 0 ; Then output Y 0 gets activated and it can be connected
;to CS pin of ROM chip.
If A14, A13, A12 = 0, 0, 1 ; Then output Y 1 gets activated and it can be connected
; to CS pin of RAM chip.
Interfacing diagram is shown in the figure below.
Fig. showing the interfacing diagram of 4KB ROM and 4KB RAM chip with the 8051 microcontroller

4. Interface 8KB ROM and 4KB RAM chip with 8051 microcontroller.
Solution:
 For 8KB ROM memory chip number of address lines required are 13, i.e.,
A12 – A0. And for 4KB RAM chip number of address lines required are 12,
i.e., A11 – A0.
 For 8KB ROM memory chip start address is 0000H and end address is
1FFFH.
 For RAM memory chip start address can be considered as immediate next
memory address after ROM end address.
 Hence for 4KB RAM chip start address is 2000H and end address is 2FFFH.
Memory Mapping:
Start Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8KB ROM Memory
End Address 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Start Address 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
4KB RAM Memory
End Address 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
To select the ROM and RAM chips uniquely, we can use A14, A13, A12 address
lines, these 3 address lines can be given as input to 74LS138, 3-8 decoder and ROM
and RAM chips can be selected uniquely as given below,
If A14, A13, A12 = 0, 0, 0 OR 0, 0, 1 ; Then output Y 0 or Y 1 gets activated
;and it can be connected to CS pin of
;ROM chip by using OR ;gate.
If A14, A13, A12 = 0, 1, 0 ; Then output Y 2 gets activated and it
;can be connected to CS pin of RAM
chip.
Interfacing diagram is shown in the figure below.

Fig. showing the interfacing diagram of 8KB ROM and 4KB RAM chip with the 8051 microcontroller

 Stack and Direct Addressing Mode:
 The stack is a section of RAM used by the CPU to store information

temporarily. This information could be data or an address.
 The register used to access the stack is called the SP (stack pointer) register.
 The stack pointer in the 8051 is only 8 bit wide, which means that it can take
value of 00 to FFH.
 When the 8051 is powered up, the SP register contains value 07H (i.e.,On
reset SP gets the value 07H )
 RAM location 08H is the first location being used for the stack by the 8051.
 PUSH:
 The storing of a CPU register in the stack is called a PUSH.
 SP is pointing to the last used location of the stack.
 As we push data onto the stack, the SP is incremented by one. Then data
stored in the stack
 Direct addressing mode is used for pushing onto the stack.
 To PUSH register on to the stack we must use their RAM addresses.
Syntax: PUSH addr
Example: (1)

Example: (2)
 POP:
 Loading the contents of the stack back into a CPU register is called a POP.
 With every pop, the top byte of the stack is copied to the register specified by
the instruction and the stack pointer is decremented once.

Syntax: POP addr
Example (1):

Example (2):


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8051 - Microcontroller

Make the system bulkier and much more expensive.

Fig. 1. General-Purpose Microprocessors Fig. 2. Microcontroller

Dept. Of ECE CMR Institute of Technology Bengaluru 1

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Examples for embedded systems are:

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Criteria for Choosing a Microcontroller:

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8051 Microcontroller Architecture:

 Eight bit CPU

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Architecture or Block Diagram of 8051

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 Port 1 can be used as input or output only

Register Set of 8051:

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The most widely used registers are

Register Set of 8051

The Programming Model of 8051 Microcontroller:

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• The A (accumulator) register is used for many operations, including

Program Counter (PC) and Data Pointer (DPTR)

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Flags and the Program Status Word (PSW) of 8051:

Program status word of 8051

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AC – AUXILIARY CARRY FLAG:

OVR - OVERFLOW FLAG:

F0 – USER DEFINED FLAG:

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CLR PSW.5; This makes F0 bit = 0

RS1, RS0 – REGISTER BANK SELECT:

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Pin Diagram 0f 8051:

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The 8051 Oscillator and Clock:

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Memory organization of 8051:

Internal RAM of 8051: (Data Memory)

Structure of internal RAM of 8051

Note: Write any one diagram for internal RAM

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Structure of internal RAM of 8051

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B. Bit Addressable RAM: 20h to 2Fh:

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C. General Purpose RAM: 30H to 7FH.

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ROM Organization / Code Memory / Program Memory:

1. Only Internal ROM:

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2. Internal And External ROM:

3. Only External ROM:

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SFR registers and their addressees:

MOV 0F0H,R0 ;is the same as

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