--STEPPER MOTOR

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity STEPPERnew is
Port ( dout : out std_logic_vector(3 downto 0);
clk,reset: in std_logic;
row:in std_logic_vector(1 downto 0);
dir:in std_logic);
end STEPPERnew;
architecture Behavioral of STEPPERnew is
signal clk_div : std_logic_vector(25 downto 0);
signal clk_int: std_logic;
signal shift_reg : std_logic_vector(3 downto 0);
begin
process(clk)
begin
if rising_edge (clk) then
clk_div <= clk_div + '1';
end if;
end process;
clk_int<=clk_div(21) when row="00"else
clk_div(19) when row="01"else
clk_div(17) when row="10"else
clk_div(15) ;
process(reset,clk_int,dir)
begin
if reset='0' then
shift_reg <= "1001";
elsif rising_edge(clk_int) then
if dir='0' then
shift_reg <= shift_reg(0) & shift_reg(3 downto 1);
else
shift_reg<=shift_reg(2 downto 0) & shift_reg(3);
end if;
end if;
end process;
dout <= shift_reg;
end Behavioral;

--DC MOTER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dcmotor is
generic(bits : integer := 8 );
port ( CLK: in STD_LOGIC; -- 4 MHz clock
RESET,dir: in STD_LOGIC;
pwm : out std_logic_VECTOR(1 DOWNTO 0);
rly: out std_logic;
ROW: in STD_LOGIC_VECTOR(0 to 3 );
end dcmotor;
architecture dcmotor1 of dcmotor is
signal counter : std_logic_vector(bits - 1 downto 0):="11111110";
signal DIV_REG: STD_LOGIC_VECTOR (16 downto 0); -- clock divide register
signal DDCLK,tick: STD_LOGIC; -- this has the divided clock.
signal duty_cycle: integer range 0 to 255;
signal ROW1 : STD_LOGIC_VECTOR(0 to 3); -- this are the row lines
begin
process (CLK, DIV_REG) -- clock divider
begin
if (CLK'event and CLK='1') then
DIV_REG <= DIV_REG + 1;
end if;
end process;
DDCLK<=DIV_REG(12);
tick <= row(0) and row(1) and row(2) and row(3);
process(tick)
begin
if falling_edge(tick) then

case row is
when "1110" =>duty_cycle <= 255 ;
when "1101" =>duty_cycle <= 200 ;
when "1011" =>duty_cycle <= 150 ;
when "0111" =>duty_cycle <= 100 ;
when others =>duty_cycle <= 100;
end case;
end if;

--motor speed 1
--motor speed 2
--motor speed 3
--motor speed 4

end process;
process(DDCLK, reset)
begin
if reset = '0' then
counter <= (others => '0');
PWM<="01";
elsif (DDCLK'event and DDCLK = '1') then
counter <= counter + 1;
if counter >= duty_cycle then
pwm(1) <= '0';
else
pwm(1) <= '1';
end if;
end if;
end process;
rly<=dir;
end dcmotor1;

--square wave
entity square is
Port ( clk : in STD_LOGIC;
dout : inout STD_LOGIC_VECTOR (3 downto 0):=(others=>'0'));
end square;
architecture Behavioral of square is
signal count: STD_LOGIC_VECTOR (7 downto 0):=(others=>'0');
begin
process(clk)
begin
if rising_edge(clk)then
count<= count+1;
if count="00001111" then
dout<= not dout;
end if ;
end if;
end process;
end Behavioral;

--triangle wave
entity triangular_wave is
Port ( clk : in std_logic;
rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end triangular_wave ;
architecture Behavioral of triangular_wave is
signal counter : std_logic_vector(0 to 8);
signal temp : std_logic_vector(3 downto 0);
signal en :std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp <= temp + '1' ;
end if;
end process;
process(temp(3))
begin
if rst='1' then
counter <= "000000000";
elsif rising_edge(temp(3)) then
counter <= counter + 1 ;
if counter(0)='1' then
dac_out <=counter(1 to 8);
else
dac_out <=not(counter(1 to 8));
end if;

end if;
end process;
end Behavioral;

--Ramp Wave
entity ramp_wave is
Port ( clk : in std_logic;
rst : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end ramp_wave;
architecture Behavioral of ramp_wave is
signal temp : std_logic_vector(3 downto 0);
signal counter : std_logic_vector(0 to 7);
signal en :std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
temp <= temp + '1' ;
end if;
end process;
process(temp(3))
begin
if rst='1' then
counter <= "00000000";
elsif rising_edge(temp(3)) then
counter <= counter + 1 ;
end if;
end process;
dac_out <=counter;
end Behavioral;

--SINE WAVEFORM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sine is
Port ( clk,rst : in STD_LOGIC;
d : out STD_LOGIC_VECTOR (07 downto 0));
end sine;
architecture Behavioral of sine is
signal c:std_logic_vector(7 downto 0);
signal i: integer range 0 to 707;
type sine is array (0 to 719) of integer range 0 to 255;
constant value : Sine := (128,132,136,141,145,150,154,158,163,167,171,175,
180,184,188,192,195,199,203,206,210,213,216,220,223,226,228,231,234,236,
238,241,243,244,246,247,248,249,250,251,252,253,254,255,255,255,255,255,
254,253,252,251,249,246,244,243,241,236,234,231,228,226,223,220,216,230,
210,206,203,199,195,192,188,184,180,175,171,167,163,158,154,150,145,141,
136,132,128,123,119,114,110,105,101,97,92,88,84,80,75,71,67,64,60,56,52,
49,45,42,39,35,32,29,27,24,21,19,17,14,12,11,9,7,6,4,3,2,1,0,0,0,0,0,0,1,
1,2,3,4,6,7,9,11,12,14,17,19,21,14,17,19,21,24,27,29,32,35,39,42,45,49,52,
56,60,64,67,71,75,80,84,88,92,97,101,105,110,114,119,123,128,128,128,132,
136,141,145,150,154,158,163,167,171,175,180,184,188,192,195,199,203,206,
210,213,216,220,223,226,228,231,234,236,238,241,243,244,246,247,248,249,
250,251,252,253,254,255,255,255,255,255,254,253,252,251,249,246,244,243,
241,236,234,231,228,226,223,220,216,230,210,206,203,199,195,192,188,184,
180,175,171,167,163,158,154,150,145,141,136,132,128,123,119,114,110,105,
101,97,92,88,84,80,75,71,67,64,60,56,52,49,45,42,39,35,32,29,27,24,21,19,
17,14,12,11,9,7,6,4,3,2,1,0,0,0,0,0,0,1,1,2,3,4,6,7,9,11,12,14,17,19,21,
14,17,19,21,24,27,29,32,35,39,42,45,49,52,56,60,64,67,71,75,80,84,88,92,
97,101,105,110,114,119,123,128,128,128,132,136,141,145,150,154,158,163,
167,171,175,180,184,188,192,195,199,203,206,210,213,216,220,223,226,228,

231,234,236,238,241,243,244,246,247,248,249,250,251,252,253,254,255,255,
255,255,255,254,253,252,251,249,246,244,243,241,236,234,231,228,226,223,
220,216,230,210,206,203,199,195,192,188,184,180,175,171,167,163,158,154,
150,145,141,136,132,128,123,119,114,110,105,101,97,92,88,84,80,75,71,67,
64,60,56,52,49,45,42,39,35,32,29,27,24,21,19,17,14,12,11,9,7,6,4,3,2,1,0,
0,0,0,0,0,1,1,2,3,4,6,7,9,11,12,14,17,19,21,14,17,19,21,24,27,29,32,35,39,
42,45,49,52,56,60,64,67,71,75,80,84,88,92,97,101,105,110,114,119,123,128,
128,128,132,136,141,145,150,154,158,163,167,171,175,180,184,188,192,195,
199,203,206,210,213,216,220,223,226,228,231,234,236,238,241,243,244,246,
247,248,249,250,251,252,253,254,255,255,255,255,255,254,253,252,251,249,
246,244,243,241,236,234,231,228,226,223,220,216,230,210,206,203,199,195,
192,188,184,180,175,171,167,163,158,154,150,145,141,136,132,128,123,119,
114,110,105,101,97,92,88,84,80,75,71,67,64,60,56,52,49,45,42,39,35,32,29,
27,24,21,19,17,14,12,11,9,7,6,4,3,2,1,0,0,0,0,0,0,1,1,2,3,4,6,7,9,11,12,
14,17,19,21,14,17,19,21,24,27,29,32,35,39,42,45,49,52,56,60,64,67,71,75,
80,84,88,92,97,101,105,110,114,119,123,128,128);
begin
process(clk,rst)
begin
if (rst='1') then
c<=(others=>'0');
elsif (clk' event and clk='1') then
c<= c + 1;
end if;
end process;
process(c(3))
begin
if(c(3)'event and c(3)='1') then
d<= conv_std_logic_vector(value(i),8);
i<=i+1;
if (i=719) then
i<=0;
end if;
end if;
end process;
end Behavioral;

--Relay type
entity extlight is
Port ( cntrl1,cntrl2 : in std_logic;
light : out std_logic);
end extlight;
architecture Behavioral of extlight is
begin
light<= cntrl1 XOR cntrl2 ;
end Behavioral;
CLOCK DIVIDER COUNTER INTERFACING PROGRAM-BINARY
entity up_counter_interface is
Port ( rst : in STD_LOGIC;
clk : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (3 downto 0));
end up_counter_interface;
architecture Behavioral of up_counter_interface is
signal count: std_logic_vector(3 downto 0);
signal clk1: std_logic;
signal clk2: std_logic_vector(22 downto 0):=(others=>'0');
begin
entity up_counter_interface is
Port ( rst : in STD_LOGIC;
process(clk,clk2)
begin
if rising_edge(clk)then
clk2<=clk2+'1';
end if;
end process;
clk1<=clk2(20);

process(clk1,rst)
begin
if (rst='0')then
count<="0000";
elsif rising_edge(clk1)then
count<=count+1;
end if;
y<=count;
end process;
--end up_counter_interface;

end Behavioral;

CLOCK DIVIDER COUNTER INTERFACING PROGRAM-Bcd

entity qwq is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (3 downto 0));
end qwq;
architecture Behavioral of qwq is
signal count: std_logic_vector(3 downto 0);
signal clk1: std_logic;
signal clk2: std_logic_vector(22 downto 0):=(others=>'0');
begin
process(clk,clk2)
begin
if rising_edge(clk)then
clk2<=clk2+'1';
end if;
end process;
clk1<=clk2(20);
process(clk1,rst)
begin
if (rst='1')then
count<="0000";
elsif rising_edge(clk1)then
if(count="1001")then
count<="0000";
else
count<=count+1;
end if;
y<=count;
end if;
end process;
--end up_counter_interface;

end Behavioral;

CLOCK DIVIDER COUNTER INTERFACING PROGRAM-random sequence

entity rndm_evn is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (2 downto 0));
end rndm_evn;
architecture Behavioral of rndm_evn is
--signal count: std_logic_vector(3 downto 0);
signal clk1: std_logic;
signal clk2: std_logic_vector(25 downto 0):=(others=>'0');
begin
process(clk,clk2)
begin

if rising_edge(clk)then
clk2<=clk2+'1';
end if;
end process;
clk1<=clk2(21);
process(clk1,reset)
variable prs:std_logic_vector(2 downto 0);
variable nes:std_logic_vector(2 downto 0);
begin
if rising_edge(clk1)then
if (reset='0')then
prs:="000";
else
case prs is
when "000"=>nes:="010";
when "010"=>nes:="110";
when "110"=>nes:="001";
when "001"=>nes:="011";
when "011"=>nes:="101";
when "101"=>nes:="111";
when others=>nes:="000";
end case;
y<=prs;
prs:=nes;
end if;
end if;
end process;
end Behavioral;