PD - 96123

IRLR8743PbF
IRLU8743PbF
Applications HEXFET® Power MOSFET
l High Frequency Synchronous Buck
Converters for Computer Processor Power
VDSS RDS(on) max Qg
l High Frequency Isolated DC-DC 30V 3.1m: 39nC
Converters with Synchronous Rectification
for Telecom and Industrial Use D
l Lead-Free

Benefits
S S
l Very Low RDS(on) at 4.5V VGS G
D
G
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage D-Pak I-Pak
IRLR8743PbF IRLU8743PbF
and Current
G D S
Gate Drain Source
Absolute Maximum Ratings
Parameter Max. Units
VDS Drain-to-Source Voltage 30 V
VGS Gate-to-Source Voltage ± 20
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 160 f
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 113 f A
IDM Pulsed Drain Current c 640
PD @TC = 25°C Maximum Power Dissipation g 135 W
PD @TC = 100°C Maximum Power Dissipation g 68
Linear Derating Factor 0.90 W/°C
TJ Operating Junction and -55 to + 175 °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case)

Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.11
RθJA Junction-to-Ambient (PCB Mount) g ––– 50 °C/W
RθJA Junction-to-Ambient ––– 110

Notes  through … are on page 11

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IRLR/U8743PbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
BVDSS Drain-to-Source Breakdown Voltage 30 ––– ––– V VGS = 0V, ID = 250µA
∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 20 ––– mV/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 2.4 3.1 VGS = 10V, ID = 25A e
––– 3.0 3.9
mΩ
VGS = 4.5V, ID = 20A e
VGS(th) Gate Threshold Voltage 1.35 1.9 2.35 V VDS = VGS, ID = 100µA
∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -6.4 ––– mV/°C
IDSS Drain-to-Source Leakage Current ––– ––– 1.0 VDS = 24V, VGS = 0V
µA
––– ––– 150 VDS = 24V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 VGS = 20V
nA
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
gfs Forward Transconductance 89 ––– ––– S VDS = 15V, ID = 20A
Qg Total Gate Charge ––– 39 59
Qgs1 Pre-Vth Gate-to-Source Charge ––– 10 ––– VDS = 15V
Qgs2 Post-Vth Gate-to-Source Charge ––– 3.9 ––– nC VGS = 4.5V
Qgd Gate-to-Drain Charge ––– 13 ––– ID = 20A
Qgodr Gate Charge Overdrive ––– 12 ––– See Fig. 16
Qsw Switch Charge (Qgs2 + Qgd) ––– 17 –––
Qoss Output Charge ––– 21 ––– nC VDS = 16V, VGS = 0V
RG Gate Resistance ––– 0.85 1.5 Ω
td(on) Turn-On Delay Time ––– 19 ––– VDD = 15V, VGS = 4.5V e
tr Rise Time ––– 35 ––– ID = 20A
ns
td(off) Turn-Off Delay Time ––– 21 ––– RG = 1.8Ω
tf Fall Time ––– 17 ––– See Fig. 14
Ciss Input Capacitance ––– 4880 ––– VGS = 0V
Coss Output Capacitance ––– 950 ––– pF VDS = 15V
Crss Reverse Transfer Capacitance ––– 470 ––– ƒ = 1.0MHz

Avalanche Characteristics
Parameter Typ. Max. Units
EAS Single Pulse Avalanche Energy d ––– 250 mJ
IAR Avalanche Current c ––– 20 A
EAR Repetitive Avalanche Energy c ––– 13.5 mJ

Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current
(Body Diode)
––– –––
160 f MOSFET symbol
showing the
A
ISM Pulsed Source Current ––– ––– integral reverse
(Body Diode)c 640
p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.0 V TJ = 25°C, IS = 20A, VGS = 0V e
trr Reverse Recovery Time ––– 18 27 ns TJ = 25°C, IF = 20A, VDD = 15V
Qrr Reverse Recovery Charge ––– 32 48 nC di/dt = 300A/µs e
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

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 IRLR/U8743PbF

1000 1000
VGS VGS
TOP 10V TOP 10V
4.5V 4.5V
3.7V 3.7V

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

3.5V 3.5V
100 3.3V 3.3V
3.0V 3.0V
2.7V 100 2.7V
BOTTOM 2.5V BOTTOM 2.5V

10

10
1 2.5V
2.5V
≤60µs PULSE WIDTH ≤60µs PULSE WIDTH
Tj = 25°C Tj = 175°C
0.1 1
0.1 1 10 100 0.1 1 10 100
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 2.0
RDS(on) , Drain-to-Source On Resistance

ID = 25A
VGS = 10V
ID, Drain-to-Source Current (A)

100
1.5
(Normalized)

10 T J = 175°C

1.0
T J = 25°C
1

VDS = 15V
≤60µs PULSE WIDTH
0.1 0.5
0 2 4 6 8 -60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

vs. Temperature
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 IRLR/U8743PbF

100000 5.0
VGS = 0V, f = 1 MHZ ID= 20A
C iss = C gs + C gd, C ds SHORTED VDS= 24V
VDS= 15V

VGS, Gate-to-Source Voltage (V)

C rss = C gd
4.0
C oss = C ds + C gd
C, Capacitance (pF)

10000
3.0
Ciss

2.0
Coss
1000
Crss
1.0

100 0.0
1 10 100 0 5 10 15 20 25 30 35 40 45 50

VDS, Drain-to-Source Voltage (V) QG, Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Fig 6. Typical Gate Charge vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000 10000
OPERATION IN THIS AREA
LIMITED BY R DS(on)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)

T J = 175°C 1000
100
100µsec

T J = 25°C 100 1msec

10 10msec

10

1
1
Tc = 25°C
Tj = 175°C
VGS = 0V Single Pulse
0.1 0.1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 1 10 100
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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 IRLR/U8743PbF

180 2.5

160 Limited By Package

VGS(th) , Gate Threshold Voltage (V)

140
2.0
ID, Drain Current (A)

120

100 ID = 100µA
1.5
80

60
1.0
40

20

0 0.5
25 50 75 100 125 150 175 -75 -50 -25 0 25 50 75 100 125 150 175 200
T C , Case Temperature (°C) T J , Temperature ( °C )

Fig 9. Maximum Drain Current vs. Fig 10. Threshold Voltage vs. Temperature
Case Temperature

10
Thermal Response ( Z thJC ) °C/W

1
D = 0.50

0.20
0.1 0.10 Ri (°C/W) τi (sec)
R1 R2 R3 R4
R1 R2 R3 R4
0.05 τJ
0.02879 0.000017
τC
τJ τ
0.02 τ1
0.25773 0.000143
τ2 τ3 τ4
τ1 τ2 τ3 τ4
0.01 0.48255 0.001411
0.01 Ci= τi/Ri
Ci i/Ri 0.34135 0.010617
Notes:
SINGLE PULSE 1. Duty Factor D = t1/t2
( THERMAL RESPONSE ) 2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRLR/U8743PbF
15V 1200

EAS , Single Pulse Avalanche Energy (mJ)

ID

1000 TOP 2.7A

L DRIVER
VDS 3.7A
BOTTOM 20A
800
RG D.U.T +
V
- DD
IAS A
20V
VGS 600
tp 0.01Ω

Fig 12a. Unclamped Inductive Test Circuit 400

200
V(BR)DSS
tp
0
25 50 75 100 125 150 175
Starting T J , Junction Temperature (°C)

Fig 12c. Maximum Avalanche Energy

Vs. Drain Current
I AS
RD
Fig 12b. Unclamped Inductive Waveforms V DS

V GS
D.U.T.
RG
+
-V DD
Current Regulator
Same Type as D.U.T. VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
50KΩ

12V .2µF
.3µF Fig 14a. Switching Time Test Circuit
+
V
D.U.T. - DS VDS
90%
VGS

3mA

IG ID 10%
Current Sampling Resistors
VGS
td(on) tr t d(off) tf

Fig 13. Gate Charge Test Circuit

Fig 14b. Switching Time Waveforms

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 IRLR/U8743PbF

Driver Gate Drive

P.W.
D.U.T P.W.
Period D=
Period
+

ƒ VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance
D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG V DD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

Id
Vds

Vgs

Vgs(th)

Qgodr Qgd Qgs2 Qgs1

Fig 16. Gate Charge Waveform

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IRLR/U8743PbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
Ploss = (Irms 2 × Rds(on ) )
⎛ Qgd ⎞ ⎛ Qgs 2
+⎜I × × Vin × f⎟ + ⎜ I × × Vin × f ⎟
⎝ ig ⎠ ⎝ ig
+ (Qg × Vg × f )
⎛ Qoss
+ × Vin × f ⎞
⎝ 2 ⎠ are transfered to Q1 and increase the dissipation in
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Q gs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
8 www.irf.com
Synchronous FET
The power loss equation for Q2 is approximated
by;
Ploss = Pconduction + Pdrive + Poutput
*
( 2
Ploss = Irms × Rds(on) )
+ (Qg × Vg × f )
⎛Q ⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2 ⎠
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an im-
⎞ portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
⎠ it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
 IRLR/U8743PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)

D-Pak (TO-252AA) Part Marking Information

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www.irf.com 9
IRLR/U8743PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)

I-Pak (TO-251AA) Part Marking Information

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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
10 www.irf.com
 IRLR/U8743PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR TRR TRL

16.3 ( .641 ) 16.3 ( .641 )

15.7 ( .619 ) 15.7 ( .619 )

12.1 ( .476 ) 8.1 ( .318 )

FEED DIRECTION FEED DIRECTION
11.9 ( .469 ) 7.9 ( .312 )

NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

13 INCH

16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.

Note:
Notes:For the most current drawing please refer to IR website at http://www.irf.com/package/

 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 1.252mH, RG = 25Ω,
IAS = 20A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 50A.
… When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to
application note #AN-994.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.08/2007
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IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”) .
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
For further information on the product, technology,
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contact your nearest Infineon Technologies office
(www.infineon.com).
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