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IRF9520

Data Sheet July 1999 File Number 2281.3

6A, 100V, 0.600 Ohm, P-Channel Power Features


MOSFET • 6A, 100V
This advanced power MOSFET is designed, tested, and
• rDS(ON) = 0.600Ω
guaranteed to withstand a specified level of energy in the
breakdown avalanche mode of operation. These are • Single Pulse Avalanche Energy Rated
P-Channel enhancement mode silicon gate power field • SOA is Power Dissipation Limited
effect transistors designed for applications such as switching
regulators, switching converters, motor drivers, relay drivers • Nanosecond Switching Speeds
and drivers for high power bipolar switching transistors • Linear Transfer Characteristics
requiring high speed and low gate drive power. These types
• High Input Impedance
can be operated directly from integrated circuits.

Formerly developmental type TA17501. Symbol


D
Ordering Information
PART NUMBER PACKAGE BRAND

IRF9520 TO-220AB IRF9520 G

NOTE: When ordering, use the entire part number.


S

Packaging
JEDEC TO-220AB

SOURCE
DRAIN
GATE

DRAIN (FLANGE)

4-3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
IRF9520

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified


IRF9520 UNITS
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS -100 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR -100 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID -6 A
TC =100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID -4 A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM -24 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD 40 W
Linear Derating Factor (Figure 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.32 W/oC
Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS 370 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL 300 oC
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 260 oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. TJ = 25oC to TJ = 125oC.

Electrical Specifications TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS


Drain to Source Breakdown Voltage BVDSS ID = -250µA, VGS = 0V (Figure 10) -100 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = -250µA -2 - -4 V
Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - -25 µA
VDS = 0.8 x Rated BVDSS, VGS = 0V - - -250 µA
TC = 125oC
On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON) MAX, VGS = -10V -6 - - A
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
Drain to Source On Resistance (Note 2) rDS(ON) ID = -3.5A, VGS = -10V (Figures 8, 9) - 0.500 0.600 Ω
Forward Transconductance (Note 2) gfs VDS > ID(ON) x rDS(ON)MAX, ID = -3.5A 0.9 2 - S
( Figure 12)
Turn-On Delay Time td(ON) VDD = 0.5 x Rated BVDSS, ID ≈ -6.0A, - 25 50 ns
RG = 50Ω , RL = 7.7Ω for VDSS = 50Ω
Rise Time tr - 50 100 ns
MOSFET Switching Times are Essentially
Turn-Off Delay Time td(OFF) Independent of Operating Temperature - 50 100 ns
Fall Time tf - 50 100 ns
Total Gate Charge Qg(TOT) VGS = -10V, ID = -6A, VDS = 0.8 x Rated BVDSS - 16 22 nC
(Gate to Source + Gate to Drain) (Figure 14) Gate Charge is Essentially
Gate to Source Charge Qgs Independent of Operating Temperature - 9 - nC
Gate to Drain “Miller” Charge Qgd - 7 - nC
Input Capacitance CISS VDS = -25V, VGS = 0V, f = 1MHz - 300 - pF
(Figure 11)
Output Capacitance COSS - 200 - pF
Reverse Transfer Capacitance CRSS - 50 - pF
Internal Drain Inductance LD Measured From the Modified MOSFET - 3.5 - nH
Contact Screw on Tab To Symbol Showing the
Center of Die Internal Devices
Measured From the Drain Inductances - 4.5 - nH
D
Lead, 6mm (0.25in) from
Package to Center of Die LD
Internal Source Inductance LS Measured From the - 7.5 - nH
Source Lead, 6mm G
(0.25in) From Header to LS
Source Bonding Pad
S

Thermal Resistance Junction-to-Case RθJC - - 3.12 oC/W

Thermal Resistance Junction-to-Ambient RθJA Typical Socket Mount - - 62.5 oC/W

4-4
IRF9520

Source to Drain Diode Specifications


PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current ISD Modified MOSFET Sym- - - -6.0 A
bol Showing the Integral D
Pulse Source to Drain Current ISDM - - -24 A
Reverse P-N Junction
(Note 3)
Diode
G

Source to Drain Diode Voltage VSD TC = 25oC, ISD = -6.0A, VGS = 0V - - -1.5 V
(Note 2) (Figure 13)
Reverse Recovery Time trr TJ = 150oC, ISD = -6.0A, dISD/dt = 100A/µs - 230 - ns
Reverse Recovery Charge QRR TJ = 150oC, ISD = -6.0A, dISD/dt = 100A/µs - 1.3 - µC
NOTES:
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 25V, starting TJ = 25oC, L = 15.4mH, RG = 25Ω, peak IAS = 6.0A.

Typical Performance Curves Unless Otherwise Specified

1.2 6.0
POWER DISSIPATION MULTIPLIER

1.0
4.8
ID, DRAIN CURRENT (A)

0.8
3.6

0.6
2.4
0.4

1.2
0.2

0.0 0
0 25 50 75 100 125 150 25 50 75 100 125 150
TA , CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE

1
ZθJC, NORMALIZED TRANSIENT
THERMAL IMPEDANCE

0.5

0.2 PDM

0.1
0.1
0.05 t1
t2
0.02
0.01 NOTES:
SINGLE PULSE DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
10-5 10-4 10-3 10-2 10-1 1 10
t 1, RECTANGULAR PULSE DURATION (s)

FIGURE 3. NORMALIZED TRANSIENT THERMAL IMPEDANCE

4-5
IRF9520

Typical Performance Curves Unless Otherwise Specified (Continued)

-10
VGS = -10V VGS = -9V
10µs
-8 VGS = -8V

ID, DRAIN CURRENT (A)


10 100µs
ID, DRAIN CURRENT (A)

-6
1ms VGS = -7V

PULSE DURATION = 80µs


OPERATION IN THIS AREA -4 DUTY CYCLE = 0.5% MAX.
1 10ms
IS LIMITED BY rDS(ON) VGS = -6V
100ms
DC -2
VGS = -5V
TC = 25oC VGS = -4V
TJ = MAX RATED
0.1 0
1 10 100 0 -10 -20 -30 -40 -50
VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

-5 -10
VDS ≥ I D(ON) x rDS(ON) MAX
VGS = -7V ID(ON), ON-STATE DRAIN CURRENT (A) PULSE DURATION = 80µs
VGS = -8V
-4 -8 DUTY CYCLE = 0.5% MAX.
ID, DRAIN CURRENT (A)

VGS = -9V TJ = 125oC


VGS = -10V TJ = 25oC
-3 VGS = -6V -6
TJ = -55oC

PULSE DURATION = 80µs


-2 -4
DUTY CYCLE = 0.5% MAX.
VGS = -5V
-1 -2
VGS = -4V
0 0
0 -1 -2 -3 -4 -5 0 -2 -4 -6 -8 -10
VDS, DRAIN TO SOURCE VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V)

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

2.0 2.2
PULSE DURATION = 80µs VGS = -10V, ID = -4A
DUTY CYCLE = 0.5% MAX.
NORMALIZED DRAIN TO SOURCE

PULSE DURATION = 80µs


1.8 DUTY CYCLE = 0.5% MAX.
rDS(ON), DRAIN TO SOURCE

1.6
ON RESISTANCE (Ω)

ON RESISTANCE

1.2 1.4
VGS = -10V

0.8 1.0

0.4 0.6
VGS = -20V

0 0.2
0 -5 -10 -15 -20 -25 -40 0 40 80 120
ID, DRAIN CURRENT (A) TJ , JUNCTION TEMPERATURE (oC)

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE FIGURE 9. NORMALIZED DRAIN TO SOURCE ON


VOLTAGE AND DRAIN CURRENT RESISTANCE vs JUNCTION TEMPERATURE

4-6
IRF9520

Typical Performance Curves Unless Otherwise Specified (Continued)

1.25 500
ID = 250µA VGS = 0V, f = 1MHz
CISS = CGS + CGD
NORMALIZED DRAIN TO SOURCE

400 CRSS = CGD


1.15
COSS ≈ CDS + CGD
BREAKDOWN VOLTAGE

C, CAPACITANCE (pF)
CISS
1.05 300

COSS
0.95 200

0.85 100 CRSS

0.75 0
-40 0 40 80 120 160 0 -10 -20 -30 -40 -50
TJ , JUNCTION TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VOLTAGE vs JUNCTION TEMPERATURE

3 -100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
gfs, TRANSCONDUCTANCE (S)

ISD, DRAIN CURRENT (A)

2 -10
TJ = 150oC

TJ = -55oC
TJ = 25oC
TJ = 25oC
1 TJ = 125oC -1.0

0 -0.1
0 -2 -4 -6 -8 -10 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8
ID , DRAIN CURRENT (A) VSD, SOURCE TO DRAIN VOLTAGE (V)

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

0
ID = -6A
VGS, GATE TO SOURCE (V)

-5

VDS = -80V

-10 VDS = -50V


VDS = -20V

0 4 8 12 16 20
Qg(TOT) , TOTAL GATE CHARGE (nC)

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

4-7
IRF9520

Test Circuits and Waveforms

VDS
tAV

L 0

VARY tP TO OBTAIN
RG
-
REQUIRED PEAK IAS
VDD
+

0V DUT VDD
tP IAS
VGS
VDS
IAS tP
0.01Ω
BVDSS

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

tON tOFF

td(ON) td(OFF)

tr tf
0
RL 10% 10%

DUT - VDS
VDD 90% 90%
RG
VGS + VGS
0
10%

50% 50%
PULSE WIDTH
90%

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
-VDS
CURRENT (ISOLATED
REGULATOR SUPPLY)
0

VDS
DUT
12V
0.2µF 50kΩ
BATTERY
0.3µF

Qgs VGS
D Qgd

Qg(TOT)
G DUT
VDD
0
IG(REF) S
0
+VDS
IG CURRENT ID CURRENT
SAMPLING SAMPLING
RESISTOR RESISTOR IG(REF)

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

4-8
IRF9520

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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