D/A Converters Continued:: - Component Matching - Systematic & Random Errors

EE247
Lecture 14
• D/A converters continued:
– Resistor string DACs (continued)
– Serial charge redistribution DACs
– Charge scaling DACs
– R-2R type DACs
– Current based DACs
– Static performance of D/As
• Component matching
• Systematic & random errors
– Practical aspects of current-switched DACs
– Segmented current-switched DACs
EECS 247- Lecture 14 Data Converters: DAC Design © 2008 H.K. Page 1
R-String DAC
• Advantages:
– Takes full advantage of availability Vref
of almost perfect switches in MOS
technologies
– Simple, fast for <8-10bits
– Inherently monotonic
– Compatible with purely digital
technologies
• Disadvantages:
– 2B resistors & ~2x2B switches for B C
bits Æ High element count & large
area for B >10bits
– High settling time for high resolution
DACs:
τmax ~ 0.25 x 2B RC
Ref:
M. Pelgrom, “A 10-b 50-MHz CMOS D/A Converter with 75-W Buffer,” JSSC, Dec. 1990, pp. 1347
R-String DAC
Including Interpolation
Resistor string DAC + Resistor string

Vref
interpolator increases resolution w/o drastic
increase in complexity
e.g. 10bit DACÆ (5bit +5bitÆ 2x25=26 # of
Rs) instead of direct 10bitÆ210
Vout
Considerations:
Main R-string loaded by the interpolation
string resistors
Large R values for interpolating stringÆ

less loading but lower speed
Can use buffers
R-String DAC
Including Interpolation
Vref
Use buffers to prevent
loading of the main
ladder
Issues:
Æ Buffer DC offset
Æ Effect of buffer
bandwidth
limitations on
overall speed
Charge Based: Serial Charge Redistribution DAC
Simplified Operation
Nominally C1=C2
• Operation based on redistribution of charge associated with C1 &

C2 to perform accurate division by factor of 2
Charge Based: Serial Charge Redistribution DAC

Simplified Operation: Conversion Sequence
T1 T2
QCT11 = VREF × C1 & QCT11 = 0 QCT11 + QCT12 = QCT 2 + QCT 2 = (C1 + C2 )Vo
1 2
→ QCT11 + QCT12 = VREF × C1 VREF × C1 = ( C1 + C2 )Vo
C1
Vo = VREF ×
C1 + C2
VREF
S i nce C1 = C2 → Vo =
2
Serial Charge Redistribution DAC
Simplified Operation (Cont’d)
T1 T2
• Conversion sequence:
– Next cycle
• If S3 closed VC1=0 then when S1 closes VC1 = VC2 = VREF/4
• If S2 closed VC1=VREF then when S1 closes VC1 =VC2 =VREF/2+VREF/4

• Conversion sequence:
– Discharge C1 & C2Æ S3& S4
closed
– For each bit in succession
beginning with LSB, b1:
• S1 open- if bi=1 C1
precharge to VREF if bi=0
discharged to GND
• S2 & S3 & S4 open- S1
closed- Charge sharing
C1 & C2
Æ ½ of precharge on
C1 +½ of charge
previously stored on
C2Æ C2
Example: Input Code 101
LSB
MSB
b3 b2 b1
• Example input code 101Æ output (4/8 +0/8 +1/8 )VREF =5/8 VREF
• Very small area
• For an N-bit DAC, N redistribution cycles for one full analog output
generation Æ quite slow
Parallel Charge Scaling DAC

• DAC operation based on capacitive voltage division
Vout
Cy Cx C Cx
Vout = Vref
Cx + Cy + C
Vref
Æ Make Cx & Cy function of incoming DAC digital word
Parallel Charge Scaling DAC
reset
Vout
2(B-1) C 8C 4C 2C C C
bB-1 (msb) b3 b2 b1 b0 (lsb)
Vref
B −1
• E.g. “Binary weighted” ∑ bi 2 i C
Vout = i =0 Vref
• B+1 capacitors & switches 2B C
(Cs built of unit elements
Æ 2B units of C)
Charge Scaling DAC

Example: 4Bit DAC- Input Code 1011
1- Reset phase 2- Charge phase
reset Vout
Vout
8C 4C 2C C C 8C 4C 2C C C
b3 b2
b3 b2 b1 b1 b0 (lsb)
b0 (lsb)
Vref Vref
20 C + 21 C + 23C 11
Vout = Vref = Vref
24 C 16
Charge Scaling DAC
reset CP
Vout
2(B-1) C 8C 4C 2C C C B −1

∑b 2 C i
i
Vout = i =0
Vref
2 B C + CP
Vref
• Sensitive to parasitic capacitor @ output

– If Cp constant Æ gain error
– If Cp voltage dependant Æ DAC nonlinearity
• Large area of caps for high DAC resolution (10bit DAC ratio
1:512)
• Monotonicity depends on element matching (more later)
Parasitic Insensitive
Charge Scaling DAC
CI
reset CP
-
2(B-1) C 8C 4C 2C C
+ Vout
Vref
B −1 i B −1 i
∑ bi 2 C ∑ bi 2
Vout = − i = 0 Vref , B
CI = 2 C → Vo ut = − i = 0 Vref
CI 2B
• Opamp helps eliminate the parasitic capacitor effect by producing virtual

ground at the sensitive node since CP has zero volts at start & end
– Issue: opamp offset & speed
Charge Scaling DAC
Incorporating Offset Compensation
CI S2
reset
reset CP S1
-
S3 Vos
2(B-1) C 8C 4C 2C C reset Vout
+
Vref
• During reset phase:
– Opamp disconnected from capacitor array via switch S3
– Opamp connected in unity-gain configuration (S1)
– CI Bottom plate connected to ground (S2)
– Vout ~ - Vos Æ VCI = -Vos
• This effectively compensates for offset during normal phase
Charge Scaling DAC

Utilizing Split Array
reset 8/7C
+
C C 2C 4C C 2C 4C
- Vout
b0 b1 b2 b3 b4 b5
Vref
∑ all LSB arra y C
Cse rie s = C
∑ a ll MS B a rr ay C
• Split arrayÆ reduce the total area of the capacitors required for high
resolution DACs
– E.g. 10bit regular binary array requires 1024 unit Cs while split array
(5&5) needs 64 unit Cs
– Issue: Sensitive to parasitic capacitor
Charge Scaling DAC
• Advantages:
– Low power dissipation Æ capacitor array does not dissipate DC power
– Output is sample and held Æ no need for additional S/H
– INL function of capacitor ratio
– Possible to trim or calibrate for improved INL
– Offset cancellation almost for free
• Disadvantages:
– Process needs to include good capacitive material Æ not
compatible with standard digital process
– Requires large capacitor ratios
– Not inherently monotonic (more later)
Segmented DAC
Resistor Ladder (MSB) & Binary Weighted Charge Scaling (LSB)
• Example: 12bit
DAC
– 6-bit MSB DACÆ
R- string reset
– 6-bit LSB DAC Æ Vout
binary weighted 32 C 16C 8C 4C 2C C C
charge scaling ...
... b1 b0
• Complexity much ... b5 b4 b3 b2
lower compared to .
full R-string
– Full R stringÆ
6-bit
4096 resistors
binary weighted
– Segmented Æ 64 charge redistribution DAC
R + 7 Cs (64 unit 6bit
caps) resistor
ladder Switch
Network
Current Based DACs
R-2R Ladder Type
• R-2R DAC basics:
R V/2
– Simple R network I/2
I I/2
divides both voltage V
& current by 2 2R 2R
Increase # of bits by replicating circuit

R-2R Ladder DAC
Iout
VB
2R 2R 2R 2R 2R 2R
R R R R
VEE
Emitter-follower added to convert to high output impedance current

sources
R-2R Ladder DAC
How Does it Work?
Consider a simple 3bit R-2R DAC:
Iout
VB 4xAunit 2xAunit 1xAunit 1xAunit
2R 2R 2R 2R
R R
VEE
R-2R Ladder DAC

How Does it Work?
Simple 3bit DAC:
1- Consolidate first two stages:
I3 I2 I1 IT I3 I2 I1+IT
VB Q3 Q2 Q1 QT VB Q3 Q2
4Aunit 2Aunit Aunit Aunit 4Aunit 2Aunit 2Aunit
2R 2R 2R 2R 2R 2R R
R R R R
VEE VEE
R-2R Ladder DAC
How Does it Work?
Simple 3bit DAC-
2- Consolidate next two stages:
I1+IT I2+I1+IT
I3 I2 I3
VB Q3 Q2 VB Q3 Q2
4Aunit 2Aunit 2Aunit 4Aunit 4Aunit
2R 2R R 2R R
R R R
VEE VEE
I I I
I3 = I2 + I1 + IT → I3 = T ot al , I2 = T ot a l , I1 = To t al
2 4 8
R-2R Ladder DAC

How Does it Work?
Consider a simple 3bit R-2R DAC:
Iout
VB 4Aunit 2Aunit Aunit

Aunit
4I 2R 2I 2R I 2R I 2R
R R
VEE
4I 2I
In most cases need to convert output current to voltage

Ref: B. Razavi, “Data Conversion System Design”, IEEE Press, 1995, page 84-87
R-2R Ladder DAC
RTotal
R
-
+ Vout
VB
16I 2R 8I 2R 4I 2R 2I 2R I 2R I 2R
R R R R
VEE
16I 8I 4I 2I
Trans-resistance amplifier added to:
- Convert current to voltage
- Generate virtual ground @ current summing node so that output
impedance of current sources do not cause error
- Issue: error due to opamp offset
R-2R Ladder DAC

Opamp Offset Issue
out = V in ⎛ 1 +
Vos
R ⎞ R
os ⎜ ⎟
⎝ R T ot al ⎠
RTotal
If R T ota l = l a r g e, -
out
→ Vos in
≈ Vos Vos
+ Vout
If RT ota l = n o t l a rg e
out in ⎛ 1 + R ⎞ Offset
→ Vos = Vos ⎜ RT ot al ⎟
⎝ ⎠ Model
P r ob l em :
S i nce RT ota l i s co d e d ep en d an t
ou t
→ Vos w ou l d b e co de d ep en da n t
→ G i ves r i s e t o I N L & DN L
R-2R Ladder
Summary
• Advantages:
– Resistor ratios only x2
– Does not require precision capacitors
• Disadvantages:
– Total device emitter area Æ AEunitx 2B
Æ Not practical for high resolution DACs
– INL/DNL error due to amplifier offset
Current based DAC

Unit Element Current Source DAC
……………
Iout
Iref Iref Iref Iref Iref

……………
• “Unit elements” or thermometer

• 2B-1 current sources & switches
• Suited for both MOS and BJT technologies
• Monotonicity does not depend on element matching and is guaranteed
• Output resistance of current source Æ gain error
– Cascode type current sources higher output resistance Æ less gain
error
Current Source DAC
Unit Element R
…………… -
Vout
+
Iref Iref Iref Iref

……………
• Output resistance of current source Æ gain error problem

Æ Use transresistance amplifier
- Current source output held @ virtual ground
- Error due to current source output resistance eliminated
- New issues: offset & speed of the amplifier
Current Source DAC

Binary Weighted
……………
Iout
2B-1 Iref 4 Iref 2Iref Iref

……………
• “Binary weighted”
• B current sources & switches (2B-1 unit current sources but less
# of switches)
• Monotonicity depends on element matching Ænot guaranteed
Static DAC Errors -INL / DNL
Static DAC errors mainly due to component mismatch
– Systematic errors
• Contact resistance
• Edge effects in capacitor arrays
• Process gradients
• Finite current source output resistance
– Random variations
• Lithography etc…
• Often Gaussian distribution (central limit theorem)
*Ref: C. Conroy et al, “Statistical Design Techniques for D/A Converters,” JSSC
Aug. 1989, pp. 1118-28.
Current Source DAC

DNL/INL Due to Element Mismatch
-
Vout
+
Iref Iref Iref Iref Iref
Iref -ΔI Iref +ΔI
• Simplified example:
– 3-bit DAC
– Assume only two of the current sources mismatched (# 4 & #5)
Current Source DAC
DNL/INL Due to Element Mismatch
seg men t[ m] − V [ L S B ] Analog

DN L[ m] = Output
V [ LSB] 7 Iref R
seg men t[ 4 ] − V [ L S B ] 6
DN L[ 4 ] =
V [ LSB]
5
( I − Δ I )R − IR
= 4
IR
DN L[ 4 ] = −Δ I / I [ LSB ] 3
( I + Δ I )R − IR 2
DN L[ 5] =
IR
1xIref R
DN L[ 5 ] = Δ I / I [ L S B ] Digital
Input
→ IN Lmax = −Δ I / I [ L S B ] 0
000 001 010 011 100 101 110 111
Component Mismatch
Probability Distribution Function
• Component parameters Æ Random variables
• Each component is the product of many fabrication steps

• Most fabrication steps includes random variations
ÆOverall component variations product of several random variables
ÆAssuming each of these variables have a uniform pdf distribution:

ÆJoint pdf of a random variable affected by two uniformly
distributed variables Æ convolution of the two uniform pdfs…….
pdf [f(x1)] pdf [f(x2)] pdf [f(x1,x2)]
* Æ
pdf [f(x1,x2)] pdf [f(x3,x4)] pdf [f(xm,xn)] Gaussian pdf
..……..
* * Æ
Gaussian Distribution
0.4
Probability density p(x)

0.3
0.2
2 0.1
−(
x−μ )
1 2σ 2
p( x ) = e
2πσ 0
-3 -2 -1 0 1 2 3
where: (x-μ) /σ
μ is the expected value and
standard deviation :σ = E( X 2 ) − μ 2
σ 2 → variance
Yield
In most cases we are
0.4
Probability density
interested in finding the

0.3
percentage of
p(x)
components (e.g. R) 0.2

falling within certain 0.1
bounds: 0
P (− X ≤ x ≤ + X ) = 1
P(-X ≤ x ≤ +X)
95.4
2
0.8
+X − x 68.3
1 0.6
= ∫e
2π − X
2 dx
0.4 38.3
0.2
0
⎛ X ⎞ 0 0.5 1 1.5 2 2.5 3
= e rf ⎜ ⎟ X/σ
⎝ 2⎠
Yield
X/σ P(-X ≤ x ≤ X) [%] X/σ P(-X ≤ x ≤ X) [%]
0.2000 15.8519 2.2000 97.2193

0.4000 31.0843 2.4000 98.3605
0.6000 45.1494 2.6000 99.0678
0.8000 57.6289 2.8000 99.4890
1.0000 68.2689 3.0000 99.7300
1.2000 76.9861 3.2000 99.8626
1.4000 83.8487 3.4000 99.9326
1.6000 89.0401 3.6000 99.9682
1.8000 92.8139 3.8000 99.9855
2.0000 95.4500 4.0000 99.9937
Example
• Measurements show that the offset voltage of
a batch of operational amplifiers follows a
Gaussian distribution with σ = 2mV and μ = 0.
• Find the fraction of opamps with |Vos| < 6mV:

– X/σ = 3 Æ 99.73 % yield
• Fraction of opamps with |Vos| < 400μV:

– X/σ = 0.2 Æ 15.85 % yield
Component Mismatch
Example: Resistors layouted out 400
side-by-side
No. of resistors
300
……. ……. ΔR
200
R
100
After fabrication large # of
devices measured 0
& graphed Æ typically if 988 992 996 1000 1004 1008 1012
sample size large shape R[ Ω ]
is Gaussian E.g. Let us assume in this example 1000 Rs measured
& 68.5% fall within +-4OHM or +-0.4% of average
Æ 1σ for resistorsÆ 0.4%
Component Mismatch
Example: Two resistors 0.4
Probability density p(x)
layouted out side-by-side 0.35

0.3
0.25 ΔR
0.2
R
0.15
R1 + R2 0.1
R= 0.05
2
0
dR = R1 − R2 −3σ −2σ −σ 0 σ 2σ 3σ
dR
For typical technologies & geometries R
1 1σ for resistors Æ 0.02 to 5%
σ dR
2
∝
Are a
R In the case of resistors σ is a function of area
DNL Unit Element DAC
E.g. Resistor string DAC: Vref
Assumption: No systematic error- only random error
2B −1
Iref
∑o Ri
Δ = Rmedi an Iref w h ere Rmedian =
2B
Δi = Ri Iref
Δi − Δmedian
D N Li =
Δmedian Δi = Ri I ref
Ri − R dR dR
medi an
= = ≈
R R Ri
median median
σ DNL = σ dRi
Ri
To first order Æ DNL of unit element DAC is independent of resolution!
Note: Similar results for other unit-element based DACs

E.g. Resistor string DAC:
Example:
If σdR/R = 0.4%, what
σ D NL = σ dR DNL spec goes into
i
the DAC datasheet so
Ri
that 99.9% of all
converters meet the
spec?
Yield
X/σ P(-X ≤ x ≤ X) [%] X/σ P(-X ≤ x ≤ X) [%]
0.2000 15.8519 2.2000 97.2193

0.4000 31.0843 2.4000 98.3605
0.6000 45.1494 2.6000 99.0678
0.8000 57.6289 2.8000 99.4890
1.0000 68.2689 3.0000 99.7300
1.2000 76.9861 3.2000 99.8626
1.4000 83.8487 3.4000 99.9326
1.6000 89.0401 3.6000 99.9682
1.8000 92.8139 3.8000 99.9855
2.0000 95.4500 4.0000 99.9937

E.g. Resistor string DAC: Example:
If σdR/R = 0.4%, what DNL spec
goes into the datasheet so that
99.9% of all converters meet
σ D NL = σ dR i
the spec?
Ri Answer:
From table: for 99.9%
Æ X/σ = 3.3
σDNL = σdR/R = 0.4%
3.3 σDNL = 3.3x0.4%=1.3%
ÆDNL= +/- 0.013 LSB
DAC INL Analysis
Ideal Variance
N A=n+E n n.σε2
B B=N-n-E N-n (N-n).σε2

Output [LSB]
E E = A-n r =n/N N=A+B

n A = A-r(A+B)
= (1-r). A - r.B
Æ Variance of E:
n
Input [LSB]
N=2B-1 σE2 =(1-r)2 .σΑ2 + r 2 .σB2
=N.r .(1-r).σε2 = n .(1- n/N).σε2
DAC INL
σINL/σε
⎛ n⎞
σ E2 = n ⎜ 1 − ⎟ ×σ ε
2 (2B-1)0.5/2
⎝ N⎠
dσ E 2
T o f i n d ma x. var i a nce : =0
dn
N
→ n = N / 2 → σ E2 = ×σ ε 2
4
• Error is maximum at mid-scale (N/2):
1
σ IN L = 2B − 1 σε 0
2 0 0.5 1
w i th N = 2B − 1 n/N
• INL depends on both DAC resolution & element matching σε
• While σDNL = σε is to first order independent of DAC resolution and is
only a function of element matching
Ref: Kuboki et al, TCAS, 6/1982
Untrimmed DAC INL
Example:
1 B
σ INL ≅ 2 − 1 σε
Assume the following requirement 2
for a DAC:
σINL = 0.1 LSB ⎡ σ INL ⎤
B ≅ 2 + 2log 2 ⎢ ⎥
⎣ σε ⎦
Find maximum resolution for:
σε = 1% σε = 1% → Bmax = 8.6bits
σε = 0.5% σε = 0.5% → Bmax = 10.6bits
σε = 0.2% σε = 0.2% → Bmax = 13.3bits
σε = 0.1% σε = 0.1% → Bmax = 15.3bits
Simulation Example
12 Bit converter DNL and INL
2 σε = 1%
B = 12
DNL [LSB]
-0.04 / +0.03 LSB

1
Random #
generator used in
0
MatLab
-1
500 1000 1500 2000 2500 3000 3500 4000 Computed INL:
bin
2 σINLmax = 0.3 LSB
-0.2 / +0.8 LSB
(midscale)
INL LSB]
0
Why is the
results not as
-1
500 1000 1500 2000 2500 3000 3500 4000 expected per our
bin derivation?
INL & DNL for Binary Weighted DAC
Iout
• INL same as for unit
element DAC
• DNL depends on transition

–Example: 2B-1 Iref 4 Iref 2Iref Iref
……………
0 to 1 ÆσDNL2 = σ(dΙ/Ι) 2
1 to 2 Æ σDNL2 = 3σ(dΙ/Ι) 2
• Consider MSB transition:

0111 … Æ 1000 …
DAC DNL
Example: 4bit DAC
..
Analog ..
Iout Output [Iref]
.
I8on, I4off ,I2off ,I1off
8
I8off, I4on ,I2on ,I1on
7
I8 I2 I1 6
I4
8Iref 5
4Iref 2Iref Iref
4 I4on ,I2off ,I1off
..
..
.
3 I2on ,I1on
• DNL depends on transition
2 I2on ,I1off
– Example:
I1on
0 to 1 ÆσDNL2 = σ(dΙref/Ιref)2 1
Digital
1 to 2 Æ σDNL2 = 3σ(dΙref/Ιref)2
Input
0
0000 0001 0010 0011 0100 0101 0110 0111 1000
Binary Weighted DAC DNL
• Worst-case transition
DNL for a 4-Bit DAC occurs at mid-scale:
15
2
σ DNL ( )
= 2B−1 − 1 σ ε2 + 2B−1 σε2
144244
3 14243
( )
σDNL2/ σε2
0111... 1000...
10
≅ 2Bσ ε2
σ DNLma x = 2B / 2σε
5 1 1
σ INLmax ≅ 2B − 1 σ ε ≅ σ DNLmax
2 2
• Example:
0 2 4 6 8 10 12 14 B = 12, σε = 1%
DAC Output [LSB] ÆσDNL = 0.64 LSB
ÆσINL = 0.32 LSB
MOS Current Source Variations

Due to Device Matching Effects
Id1 + Id 2
Id =
2
Id1 Id2
dId Id1 − Id 2
=
Id Id
dId dW L 2 × dVth
= +
Id W
L VGS −Vth
• Current matching depends on:

- Device W/L ratio matching
Æ Larger device area less mismatch effect
- Current mismatch due to threshold voltage variations:
Æ Larger gate-overdrive less threshold voltage mismatch effect
Current-Switched DACs in CMOS
Iout
Iref Switch Array
dId dW L 2d Vth
= +
Id W
L VGS − Vth ……
256 128 64 ………..…..1
• Advantages: Example: 8bit Binary Weighted

Can be very fast
Reasonable area for resolution < 9-10bits
• Disadvantages:
Accuracy depends on device W/L & Vth matching
Unit Element versus Binary Weighted DAC

Unit Element DAC Binary Weighted DAC
B
σ DN L = σε σ DN L ≅ 2 2 σε = 2σ IN L
−1 B −1 B
σ IN L ≅ 2 2 σε σ IN L ≅ 2 2 σε
Number of switched elements:
S = 2B S=B
Key point: Significant difference in performance and complexity!
Unit Element versus Binary Weighted DAC
Example: B=10
Unit Element DAC Binary Weighted DAC
σ D NL = σ ε σ DNL ≅ 2 σ ε = 32σ ε
B
2
−1 −1
σ INL ≅ 2 σ ε = 16σ ε
B
σ I NL ≅ 2 σ ε = 1 6σ ε
B 2
2
Number of switched elements:
S = B = 10
S = 2B = 1 0 2 4
Significant difference in performance and complexity!
“Another” Random Run …

DNL and INL of 12 Bit converter
2 Now (by chance) worst
-1 / +0.1 LSB, DNL is mid-scale.
DNL [LSB]
1
0
-1
-2 Statistical result!
500 1000 1500 2000 2500 3000 3500 4000
bin
2
INL [LSB]
-0.8 / +0.8 LSB

1
-1
500 1000 1500 2000 2500 3000 3500 4000
bin
10Bit DAC DNL/INL Comparison
Plots: 100 Simulation Runs Overlaid
Ref: C. Lin
and K. Bult,
"A 10-b,
500-
MSample/s
CMOS DAC
in 0.6
mm2," IEEE
Journal of
Solid-State
Circuits, vol.
33, pp. 1948
- 1958,
December
1998.
Note: σε=2%
10Bit DAC DNL/INL Comparison

Plots: RMS for 100 Simulation Runs
Ref: C. Lin
and K. Bult,
"A 10-b,
500-
MSample/s
CMOS DAC
in 0.6
mm2," IEEE
Journal of
Solid-State
Circuits, vol.
33, pp. 1948
- 1958,
December
1998.
Note: σε=2%
DAC INL/DNL Summary
• DAC choice of architecture has significant impact on
DNL
• INL is independent of DAC architecture and requires

element matching commensurate with overall DAC
precision
• Results assume uncorrelated random element

variations
• Systematic errors and correlations are usually also

important and may affect final DAC performance
Ref: Kuboki, S.; Kato, K.; Miyakawa, N.; Matsubara, K. Nonlinearity analysis of resistor string A/D
converters. IEEE Transactions on Circuits and Systems, vol.CAS-29, (no.6), June 1982. p.383-9.
Segmented DAC
• Objective:
Compromise between unit element and binary weighted DAC
MSB (B1 bits) (B2 bits) LSB

… …
Unit Element Binary Weighted
• Approach: VAnalog
B1 MSB bits Æ unit elements
B2 LSB bits Æ binary weighted BTotal = B1+B2
• INL: unaffected same as either architecture

• DNL: Worst case occurs when LSB DAC turns off and one more MSB
DAC element turns on Æ Same as binary weighted DAC with (B2+1) # of
bits
• Number of switched elements: (2B1-1) + B2
Comparison
Example: ( B2 +1)
B = 12, B1 = 5, B2 = 7 σ DNL ≅ 2 2
σ ε = 2σ I NL
B1 = 6, B2 = 6 −1
σ I NL ≅ 2 σε
B
2
MSB LSB
S = 2B1 − 1 + B2
Assuming: σε = 1%
DAC Architecture σINL[LSB] σDNL[LSB] # of switched

(B1+B2) elements
Unit element (12+0) 0.32 0.01 4095
Segmented (6+6) 0.32 0.113 63+6=69
Segmented (5+7) 0.32 0.16 31+7=38
Binary weighted(0+12) 0.32 0.64 12

D/A Converters Continued:: - Component Matching - Systematic & Random Errors

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D/A Converters Continued:: - Component Matching - Systematic & Random Errors

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EE247

Resistor string DAC + Resistor string

Large R values for interpolating stringÆ

Can use buffers

• Operation based on redistribution of charge associated with C1 &

Charge Based: Serial Charge Redistribution DAC

→ QCT11 + QCT12 = VREF × C1 VREF × C1 = ( C1 + C2 )Vo

Serial Charge Redistribution DAC

Parallel Charge Scaling DAC

Æ Make Cx & Cy function of incoming DAC digital word

bB-1 (msb) b3 b2 b1 b0 (lsb)

Charge Scaling DAC

bB-1 (msb) b3 b2 b1 b0 (lsb)

• Sensitive to parasitic capacitor @ output

• Opamp helps eliminate the parasitic capacitor effect by producing virtual

bB-1 (msb) b3 b2 b1 b0 (lsb)

Charge Scaling DAC

Increase # of bits by replicating circuit

R-2R Ladder DAC

Emitter-follower added to convert to high output impedance current

VB 4xAunit 2xAunit 1xAunit 1xAunit

R-2R Ladder DAC

4Aunit 2Aunit Aunit Aunit 4Aunit 2Aunit 2Aunit

4Aunit 2Aunit 2Aunit 4Aunit 4Aunit

R-2R Ladder DAC

VB 4Aunit 2Aunit Aunit

In most cases need to convert output current to voltage

R-2R Ladder DAC

Current based DAC

Iref Iref Iref Iref Iref

• “Unit elements” or thermometer

Iref Iref Iref Iref

• Output resistance of current source Æ gain error problem

Current Source DAC

2B-1 Iref 4 Iref 2Iref Iref

Current Source DAC

Iref Iref Iref Iref Iref

Iref -ΔI Iref +ΔI

seg men t[ m] − V [ L S B ] Analog

• Each component is the product of many fabrication steps

ÆAssuming each of these variables have a uniform pdf distribution:

Probability density p(x)

interested in finding the

components (e.g. R) 0.2

0.2000 15.8519 2.2000 97.2193

• Find the fraction of opamps with |Vos| < 6mV:

• Fraction of opamps with |Vos| < 400μV:

layouted out side-by-side 0.35

DNL Unit Element DAC

0.2000 15.8519 2.2000 97.2193

DNL Unit Element DAC

ÆDNL= +/- 0.013 LSB

B B=N-n-E N-n (N-n).σε2

E E = A-n r =n/N N=A+B

-0.04 / +0.03 LSB

• DNL depends on transition

• Consider MSB transition:

MOS Current Source Variations

• Current matching depends on:

256 128 64 ………..…..1

• Advantages: Example: 8bit Binary Weighted

Unit Element versus Binary Weighted DAC

Number of switched elements:

Large R values for interpolating stringÆ

Can use buffers