6

1.5 Logic Gates

S.No. Gate Graphic Symbol Algebraic Function Truth Table

1. AND Y = AANDB A B y

:=0-, Y=A.B 0
0
1
O.
1
0
0
0
0
1 1 1
2. OR Y = A OR B A B Y
Y=A+B 0 0 0

3. NOT
:=D-' 0
1
1 1
1
0
1
1
1
Y = NOTA A A =Y
Y=A 0 1
A~. Y=A
1 0
4: NAND Y = ANOTANDB A B Y
= ANANDB 0 0 1
--
A~, Y=A.B 0 1 1
B . 1 0 1
1 1 0
5. NOR Y = ANOTORB A B Y
= ANORB 0 0 1

:=D-' Y = Y = (A + B) 0
1
1
1
0
1
0
0
0
6. EX-OR Y = .A EX-OR B A B Y
= A E9 B 0 O· 0
.........

7.
..

EX-NOR
.. :JD-' Y = AB + AB

Y = A EX-NOR B
0
1
1
A
1
0
1
B
0
Y
1
1

-
Y = AB + AB 0 0 1

.. .. .
.'
..
:": '. :
...
'

..
".'
"
'.;
-;.
..
~..
:~D-'
. . ..
-
=A0B 0
1
1
1
0
1
0
0
1

1.6 Logic Families

Since the introduction of integrated circuits (ICs) in 1960s, many logic families were
introduced into the market. The major requirements and the desirable features of a logic
family are:

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 Logic flexibility
 Availability of complex functions
 High noise immunity
 Wide operating temperature range
 Loading
 Speed
 Low power dissipation
 Lack of generated noise
 Input and output structures
 Packaging
 Low cost
ICs are fabricated using various technologies such as TTL, ECL, and IIL which use bipolar
transistors, whereas the MOS and CMOS technologies use unipolar MOSFETs.

Characteristics of Digital ICs

1. Propagation Delay

A pulse through a gate takes a certain amount of time to propagate from input to
output. This interval of time is known as the propagation delay of the gate. It is the average
transition delay time tpd, expressed by

where tPLH is the signal delay time when the output goes from a logic 0 to a logic 1 state and
tPHL is the signal delay time when the output goes from a logic 1 to a logic 0 state.
V 1\
WI

:~::;H..H H..{ =\:--: -'--_

~ (a) Input pulse ~ ~
. .
V out " :
•
:
:

:~;.~;HHHHHHL.\HHHHHHHL
~ .~ ~
~ ~ t
(b) Output pulse

Fig. 11.1 Propagation delay in an inverter.

2. Power Dissipation
Every logic gate draws some current from the supply for its operation. The current
drawn in HIGH state is different from that drawn in LOW state. The power dissipation PD, of
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logic gate is the power required by the gate to operate with 50% duty cycle at a specified
frequency and is expressed in milliwatts. This means that 1 and 0 periods of the output are
equal. The power dissipation of a gate is given by

Po = Vee x lecCavg)/n

where VCC is the gate supply voltage, ICC(avg) is the average current drawn from the supply
by the entire IC and n is the number of gates in the IC.

3. Fan – in
The fan – in of a logic gate is defined as the number of inputs that the gate is designed
to handle
4. Fan - out

The fan-out (also called the loading factor) of a logic gate is defined as the maximum
number of standard loads that the output of the gate can drive without impairing its normal
operation. A standard load is usually specified as the amount of current needed by an input of
another gate of the same IC family. If a gate is made to drive more than this number of gate
inputs, the performance of the gate is not guaranteed. The gate may malfunction.
Fan-out may be HIGH state fan-out, i.e. the fan-out of the gate when its output is a
logic l, or it may be LOW state fan-output, i.e. the fan-out of the gate when its output is a logic
0. The smaller of these two numbers is taken as the actual fan-out. The fan-out of a gate affects
the propagation delay time as well as saturation. The driving gate sinks current when it is in
LOW state and sources current when it is in HIGH state.
HIGH state fan-out = IOH (max)
Jilt
where IOH(max) is the maximum current that the driver gate can source when it is in a 1 state
and IIH is the current drawn by each driven gate from the driver gate.
LOW slate fan-out = IOL (max)
I'L
where IOL(max) is the maximum current that the driver gate can sink when its output is a logic
0 and IIL is the current drawn from each driven gate by the driver gate.

LOW

(a) Current sourcmg in HIGH state (b) Current sinking in LOW state
.
Fig. 11.2 HIGH state and LOW state fan-outs for TTL 7400 NAND gate.

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5. Speed Power Product

A common means for measuring and comparing the overall performance of an IC

family is the speed power product, which is obtained by multiplying the gate propagation delay
by the gate power dissipation. A low value of speed power product is desirable. The smaller
the product, the better the overall performance. The speed power product has the units of energy
and is expressed in picojoules. It is the figure of merit of an IC family. Suppose an IC family
has an average propagation delay of 10 ns and an average power dissipation of 5 mW, the speed
power product is
10 ns x 5 mW = 50 x 10-12 watt-seconds = 50 picojoules (pJ)

Advantages & Disadvantages of Various Logic Families

1. Transistor Transistor Logic (TTL)

a. Advantages
 It is the fastest logic family. TTL gates are available in form of high
speed, high speed schottky, low power schottky and a variety type
 It has good noise immunity. Typical noise margin is about 0.4 V.
 Power dissipation is in the megawatt range.
 Compatible with other logic families
 Commercial and military versions of TTL gates are available.
 More fan out; can drive upto 10 gates
 Low output impedance for higher/low states
b. Disadvantages
 Noise immunity is not very high.
 Power dissipation is much higher than MOS gates.
 Cost is higher.
 It generates transient voltages at switching instants.
2. Emitter – Coupled Logic (ECL)
a. Advantages
 Since transistor operates in the active region, highest speed among all
logic families.
 Complementary outputs are available
 Parameters do not vary much with temperature.
 Typical supply voltage is -5.2V
b. Disadvantages
 Very low noise margin.
 Highest power dissipation among all logic gates
 Capacity loading limits fan out
 Higher cost
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3. Complementary Metal Oxide Semiconductor Logic (CMOS)

a. Advantages
 Extremely large fan out capability (>50)
 Lowest power dissipation of all gates
 Very high noise immunity and noise margin
 Lower propagation delay than NMOS
 Single power supply required
 Temperature stability is excellent
b. Disadvantages
 Increased cost due to additional processing steps
 Packing density is less than the NMOS
 MOS chips must be protected

Comparison of Various Logic Families

Table 16.1 Comparison of logic families

Logic Propagation Power dissipation Noise Fan-in Fan-out Cost
family delay time (ns) per gate (mW) margin eV)
TTL 9 10 0.4 8 10 Low
ECL 1 50 0.25 5 10 High
MOS 50 0.1 l.5 10 Low
CMOS < 50 0.01 5 10 50 Low
IIL 1 0.1 0.35 5 8 Very low

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