BUS ARBITRATION

• A conflict occurs if the processor and a DMA controller or 2 or more DMA controllers
tries to use the bus at the same time to access the main memory.

• To resolve these conflicts an Arbitration procedure is implemented on the bus to

coordinate the activities of all the devices requesting the memory transfers.

• The device which is allowed to initiate data transfer on the bus at any given time is
always called Bus Master at that time. When the current master relinquishes the
control of the bus, another device can acquire this status.

• Bus arbitration is the process by which the next device to become the bus master is
selected and bus mastership is transferred to it.

• There are 2 approaches to the Bus arbitration procedure:

1. Centralized Bus Arbitration

2. Distributed Bus Arbitration.

 Centralized Bus Arbitration
• The bus arbiter may be the processor or a separate unit connected to the bus.

• In the above architecture the processor contains the bus arbitration circuit. Normally
processor is the bus master unless it grants bus mastership to one of the DMA
controllers.
• If a DMA controller needs the bus it sends an active signal to bus master over the BR
line
• If any of the DMA controller request for the bus, the BR line will be active.

• When BR line is activated, the processor grants the BG(Bus Grant) signal to the DMA
controller. This BG line is connected in daisy chain fashion. i.e. if DMA controller1
has requested the bus, it will block the propagation of BG signal to other DMA
controllers. Otherwise if DMA controller1 has not requested the bus, it will pass the
bus grant signal to the next device.

• The current bus master indicates to all other devices that it is using the bus by keeping
the BBUSY(Bus Busy) signal active.

• Hence after receiving the BG signal , the device waits for BBUSY signal to become
inactive and then assumes the mastership of the bus and makes the BBUSY signal
active and starts using the bus.
The timing diagram shows the sequence of events when DMA controller2 requests for
the bus and acquires the bus mastership from the processor and after some time
releases the bus.
 Distributed Arbitration

• In distributed arbitration all devices waiting for the bus have equal responsibility in
carrying out the arbitration process. Central arbiter is absent here.
• An example is illustrated by the following fig.
• Each device is given a 4 bit identification number.
• When one or more devices request the bus, they assert the Start-Arbitration signal
active and place their 4 bit code on the Arbitration lines ARB0 to ARB3.

• A winner is selected as a result of the interaction between the signals transmitted over
these arbitration lines.

• The process can be illustrated with an example in the next slide:

✓ Assume 2 devices with IDs 0 1 0 1 and 0 1 1 0 are trying to get the ownership of
the bus.

✓ Both devices send their IDs to the arbitration lines ARB0 to ARB3 through an
inverter.

✓ The resultant code seen by both the devices is 0 1 1 1.

✓ Each device compares its pattern ID with the pattern on the arbitration lines,
starting from the most significant bit. If a mismatch is found at any bit position, it
disables its drivers at that bit position and for all lower order bits.

✓ This causes the pattern on the arbitration lines to 0 1 1 0 which means that device
with ID 0 1 1 0 has won the contention.
 ARB3

ARB2
ARB1

ARB0

StartArbitra
tion

0101(Device A) 0110(Device B)