BUS

• Processor, main memory and I/O devices can be interconnected using a

common bus whose primary function is to provide communication paths for
the transfer of data.
• Bus protocol is the set of rules that govern the behavior of various devices
connected to the bus. This include when to place information on the bus,
when to assert control signals and so on.
• The bus lines can be grouped into data lines, address lines and control lines.
• The bus control lines also carry timing information. They specify the times at
which the processor and the i/o devices may place data on the bus or receive
data from the bus.
• Based on the timing information, there are two schemes for bus
implementation
(a) Synchronous Bus
(b) Asynchronous Bus
 SYNCHRONOUS BUS

• In synchronous bus all devices derive timing information from a common

clock line.

• Equally spaced pulses on these lines define equal time intervals. Each of
these intervals constitute a bus cycle during which one data transfer can
take place.

• Such a scheme is illustrated in next slide which shows the sequence of

events during an input(Memory read ) operation.

• Master(Bus master) is the device which initiate the data transfer and all
other devices are termed as slaves.
• At time t0, the bus master places the address on the address lines and
appropriate command on the control line. Since memory read operation is
to be performed, the control line corresponding to the READ signal will be
made active.

• Information travels over the bus and reaches to all the devices connected to
the bus. The delay between transmitting a data from the sender side and
receiving at the other end is called propagation delay.

• The difference t1-t0 should be larger than the maximum propagation delay
between two devices. It should be long enough to allow the devices to
decode the address and control signals so that the addressed device can
respond at time t1.

• It is important that slaves should not place data before t1 because

information on the data bus is unreliable during the period t0 – t1.
• The addressed device places the data at time t1 on the data bus.

• At the end of the clock cycle, at time t2 the master strobes the data from the
data bus and store it in the buffer(Memory Data Register or Memory Buffer
Register).

• The period t2-t1 should be greater than the maximum propagation delay
plus the setup time of the register in the master.
• This proposed scheme is a simple design but have some limitations.
✓ The clock period t2 – t0 must be chosen to accommodate the
slowest device connected to the bus. This forces all devices operate
at the speed of the slowest device.
✓ The processor has no way of determining whether the addressed
device has actually been responded. It simply assumes that at time t2
the input device places the data on the bus, or the output device has
been received the data from the bus.
 ASYNCHRONOUS BUS

• A handshake signal is used between master and slave.

• The common clock is replaced by two timing signals, master-ready and

slave-ready signals. The master-ready signal is asserted by the master to
indicate that it is ready for a transaction and the slave-ready signal is a
response from the slave.

• The master places the address and control information on the bus.
• Then it activates master-ready signal to indicate that it has done a
transaction. This causes all devices on the bus to decode the address on the
address bus.
• The addressed slave performs the requested operation and responds by
activating the slave-ready signal.
• At time t0, master places the address and control information on the bus. All
devices begin to decode the address.
• At time t1, the master activates the master-ready line to inform all the I/O
devices that the address and control information is already been sent.
t1 – t0 is intended to allow any skew that may occur in the bus. When two
signals transmitting simultaneously from a source may reach the destination
at different times. This is called skewing or bus skewing. This happens
because different lines on the bus may have different propagation delays.
Hence to guarantee that master-ready signal should not reach any of the
device before the address and control information the delay t1 – t0 must be
greater than the maximum possible bus skew.

• At time t2, the selected slave performs the required input operation by
placing data on the data lines. At the same time it activates the slave-ready
signal. The period t2 – t1 depends on the distance between the master and
the slave and the delays introduced by the slave circuitry.
• At time t3, the slave-ready signal arrives at the master indicating that the
input data is available on the bus. After a delay equivalent to the bus skew
the master strobes the data from the data bus into its buffer. At the same
time it drops the master-ready signal.

• At time t4, the master removes address and control signals from the bus.

• At time t5, the addressed device interface detects a 1 to 0 transition on the

master-ready signal, it removes the data and the slave-ready signal from the
bus. This completes the input transfer.