INTERFACE CIRCUITS

• An I/O interface consists of a circuitry required to connect an I/O device to a

computer bus.

• One side of the interface consists of bus signals for address, data and control
signals. The other side consists of the data path with its associated control (to
transfer the data between the interface and I/O Device).This side is called a port.

• The following are the functions of the I/O interface:

✓ I/O interface provides a storage buffer for a least one word of data.
✓ It contains a status flag that can be accessed by the processor to determine
whether the buffer is full..
✓ It has an address decoding circuitry.
✓ It generates appropriate timing signals required by the bus control scheme
✓ Mechanisms for format conversions such as serial to parallel.
 PARALLEL PORT
• A parallel port transfers data in group of bits simultaneously to/from the
device.
• In Parallel Port, the connections between the device and the computer uses a
multiple pin connector and a cable with as many wires, typically arranged in a
flat configuration.
• This type of arrangement is suitable for devices which are physically close to
the computer.
• The following fig. shows an example of an input parallel port used for
connecting a keyboard to a processor.
• The interface circuit is connected to an asynchronous bus and thus the data
transfers is controlled by handshake signals.
• The processor sends address of the device through the address bus and
sends a 1 through R/ W signal to initiate a read operation.
• After some time it sends Master-ready signal to indicate that master is ready
to read the data.
• A typical keyboard consists of mechanical switches which are normally
open.
• When a key is pressed, it closes the switch and a path is established for the
electric signal.
• This signal is detected by an encoder circuit and an ASCII code is generated
for the corresponding character.
The difficulty with such push button keyboard is that, the
contact bounces when a key is pressed. i.e. a single press on the key may be
interpreted as the key being pressed and released several times. To neglect
this bouncing effect a debouncing circuitry is used.
• The output of the encoder consists of the bits for the ASCII code of the
pressed key and a valid control signal. The valid control signal is used to
indicate the input interface that the data is available on the bus.

• When a key is pressed, the valid control signal changes from 0 to 1, the
data is read from the bus and store it in the DATAIN register of the
interface and make the SIN flag value as 1.

• The slave which is the keyboard responds by sending a Slave Ready signal
whenever data is available and will place relevant data on the data bus.

• SIN value will be cleared to 0 when the CPU reads the data from the
DATAIN register.
• The following figure shows an parallel port for output interface used to
connect a printer to the computer.

• Valid and Idle are handshake signals used between printer and the interface
circuitry. When printer is ready to accept a character it will activate the idle
signal.
• Now the interface circuit places data from the DATAOUT register to the
data bus and activate the valid signal.
• In response printer starts printing the character and deactivate the Idle
signal. When the 1 to 0 transition of idle signal is detected at the interface it
sets the valid signal to zero.

• The interface consists of a DATAOUT register and SOUT flag.

• The SOUT flag is set to 1 if the printer is ready to accept a new character
and it is cleared to 0 when the data is loaded in the DATAOUT register by
the processor.
 SERIAL PORT

• In serial port data is transferred sequentially one bit at a time. This is in

contrast to a parallel port which communicates multiple bits simultaneously
in parallel.

• The key feature of a serial interface is that it is capable of communicating in

a bit serial fashion on the device side and in a bit-parallel fashion on the
processor side.

• The block diagram of a typical serial interface is shown in the next slide.
• It includes DATAIN and DATAOUT registers.
• The input shift register accepts data serially from the I/O device. When all
the 8-bits are received the data is loaded in parallel into the DATAIN
register.
• Similarly in output operation, processor loads the data into DATAOUT
register in parallel. From the DATAOUT register bits are shifted out in
serial manner to the output device.
• SIN flag is set to 1 when new data is loaded in DATAIN, to indicate the
processor that data can be read from the device. It is cleared when the data
is read by the CPU.
• SOUT flag indicates whether the output buffer is available. It will be
cleared to 0 when processor loads data into DATAOUT register. It will be
set to 1 after the contents of DATAOUT register are transferred to output
shift register.

• Serial communication requires fewer wires than parallel communication. So

it is suitable for long distance communication.