Assignment -2 _2EL42_Digital System Design

Name: Dhruv Gor

Id: 20EL100
1. Design 4-bit ripple carry adder with 1-bit adder.
➢ Design code:-

module ripple_carry_adder(a,b,c_in,s,c_out);
input [3:0] a, b,
input c_in;
output [3:0] s; output c_out;
wire kl, k2, k3;

full_adder fal(a[0],b[0],c_in,s[0],k1);

full_adder fa2(a[1],b[1],k1,s[1],k2); full_adder

fa3(a[2],b[2],k2,s[2],k3);

full_adder fa4(a[3],b[3],k3.s[3],c_out);

endmodule

module full_adder(a,b,c_in,s,c_out);
input a,b,c_in;
output s.c_out,

assign s = a^b^c_in;
assign s=a^b^c_in; assign c_out=a&b || b&c_in || a&c_in;
endmodule
 ➢ Testbench Code:-

module add;
reg [3:0] a;
reg [3:0] b;
reg c_in; wire[3:0] s;
wire c_out;

initial begin

$monitor("time=%g | A=%b B=%bc_in=%b | C_out=%b | S=

%b",$time,a,b,c_in_c_out,s);

end

ripple_carry_adder uut( a,b,c_in,s,c_out);

initial begin
a =4'b0000;
b =4'b0000;
c_in = 1'b0;

#10
a =4'b0001; b =4'b0001;
c_in = 1'b0;
#10 a =4'b0011;
b =4'b0011;
c_in = 1'b0;
#10 a =4'b0111;
b =4'b0111; c_in 1'b0;
#10
a =4'bl111; b =4'b1111;
c_in = 1'b0;
#10
a =4'b0000;
b =4'b0000;
c_in = 1'b1;
#10 a =4b0001;
b =4'b0001; c_in = 1'b1; #10
a =4'b0011; b =4'b0011;
c_in = 1'b1; #10
a =4'b0111; b =4'b0111;
c_in = 1'b1;
#10
a =4'b1111; b =4'b1111; c_in=1'b1;
end

initial begin
$dumpfile("fullader.ved"); $dumpvars();
end
endmodule
➢ Output:-
2. Reuse 2:1 mux code to implement 8:1 mux.
➢ Design Code:-
module mux_8x1 (a,s,out);
input [7:0] a; input [2:0] s;
output out,
wire [6:0]k;
mux_2x1 mx1(a[0].a[1],s[0],k1); mux_2x1
mx2(a[2],a[3],s[0],k2);

mux_2x1 mx3(a[4],a[5],s[0],k3); mux_2x1

mx4(a[6],[7],s[0],k4);

mux_2x1 mx5(k1,k2,s[1],k5); mux_2x1 mx6(k3,k4,s[1],k6);

mux_2x1 mx8(k5,k6,s[2],out);
endmodule

module mux_2x1(a0,al,s,out);
input a0,al,s;
output out;
wire sn,k1,k2;
not(sn,s);
and(k1,a0,sn);
and(k2,al,s);
or(out,k1,k2);
endmodule

➢ Testbench Code:-

module main;
reg [7:0] a; reg [2:0] s;
wire out;
 initial begin
$monitor("time=%g S2%b | S1%b S0%b | Output=
%b",$time,s[2],s[1],s[0],out);
end

mux 8x1 uut(a,s,out);

initial begin
a8b01010101;
s[2]=0; s[1]= 0; s[0] = 0;
#10
s[2]= 0; s[1]=0; s[0] = 1; #10
s[2]=0; s[1]= 1; s[0] = 0; #10
s[2]=0; s[1]= 1; s[0] = 1; #10
s[2]= 1; s[1]=0; s[0] = 0; #10
s[2]= 1; s[1]=0; s[0] = 1; #10
s[2]= 1; s[1]= 1; s[0] = 0; #10
s[2]= 1; s[1]= 1; s[0] = 1;
end

initial begin
$dumpfile("result.vcd"); $dumpvars();
end
endmodule

➢ Output:-
3. Design a Full Substractor with gate level modelling
style.
➢ Design Code:-

module full_subrator(x,y,b_in,b_out,d);

input x,y,b_in,
output b out,d;
wire d1, b1,62,63,xn,
xor(d1,x,y); xor(d,d1,b_in);
not(xn, x);
and(b1,xn,y).
and(b2,xn, b_in);
and(b3, y,b_in),
or(b_out, b1,62,63);

endmodule

➢ Testbench Code:-
module main;

reg x,y,b_in; wire d, b_out,

initial begin

$monitor("%g | x=%b | y=%b | b_in=%b

D=%bb_out=%b",$time, x.y.b_in.d.b_out);

end

full subrator sb0( x, y, b_in, b_out, d);

initial begin x=1'b0; y=1'b0; b_in=1'b0;

#10

x=1'b0; y =1'b0; b_in=1'b1;

#10

x=1'b0; y =1'b1; b_in=1'b0; #10

x=1'b0; y = 1'b1; b_in=1'b1;

#10

x=1'b1; y =1'b0; b_in=1'b0;

#10

x=1'b1; y=1'b0; b_in=1'b1;

 #10

x=1'b1; y = 1'b1; b_in=1'b0; #10

x=1'b1; y=1'b1; b_in=1'b1;

#10

x=1'b0; y =1'b0; b_in=1'b0,

end

initial begin
//$monitor("%t, X=%d Y = %d Z = %d B = %d D = %d", $time,
X. Y, Z. B, D),
$dumpfile("subrator.vcd"); $dumpvars();
end
endmodule

➢ Output:-
4. Design a 2X4 decoder using gate level modelling

➢ Design code:-

decoder_2x4(a0,al,b0,61,62,63); output b0,61,62,63,

input a0,al;
wire aon,aln;
not(aOn,a0);
not(aln,al);
and(b0,a0n,aln):
and(bl.a0n,al);
and(b2,a0,aln);
and(b3,a0,al);

endmodule

➢ Testbench Code:-
module main,
reg a0,al; wire b0,61,62,63;
initial begin
$monitor("time=%g | a0=%b al = %b b0%b | bl=%b | b2 = %b | b3
= %b "Stime,a0,al,b0,61,62,63);
end
decoder_2x4 uut(a0,al,b0,b1, b2,b3); //intiate the design
initial
begin

a0=0; a1= 0;
#5
a0=0; al= 1;
#5
a0= 1; al=0;
#5
a0= 1; al= 1;
#5
a0=0; al=0;
end

initial
begin $dumpfile("decoder.vcd");
end

$dumpvars;
End
endmodule

➢ Output:-
5. Design 4x1 mux using operator.
➢ Design Code:-
module mux 4x1(a,s,out);
input [3:0] a;
input [1:0] s;
output out,
wire sin,son,d1,d2,d3,d4;
not(sln,s[1]);
not(son,s[0]);

and(d1,a[0],sln,son);

and(d2,a[1],sln,s[0]); and(d4,a[3].s[1],s[0]);

and(d3,a[2],s[1],s0n);
or(out,d1,d2,d3,d4);
endmodule.

> Codes for testbench:-

‘include "mux_4x1.v" module tb,

reg [3:0] a;
reg [1:0] s;
wire out;

initial begin
$monitor("%g sl=%b | s0%b | output = ",$time.s[1],s[0],out);
end

mux 4x1 uut(a,s,out);

initial begin
a=4'b1010;
s[1]=0; s[0]=0;
#10
s[1]=0; s[0] = 1;
#10
 s[1]= 1; s[0] = 0;
#10
s[1]= 1; s[0] = 1;
#5
a=4'b0101;
s[1]= 0; s[0] = 0;
#10
s[1]= 0; s[0] = 1;
#10
s[1] = 1; s[0] = 0;
#10

end

initial begin
$dumpfile("mux_4x1.vcd"); Sdumpvars();
end
endmodule

➢ Output:-
6.Design Full adder using Half adder.
➢ Design Code:-
module full_adder(a,b,c_in,c_out,s);

input a,b,c_in;
output c_out,s;

wire s1,c1, c2;

half_adder hf1(a,b,s1,c1); half_adder hf2(c_in,s1,s,c2);

or (c,c1, c2);
endmodule

module half_adder(a,b,s,c); output s,c;

input a,b;

assign s = a^b;
assign c = a&b;
endmodule

➢ Testbench Code:-

module tb;
reg a,b,c_in; wire s, c_out;

initial begin
$monitor("%t | A=%b | B=% b | c_in=%b | c_out=%b | s =
%b",$time,a,b,c_in,c_out,s);
end

full_adder FA(a,b,c_in,c_out,s); initial begin

 a = 0; b = 0; c_in = 0;
#5
a=0; b=0; c_in = 1;
#5
a = 0; b= 1; c_in = 0;
#5
a = 0; b=1;c_in = 1;
#5
a = 1; b = 0; c_in = 0;
#5
a = 1; b=0; c_in = 1;
#5
a = 1; b= 1; c_in = 0;
#5
a= 1; b= 1; c_in = 1;
end

initial begin
$dumpfile("fulleradder.vcd");
$dumpvars();
end
endmodule

➢ Output:-