Abstract

This project is intended to design a sequential ring counter for the given number
sequence. The project has been split into two closely linked parts.
Firstly, for the given sequence and flip flop, a counter was designed by making
the state table and state diagram. Using the skill of k map the minimized sum of
product expression was developed and used to make circuit with AND OR logic
gates.
Moreover, the same was repeated but for the different flip flop and without the
need for sum of product expression. Thus, instead of AND OR gates, multiplexers
was used. Also a prime number detector was used to indicate if the number was
a prime number.
Lastly, in addition to this a seven segment display chip was made and used in both
parts. The project was implemented using logisim software.

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Table of content
Section Title Page no#
1.0 INTRODUCTION 1
1.1 Ring Counter 1
1.2 State diagram 1
1.3 State table 2
1.4 Flip Flop 2
1.5 Multiplexers 4
2.0 CONTENT 5
2.1 DESIGN PROBLEM 1 5
2.1.1 Identify Design problem 5
2.1.2 State Diagram for Design Problem 1 5
2.1.3 State table for Design Problem 1 6
2.1.4 Karnaugh maps and equations for Design Problem 1 7
2.1.5 Circuit for Design Problem 2 9
2.2 DESIGN PROBLEM 2 10
2.2.1 Identify Design problem 10
2.2.2 State Diagram for Design Problem 2 10
2.2.3 State table for Design Problem 2 11
2.2.4 Multiplexer Input Table 12
2.2.5 Circuit for Design Problem 2 13
2.3 ADDITIONAL : SEVEN SEGMENT DISPLAY 14
2.3.1 Truth Table for Seven segment 14
2.3.2 Karnaugh maps and Equations 14
2.3.3 Circuit Diagram and Chip Layout 15
3.0 CONCLUSION 16
4.0 BIBLIOGRAPHY 17

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List of figures

Figure Title Page no#

Figure 1 D flip flop Ring counter 1

Figure 2 State diagram of the four flip flop 1

Figure 3 Example of a state table 2

Figure 1: The SR Latch circuit 2

Figure 5 SR, JK, T flip-flop internal circuitry 3

Figure 6 Excitation table for JK SR and T Flip flop 3

Figure 7 Example of a multiplexter, 2x1 mux 4

Figure 8 State diagram 5

Figure 9 k-map and sop equations for T3 and T2 flip-flop 7

Figure 10 k-map and sop equations for SR1 flip-flop 7

Figure 11 k-map and sop equations for SR0 flip-flop 8

Figure 12 Design Problem 1 circuit diagram 9

Figure 13 State diagram 10

Figure 2 Circuit diagram for design problem 2 13

Figure 3 k-map seven segment display 14

Figure 16 seven segment display circuit and chip pinout diagram 15

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List of tables

Table
title Page no#
no#

Table 1 T flip flop excitation table 5

Table 2 SR flip flop excitation table 5

Table 3 State table => Design problem 1 6

Table 4 JK flip flop excitation table 10

Table 5 State Table => Design problem 2 11

Table 6 Seven Segment Display truth table 14

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List of acronyms

Acronyms Meaning

1 Binary representation High

0 Binary representation low

X Binary representation unused state

D Memory circuit (chip)

T Memory circuit (chip)

SR Memory circuit (chip)

JK Memory circuit (chip)

mux Multiplexer

k-map Karnaugh map

SOP Sum of product

MSB Most significant bit

LSB Least significant bit

AND Logic gate

OR Logic gate

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1.0 INTRODUCTION
For the purpose of this project, it is vital to first of all understand what a ring counter is.
Moreover it is also vital to understand the workings and functions of a state table and
state diagram. In addition the main components of this project, the flip flops and the
multiplexer and how it helps the circuit remember the sequence of the circuit.
1.1 Ring counter
A ring counter is a sequential logic circuit made using a shift register in which same data
is recirculated using clock pulse. The counter is connected using flip flops where the
output of the previous flip flop is the input in the next.

Figure 4: D flip flop Ring counter

As seen in the above D flip flop, this is how the flip flop able to circulate data throughout
its system in a ring pattern as the input value is circulated between its flip flops [1].
1.2 State diagram
State diagram have the same functionality in all of its application. Hence, in digital logic
design, a state diagram is graphical representation of a sequence in its different stages
depending on the input, pattern and direction the sequence will flow. In simple terms a
state diagram is a simplified way to visually represent a very complex sequence and
expression.

Figure 5: State diagram of the four flip flop

As an example the state diagram of the 4 flip flops is shown above [2].

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1.3 State table
Another way of representing a sequence is by using the help of state tables. The state
table is just the representation of state diagram in three main stages.

Figure 6 Example of a state table

The current state is usually all the possible stage for a given number of bits.
The next state is the number that comes after the current state. The next state in
dependent on the condition, control (system input) which indicate where the sequence
should point next.
Lastly, the table has a certain output Y corresponding to the input [3].
1.4 Flip flop
A flip flop is a basic electronic circuit which is capable to store binary data. For this
project we will focus on 3 types of flip flop which are, SR, T and JK flip flop. Most flip flop
contains something known as a SR latch

Figure 7: The SR Latch circuit

The only difference is that a SR flip flop contain a clock which make it synchronous.

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 Figure 8: SR, JK, T flip-flop internal circuitry
A JK flip-flop is a better version of SR flip flop as it is able to give an output for S=R=1
without any problem. A T flip flop is basically a JK flip-flop with both J and K input as the
same.

Figure 9: excitation table for JK SR and T Flip flop

In order to use a flip flop we have to insert the excitation table of the respective flip flop
in the state table in order to get the input for each flip flop [4].

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1.5 Multiplexers
A multiplexer (mux) is a 2^n input and a single output combinational circuit.

Figure 10: Example of a multiplexter, 2x1 mux

A mux is basically made up of 3 important components, the input, selector and output.
The mux will always have a single output, however the number of input of the mux is 2
to the power of number of selector. The mux is always labeled according to the number
of input by 1 mux [5].

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2.0 Content
2.1 DESIGN PROBLEM 1
2.1.1 Identify Design problem

Inputs
One input => X

Flip flops
2 flip flop: T flip flop, SR flip flop
Table 1: T flip flop Table 2: SR flip flop
Q Q* J Q Q* S R
0 0 0 0 0 0 x
0 1 1 0 1 1 0
1 0 1 1 0 0 1
1 1 0 1 1 x 0

Number of flip flop = largest number of bits in the largest number

Since the largest number is 15 which is 1111 in binary, 4 flip flop will be used
2 T flip flop and 2 SR flip flop
2.1.2 State Diagram for Design Problem 1
State diagram:

Figure 11: state diagram

Note: All unused state will point to 1

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2.1.3 State table for Design Problem 1

Table 3: State table => Design problem 1

Sys
Current state Next state Flip Flop
in
x q3 q2 q1 q0 q3 q2 q1 q0 t3 t2 s1 r1 s0 r0
0 0 0 0 0 0 0 0 0 1 0 0 0 X 1 0
1 0 0 0 0 1 1 1 1 1 1 1 1 0 x 0
2 0 0 0 1 0 1 1 0 1 1 1 0 1 1 0
3 0 0 0 1 1 0 0 0 1 0 0 0 1 x 0
4 0 0 1 0 0 0 0 0 1 0 1 0 X 1 0
5 0 0 1 0 1 1 0 0 1 1 1 0 X x 0
6 0 0 1 1 0 0 0 0 1 0 1 0 1 1 0
7 0 0 1 1 1 0 0 0 1 0 1 0 1 x 0
8 0 1 0 0 0 1 0 1 1 0 0 1 0 1 0
9 0 1 0 0 1 0 0 1 0 1 0 1 0 0 1
10 0 1 0 1 0 0 0 0 1 1 0 0 1 1 0
11 0 1 0 1 1 0 1 0 1 1 1 0 1 x 0
12 0 1 1 0 0 0 0 0 1 1 1 0 X 1 0
13 0 1 1 0 1 1 1 1 0 0 0 1 0 0 1
14 0 1 1 1 0 0 1 1 1 1 0 x 0 1 0
15 0 1 1 1 1 1 0 0 0 0 1 0 1 0 1
0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0
1 1 0 0 0 1 0 1 1 1 0 1 1 0 x 0
2 1 0 0 1 0 1 0 0 1 1 0 0 1 1 0
3 1 0 0 1 1 0 0 0 1 0 0 0 1 x 0
4 1 0 1 0 0 0 0 0 1 0 1 0 X 1 0
5 1 0 1 0 1 1 0 1 1 1 1 1 0 x 0
6 1 0 1 1 0 0 0 0 1 0 1 0 1 1 0
7 1 0 1 1 1 1 1 1 0 1 0 x 0 0 1
8 1 1 0 0 0 1 1 1 1 0 1 1 0 1 0
9 1 1 0 0 1 0 1 0 1 1 1 0 X x 0
10 1 1 0 1 0 0 0 0 1 1 0 0 1 1 0
11 1 1 0 1 1 1 0 0 0 0 0 0 1 0 1
12 1 1 1 0 0 0 0 0 1 1 1 0 X 1 0
13 1 1 1 0 1 0 0 1 0 1 1 1 0 0 1
14 1 1 1 1 0 1 1 0 1 0 0 0 1 1 0
15 1 1 1 1 1 0 0 0 1 1 1 0 1 x 0

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2.1.4 Karnaugh maps and equations for Design Problem 1

Figure 12: k-map and sop equations for T3 and T2 flip-flop

Figure 13: k-map and sop equations for SR1 flip-flop

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Figure 14: k-map and sop equations for SR0 flip-flop

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2.1.5 Circuit for Design Problem 2

Figure 15: Design Problem 1 circuit diagram

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2.2 DESIGN PROBLEM 2
2.2.1 Identify Design problem
Inputs
One input => X
Flip flops
1 flip flop: JK flip Flop
Table 4: JK flip flop excitation table
Q Q* J K
0 0 0 x
0 1 1 X
1 0 x 1
1 1 x 0
Number of flip flop = largest number of bits in the largest number
Since the largest number is 15 which is 1111 in binary, 4 JK flip flop will be used
2.2.2 State Diagram for Design Problem 2
Same as design problem 1

Figure 16: state diagram

Note: All unused state will point to 1

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2.2.3 State table for Design Problem 2
Table 5: State Table => Design problem 2
Current state in Next state Flip flop out
q3 q2 q1 q0 x q3 q2 q1 q0 J3 K3 J2 K2 J1 K1 J0 K0 Y
0 0 0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X 0
1 0 0 0 0 0 0 0 0 1 0 X 0 X 0 X 1 X 0
2 0 0 0 1 0 1 1 1 1 1 X 1 X 1 X X 0 0
3 0 0 0 1 0 0 1 1 1 0 X 1 X 1 X X 0 0
4 0 0 1 0 0 1 1 0 1 1 X 1 X X 1 1 X 1
5 0 0 1 0 0 1 0 0 1 1 X 0 X X 1 1 X 1
6 0 0 1 1 0 0 0 0 1 0 X 0 X X 1 X 0 1
7 0 0 1 1 0 0 0 0 1 0 X 0 X X 1 X 0 1
8 0 1 0 0 0 0 0 0 1 0 X X 1 0 X 1 X 0
9 0 1 0 0 0 0 0 0 1 0 X X 1 0 X 1 X 0
10 0 1 0 1 0 1 0 0 1 1 X X 1 0 X X 0 1
11 0 1 0 1 0 1 0 1 1 1 X X 1 1 X X 0 1
12 0 1 1 0 0 0 0 0 1 0 X X 1 X 1 1 X 0
13 0 1 1 0 0 0 0 0 1 0 X X 1 X 1 1 X 0
14 0 1 1 1 0 0 0 0 1 0 X X 1 X 1 X 0 1
15 0 1 1 1 0 1 1 1 0 1 X X 0 X 0 X 1 1
16 1 0 0 0 0 1 0 1 1 X 0 0 X 1 X 1 X 0
17 1 0 0 0 0 1 1 1 1 X 0 1 X 1 X 1 X 0
18 1 0 0 1 0 0 0 1 0 X 1 0 X 1 X X 1 0
19 1 0 0 1 0 0 1 0 1 X 1 1 X 0 X X 0 0
20 1 0 1 0 0 0 0 0 1 X 1 0 X X 1 1 X 0
21 1 0 1 0 0 0 0 0 1 X 1 0 X X 1 1 X 0
22 1 0 1 1 0 0 1 0 1 X 1 1 X X 1 X 0 1
23 1 0 1 1 0 1 0 0 0 X 0 0 X X 1 X 1 1
24 1 1 0 0 0 0 0 0 1 X 1 X 1 X 0 1 X 0
25 1 1 0 0 0 0 0 0 1 X 1 X 1 X 0 1 X 0
26 1 1 0 1 0 1 1 1 0 X 0 X 0 1 X X 1 1
27 1 1 0 1 0 0 0 1 0 X 1 X 1 1 X X 1 1
28 1 1 1 0 0 0 1 1 1 X 1 X 0 X 0 1 X 0
29 1 1 1 0 0 1 1 0 1 X 0 X 0 X 1 1 X 0
30 1 1 1 1 0 1 0 0 0 X 0 X 1 X 1 X 1 0
31 1 1 1 1 0 0 0 0 1 X 1 x 1 X 1 X 0 0

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2.3.4 Multiplexer Input Table

Mux inputs: Table 6: Input Values for multiplexer

J3 In0 In1 In2 In3 In4 In5 In6 In7 In8 In9 In10 In11 In12 In13 In14 In15
X’ 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
x 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
Input 0 X’ 1 0 0 1 0 x 0 0 0 0 0 0 0 0

k3 In0 In1 In2 In3 In4 In5 In6 In7 In8 In9 In10 In11 In12 In13 In14 In15
X’ 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
x 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
Input 0 0 0 0 0 0 0 0 0 1 1 X’ 1 x X’ x

J2 In0 In1 In2 In3 In4 In5 In6 In7 In8 In9 In10 In11 In12 In13 In14 In15
X’ 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
x 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
Input 0 1 X’ 0 0 0 0 x x 0 X’ 0 0 0 0

K2 In0 In1 In2 In3 In4 In5 In6 In7 In8 In9 In10 In11 In12 In13 In14 In15
X’ 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
x 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
Input 0 0 0 0 1 1 1 X’ 0 0 0 0 1 x 0 1

J1 In0 In1 In2 In3 In4 In5 In6 In7 In8 In9 In10 In11 In12 In13 In14 In15
X’ 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
x 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
Input 0 1 0 0 0 x 0 0 1 X’ 0 0 0 1 0 0

K1 In0 In1 In2 In3 In4 In5 In6 In7 In8 In9 In10 In11 In12 In13 In14 In15
X’ 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
x 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
Input 0 0 1 1 0 0 1 X’ 0 0 1 1 0 0 x 1

J0 In0 In1 In2 In3 In4 In5 In6 In7 In8 In9 In10 In11 In12 In13 In14 In15
X’ 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
x 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
Input 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

K0 In0 In1 In2 In3 In4 In5 In6 In7 In8 In9 In10 In11 In12 In13 In14 In15
X’ 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
x 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
Input 0 0 0 0 0 0 0 x 0 X’ 0 0 0 1 0 X’

Y In0 In1 In2 In3 In4 In5 In6 In7 In8 In9 In10 In11 In12 In13 In14 In15
X’ 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
x 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31
Input 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 0

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2.2.5 Circuit for Design Problem 2

Figure 17: Circuit diagram for design problem 2

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2.3 ADDITIONAL: SEVEN SEGMENT DISPLAY

2.3.1 Truth Table for Seven segment

Table 6:Seven Segment Display truth table
Input First digit Second digit
MSB B2 B3 LSB A1 B1 C1 D1 E1 F1 G1 a2 b2 c2 d2 e2 f2 g2
0 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0
0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 0 0
0 0 1 0 1 1 1 1 1 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 1
0 1 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1
0 1 0 1 1 1 1 1 1 1 0 1 0 1 1 0 1 1
0 1 1 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 1 1 0 1 1 1 0 0 1 1
1 0 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0
1 0 1 1 0 1 1 0 0 0 0 0 1 1 0 0 0 0
1 1 0 0 0 1 1 0 0 0 0 1 1 0 1 1 0 1
1 1 0 1 0 1 1 0 0 0 0 1 1 1 1 0 0 1
1 1 1 0 0 1 1 0 0 0 0 0 1 1 0 0 1 1
1 1 1 1 0 1 1 0 0 0 0 1 0 1 1 0 1 1

2.3.2 Karnaugh maps and Equations

A1 B1 C1 a2 b2 c2

D1 E1 F1 d2 e2 f2

G1 g2

Figure 18: k-map seven segment display

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2.3.3 Circuit Diagram and Chip Layout

A1
B1
C1
D1

Q3 E1
F1
Q2 G1
a2
Q1 b2
c2

Q0 d2
e2

f2
g2

Pin A1=> G1 for first digit

Pin a2 => g2 for second digit

Figure 19: seven segment display circuit and chip pinout diagram

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3.0 Conclusion

In conclusion, in main purpose of the project was achieved as the synchronous counter
had successfully displayed the unique ring sequence. Despite facing a bit of a challenge
understanding how the logisim software works the project was successfully
implemented. While conducting this project, it has shown numerous problems and
ways in which mistake were made. For instance when drawing the k-map some of the
values was incorrectly inserted in the k-map and even while connecting wires in logisim.
Hence it is seen that for a successful logic design it is necessary to be focused and ensure
no mistake or error is made while conducting any step in designing.
Despite that, it is notable that to implement a function, there are more than one way.
For instance in this project the implementation of the counter was done using
combinational (and or) analysis or by using multiplexer. Never the less any method used
has its own advantages and disadvantages respectively.
Summing up, it is a vital importance to understand concept and how to use components
in conjunction with practice using various software in order to be able to master the
skill of designing sequential problems.

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4.0 Bibliography

[1] Administrator, "Electronic Hub," 13 August 2015. [Online]. Available:

https://www.electronicshub.org/ring-counters-johnson-ring-counter/. [Accessed
16 June 2021].

[2] "0sp.mans.edu," 2021. [Online]. Available:

http://osp.mans.edu.eg/cs212/Seq_circuitst_FF_states.htm. [Accessed 16 June
2021].

[3] "All About Circuits," EETech Media, LLC., 2019. [Online]. Available:
https://www.allaboutcircuits.com/textbook/digital/chpt-11/finite-state-
machines/. [Accessed 16 June 2021].

[4] Electronicsforu.com, "Electronicsforu.com," 20 Janurary 2020. [Online]. Available:

https://www.electronicsforu.com/technology-trends/learn-electronics/flip-flop-rs-
jk-t-d . [Accessed 16 June 2021].
[5] JavaTpoint, "JavaTpoint," 2021. [Online]. Available:
https://www.javatpoint.com/multiplexer-digital-electronics. [Accessed 16 june
2021].

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