DIGITAL DESIGN 2022-23

Exp.No: 1

TESTING OF LOGIC GATES

Aim: To test and verify the truth table of following logic gates using ICs.

NAND (IC7400) Gate, NOR (IC7402) Gate, NOT (IC7404) Gate, AND (IC7408) Gate, OR
(IC7432), XOR(IC7486) Gate and XNOR (IC747266) Gate.
Apparatus Required
o IC 7400 ,IC 7402 , IC 7404 , IC 7408 1 no (each IC )
IC 7432 , IC 7486 , IC 74266
o Patch Cord / Connecting Wires

Theory
OR (IC7432)Gate:
The OR Gate performs logical addition, commonly known as OR Function. IC7432 is a
quad 2-input OR function. It has two or more inputs and only one output. The operation of OR
gate is such that a HIGH (1) on the output is produced when any one of the inputs is HIGH (1).
The output is LOW (0) only when all the inputs are LOW (0).
AND (IC7408)Gate:
The AND Gate performs logical multiplication, commonly known as AND function.
IC7408 is a quad 2-input AND function. It has two inputs and only one output. The output of an
AND gate is HIGH only when all the inputs are HIGH. Even if any one of the inputs is LOW,
the output will be LOW.
NOT (IC7404)Gate:
The NOT performs the basic logical function called inversion or complementation.
IC7404 is a hex 1-input NOT function. It has one input and one output. The purpose of this logic
gate is to convert one logic to the opposite logic level. When HIGH input is applied to an inverter,
a LOW output appears at its output and vice versa.
NAND (IC7400)Gate:
NAND gate is a contraction of the NOT-AND gates. IC7400 is a quad 2-input NAND

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function. It has two inputs and only one output. When all the inputs are HIGH, the output is

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LOW. If any one or both the inputs are LOW, then the output is HIGH. The NAND called as
Universal Gate.
NOR(IC7402) Gate:
NOR gate is a contraction of the NOT-OR gates. IC7402 is a quad 2-input NOR function.
It has is a gate with two and one output. When all the inputs are LOW, the output is HIGH. If any
one or both the inputs are HIGH, then the output is LOW. The NOR gate called as Universal
Gate.
EX-OR (IC7486) Gate:
IC7486 is a quad 2-input EX-OR function. The output of a gate is HIGH when odd numbers
of HIGH inputs are applied. If Even number of HIGH inputs or all the inputs are LOW the output
will be LOW.
EX-NOR (IC74266) Gate:
IC74266 is a quad 2-input Ex-NOR function. It is a gate with two and one output. When
all the inputs are LOW or HIGH the output will be HIGH. The output of a gate is LOW when
odd numbers of HIGH inputs are applied.
Procedure

Note: Student should write it on your own with proper meaning and sentence formation

Circuit Diagram
NAND Gate (IC7400)
IC Diagram

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Logic Diagram

Truth Table

A B Y=(A.B)’
0 0
0 1
1 0
1 1

NOR Gate (IC7402)

IC Diagram

Logic Diagram

Truth table

A B Y=(A+B)’
0 0

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0 1
1 0
1 1

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NOT Gate (IC7404)

IC Diagram

Logic Diagram

Truth Table

A Y=A’

AND Gate (IC7408)

IC Diagram

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Logic Diagram

Truth Table

A B Y=A.B
0 0
0 1
1 0
1 1

OR Gate (IC 7432)

IC Diagram

Logic Diagram

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Truth Table

A B Y=A+B
0 0
0 1
1 0
1 1

EX-OR Gate (IC7486)

IC Diagram

Logic Diagram

Truth Table

A B Y=A⊕B
0 0
0 1

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1 0
1 1

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EX-NOR Gate (IC74266)

IC Diagram

Logic Diagram

Truth Table

A B Y=(A⊕B)’
0 0
0 1
1 0
1 1

Conclusion: The testing of logic gates using ICs was done and output was verified by the functionality.

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Exp.No: 2

TESTING OF ADDERS

Aim

: To test and verify the following adders using IC 7486, 7408 & 7432.
➢ Half Adder
➢ Full Adder

Apparatus Required

o ICs: 7486, 7408, 7432

o Patch Cord

Theory

Half Adder:
The half adder is an example of a simple, functional digital circuit built from two logic
gates. The half adder adds to one-bit binary numbers (AB). The output is the sum of the two bits
(S) and the carry (C). Note how the same two inputs are directed to two different gates. The
inputs to the XOR gate are also the inputs to the AND gate. The input "wires" to the XOR gate
are tied to the input wires of the AND gate; thus, when voltage is applied to the A input of the
XOR gate, the A input to the AND gate receives the same voltage.
Sum = A’B + AB’ = A⊕B
Carry = AB

Full Adder:
The full-adder circuit adds three one-bit binary numbers (C A B) and outputs two one-bit
binary numbers, a sum (S) and a carry (C1). The full-adder is usually a component in a cascade
of adders, which add 8, 16, 32, etc. binary numbers. The carry input for the full-adder circuit is
from the carry output from the circuit "above" itself in the cascade. The carry output from the full
adder is fed to another full adder "below" itself in the cascade. If you look closely, you'll see the
full adder is simply two half adders joined by an OR.

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Sum = A⊕B⊕C
Carry = AB + BC + AC

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Procedure
Note: Student should write it on your own with proper meaning and sentence formation

Half Adder
Truthtable
INPUTS OUTPUTS

A B S= A ⊕ B C= A.B

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

K-Map

Note: Student should have to find out the expression of Sum and Carry using Half Adder
truth table
Logic Diagram

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Circuit Diagram

Full Adder Truth table

INPUTS OUTPUTS

a b Cin Sum=a⊕b⊕Cin Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

K-map:

Note: Student should have to find out the expression of Sum and Carry using Full Adder
truthtable

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Logic Diagram

Circuit Diagram

Conclusion

Thus the testing of half adder and full adder using ICs was done and output is verified by
the functionality.

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VIVA QUESTIONS:-

Q1 Draw the logic diagram of half adder and full adder

Q2 What are the different gates and number of gates are required to implement a full adder?
Q3 Can you design a full adder using half adders? If so how many such half adders are
required and what should be the connections?
Q4 If the order of inputs is changed in an adder is there any change will be observed in the
output?
Q5 Can you design a full adder using half adder ICs? What additional logic gates do you
required to implement the above full adder?
Q6 Can a half adder be designed using NAND gates only? If yes, how many such NAND
gates are required to implement a half adder?
Q7 How many NAND gates are required to implement a full adder? How many 74S00N ICs
will be needed for the above implementation?
Q8 Can you use a full adder in place of half adder?
Q9 What are the sum and carry outputs in a full adder if all the inputs are logic high?

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Exp.No: 3

TESTING OF SUBTRACTORS

Aim

To test and verify the following Subtractors using ICs 7486, 7408, 7404, 7432.

➢ Half Subtractor
➢ Full Subtractor

Apparatus Required

o ICs: 7486, 7408, 7432,7404

o Patch Cord

Theory
Half Subtractor:

The half-subtractor is a combinational circuit which is used to perform subtraction of two

bits. It has two inputs, A(minuend) and B (subtrahend) and two outputs D (difference) and B
(borrow).

Difference = A’B + AB’ = A⊕B

Borrow = A’B
Full Subtractor:

As in the case of the addition using logic gates, a full subtractor is made by combining
two half- subtractors and an additional OR-gate. A full subtractor has the borrow in capability

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and so allows cascading which results in the possibility of multi-bit subtraction. The circuit
diagram for a full subtractor is given below.

Difference = A⊕B⊕C
Borrow = A’B + BC + A’C
Procedure

Note: Student should write it on your own with proper meaning and sentence formation

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Half Subtractor

Truth table

INPUTS OUTPUTS

A B Diff= A ⊕ B Bor= A’.B

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

K-Map

Note: Student should have to find out the expression of Difference and Borrow using
Half Subtractor truthtable

Logic Diagram

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Circuit Diagram

Full Subtractor
Truth table

INPUTS OUTPUTS

A B C Diff Bor

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

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1 1 0 0 0

1 1 1 1 1

K-Map

Note: Student should have to find out the expression of Difference and Borrow using Full
Subtractor truthtable
Logic Diagram

Circuit Diagram

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Conclusion

Thus the testing of half subtractor and full subtractor using ICs was done and output was
Verified by the functionality.

Viva Questions:

Q1 Draw the logic diagram of half subtractor and full subtractor.

Q2 What are the different gates and number of gates are required to implement a full
subtractor?
Q3 Can you use a half adder to verify the difference of two inputs? If yes how?

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Q4 How to implement a half subtractor using half adder ICs. If yes which output pin is
required to be modified and how? Is there any benefit of doing so or not?
Q5 Do you expect different output if the order of inputs are changed in a subtractor?
Q6 If yes, any change will be observed in Difference (D) output pin?
Q7 How many minimum number of NOR gates are required to implement a full substractor?

Exp No: 1(a) Date:

DESIGN OF LOGIC GATES

Aim:

To design basic Logic gates (AND Gate, OR Gate, NOT Gate, XOR Gate, XNOR Gate)
using Dataflow modeling.

Tools Required:

Xilinx Software V14.2.

Program:

AND Gate:

module AndGate (A,B,Y);

input A,B;
output Y;
assign Y = A & B;
endmodule

OR Gate:

module ORGate (A, B, Y);

input A, B;
output Y;
assign Y = A | B;
endmodule

NOT Gate:

module NOTGate (A, Y);

input A;
output Y;
assign Y = ~A;
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endmodule

XOR Gate:

module xor1(Y,A,B);
output Y;
input A,B;
assign Y= A^ B;
endmodule

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XNOR Gate:

module xnor1(Y,A,B);
output Y;
input A,B;
assign Y= ~(A^ B);
endmodule

Logic Diagram and Truth Table

AND Gate

Logic Diagram

Truth Table

A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1

OR Gate Logic

Diagram

Truth Table

A B Y=A+B
0 0 0
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0 1 1
1 0 1
1 1 1

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NOT Gate Logic

Diagram

Truth Table

A Y=A’

0 1

1 0

XOR Gate Logic

Diagram

Truth Table

A B Y=A⊕B
0 0 0
0 1 1
1 0 1
1 1 0

XNOR Gate

Logic Diagram

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 Truth Table

A B Y=(A⊕B)’
0 0 1
0 1 0
1 0 0
1 1 1

Result

The design of basic logic gates are done by Data flow modeling and verified the
functionality by simulation.

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 Exp No: 1(b) Date:

DESIGN OF UNIVERSAL GATES

Aim:

To design of Universal Logic Gates (NAND Gate, NOR Gate) using Gate level
modeling.

Tools Required:

Xilinx Software V14.2

Program:

NAND Gate:

module NAND(Y,A,B);
output Y;
input A,B;
nand u1(Y,A,B);
endmodule

NOR Gate:

module NOR(Y,A,B);
output Y;
input A,B;
nor u1(Y,A,B);
endmodule

Logic Diagram and Truth Table

NAND Gate

Logic Diagram

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 Truth Table

A B Y=(A.B)’
0 0 1
0 1 1
1 0 1
1 1 0

NOR Gate Logic

Diagram

Truth Table

A B Y=(A+B)’
0 0 1
0 1 0
1 0 0
1 1 0

Result

The design of universal gates are done by Gate level modeling and verified the
functionality by simulation.

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 Exp No: 2 Date:

DESIGN OF ADDERS

Aim:

To design the following Adders using basic logic gates

➢ Half Adder(HA)

➢ Full Adder(FA)

Tools Required:

Xilinx Software V14.2

Program:

Half Adder

module HA (S, C, A,B);

output S, C;
input A,B;
xor XOR(S, A,B);
and AND(C, A,B);
endmodule

Full Adder

module FA(Sum, Cout, a, b, Cin);

output Sum, Cout;
input a, b, Cin ;
wire s1, c1, c2,c3;
xor XOR1(s1, a, b);
xor XOR2(sum, s1, Cin);
and AND1(c1, a, b);
and AND2(c2, b, Cin);
and AND3(c3,a,Cin);
or OR(Cout, c2, c1,c3);
endmodule

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 Logic Diagram and Truth Table

Half Adder

Logic Diagram

Truth Table

INPUTS OUTPUTS

A B S= A ⊕ B C= A.B

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

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 Full Adder

Logic Diagram

Truth Table

INPUTS OUTPUTS

a b Cin Sum=a⊕b⊕Cin Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Result

The design of adders (Half and Full Adder) are done by Gate level modeling and verified
the functionality by simulation..

DESIGN OF SUBTRACTOR

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 Aim:

To design the following Subtractor using basic logic gates

➢ Half Subtractor (HS)

➢ Full Subtractor (FS)

Tools Required:

Xilinx Software 14.2

Program:

Half Subtractor

module HS(Diff, Bor, A, B);

output Diff, Bor;

input A,B;

wire W;

xor XOR(Diff,A,B);

and AND(Bor,W,B);

not NOT1(W,A);

endmodule

Full Subtractor

module FS( Diff, Bor, A, B, C);

output Diff, Bor;

input A, B, C;

wire W0,W1,W2,W3,W4;

xor XOR1( W0,A,B);

xor XOR2( Diff, C,W0);

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 not NOT( W1,A);

and AND1( w2, B, w1);

and AND2( W3, B,C);

and AND3( W4,C,W1);

or OR1( Bor, W2,W3,W4);

endmodule

Logic Diagram and Truth Table

Half Subtractor

Logic Diagram

Truth Table

INPUTS OUTPUTS

A B Diff= A ⊕ B Bor= A’.B

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

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 F

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 D

Truth Table

INPUTS OUTPUTS

A B C Diff Bor

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

Result

The design of subtractor (Half and Full Subtractor) are done by

Gate level modeling and
verified the functionality by simulation..

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