5368 (Diagramas - Com.br)

5 4 3 2 1
D D
Starload Schematics
Skylake-U
C 2016-02-18 C
REV : A00
B B
A DY : None Installed <Variant Name> A
UMA: UMA only installed Wistron Corporation

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
OPS: DISCRTE OPTIMUS installed Title
Cover Page
Size Document Number Rev
A3
Starload SKL-U A00
Date: Thursday, February 18, 2016 Sheet 1 of 106
5 4 3 2 1
5 4 3 2 1
CHARGER
ISL95521HRZ-T 44
Project code: 4PD07S010001
PCB P/N: 15264 Star lord SKL-U Block Diagram INPUTS
AD+
OUTPUTS
DCBATOUT
BT+
Revision: A00
SYSTEM DC/DC
SY8288CRAC-GP 45
INPUTS OUTPUTS
DDR4
PWR_5V
D Channel A 5V_S5 D
DCBATOUT 5V_AUX_S5
GPU Intel CPU
SODIMM A
12
VRAM(GDDR5) *4 NVDIA
PCIE x 4 Skylake U CPU Core Power
2GB/4GB N16S-GTR
NCP81208MNTXG-GP 46~50
GDDR5 25W 28W (UMA only) DDR4 33
PCIE Lane1~Lane4 NCP81382MNTXG-1-GP
Channel B NCP81382MNTXG-1-GP
GPU BOARD SODIMM B NCP81253MNTBG-GP
13
INPUTS OUTPUTS
SKL PCH-LP DCBATOUT VCC_CORE
HDMI HDMI Level Shifter HDMI 10 USB 2.0/1.1 ports
HDMI V1.4 57
57
DP MUX and Redriver DCBATOUT +VCCGT
6 USB 3.0 ports DCBATOUT +VCCSA_VR
High Definition Audio
PARADE DP/USB 3.0 USB3.0 type c
13.3"/15.6"/17.3" eDP 3 SATA ports Port1
(HD/FHD/UHD) 6 PCIE ports
USB3.0 PS8740B DDR4
USB3.0 LANE4 38
55
Touch panel USB2.0 USB2.0 LANE7
LPC I/F SY8288RAC-GP
51
ACPI 5.0 USB2.0 USB2.0 LANE4 CC38 USB2.0 BBY only
38
APL5338XAI-TRG-GP
INPUTS OUTPUTS
USB3.0 USB3.0 LANE1
C USB3.0 Port2 DCBATOUT
1D2V_S3 C
USB PowerShare 0D675V_S0
USB2.0 USB2.0 LANE1
Power share TI
34
TPS2544RTER SATA M.2 SSD CPU DCDC-V1D00A
AOZ1268QI-02-GP 52
63
USB3.0 USB3.0 LANE3 INPUTS OUTPUTS
USB3.0 Port3 DCBATOUT 1D0V_S5
USB2.0
ROR only 35 USB2.0 LANE2 CardReader LDO-V1D5V
SD 3.0 SD Card Slot S-1339D15-M5001-GP 54
USB2.0 LANE8 USB2.0 x 1
Realtak INPUTS OUTPUTS
7mm HDD SATA
RTS5176E 3D3V_S5 1D5V_S0
Free fall LDO-V1D8V

INT2 Gsensor Sensor Hub PCIE LANE5
PCIe APL5930KAI-TRG-GP 54
USB2.0 LANE9
ST 70 NGFF WLAN INPUTS OUTPUTS
LNG2DMTR I2C ST USB2.0
STM32L151CBU6TR USB2.0 LANE6
USB2.0 3D3V_S5 1D8V_S5
69
G + E-compass 5V/3V S0
ST G5016KD1U 40
LSM303DTR I2C OUTPUTS
IO Board INPUTS
Gyro USB2.0 5V_S5 5V_S0
B
USB2.0 LANE3 USB2.0 Port4 3D3V_S5 3D3V_S0 B
ST
L3GD20TR VCCSTG
M5938ARD1U-GP-U 40
Sensor BD
on Panel side INPUTS OUTPUTS
1D0V_S5 +VCCSTG
Camera (HD/IR)
USB2.0 x 1 VCCST
USB2.0 LANE5
D-MIC TPS22965DSGR-GP-U 40
LPC debug port LPC BUS 55
68
INPUTS OUTPUTS
1D0V_S5 +V1.00U_CPU
HDA
HDA 2CH SPEAKER SYSTEM DC/DC
CODEC (2CH 2W/4ohm) TPS51225RUKR-GP 45
Thermal KBC INPUTS OUTPUTS

NUVOTON SMBUS SMSC Realtek 3D3V_AUX_S5
NCT7718W 26 SPI
MEC1404-NU-GP ALC3253 3D3V_S5
24 27 DCBATOUT PWR_3D3V
Fan Control Flash ROM MIC_IN/GND

PS2 16MB
PWM 26 25
A
Quad Read HP_R/L A
Universal Jack
Int. Touch PAD I2C
FAN Image sensor
<Core Design>
KB
Wistron Corporation
KB transfer board 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
Block Diagram
C Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
(Reserved)
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = CPU #544669 CRB Rev0.52

+VCCST_CPU
1
R419
1KR2J-1-GP
+VCCSTG
+VCCSTG = 1.0 V +VCCSTG = 1.0 V
2
PCH_THERMTRIP#
+VCCSTG
1
EC401
D D
AZ5725-01FDR7G-GP
1
R401 XDP_TMS 1 DY 2
[PECI] and [PROCHOT#] Rb 1KR2J-1-GP EMI DVT1 0210 XDP_TDI 51R2J-2-GP1 DY 2 R421
Impedance control: 50 ohm TP401 CPU1D 4 OF 20 51R2J-2-GP R422
TPAD14-OP-GP XDP_TDO_CPU 1 DY 2
2
1 H_CATERR# D63 SKYLAKE_ULT 51R2J-2-GP R423
CATERR# PH in P.99
[24] H_PECI A54 PECI
499R2F-2-GP 1 R403 2 H_PROCHOT#_R C65 JTAG
[24,44,46] H_PROCHOT# PROCHOT#
PCH_THERMTRIP# C63 PCH_JTAG_TDI 1 2
Ra THERMTRIP#
TPAD14-OP-GP TP402 1SKTOCC# A65 SKTOCC# PROC_TCK B61 XDP_TCLK 51R2J-2-GP R408
CPU MISC D60 XDP_TDI PCH_JTAG_TDO 1 2
PROC_TDI
TPAD14-OP-GP TP405 1XDP_BPM0 C55 BPM#[0] PROC_TDO A61 XDP_TDO_CPU 51R2J-2-GP R409
TPAD14-OP-GP TP406 1XDP_BPM1 D55 BPM#[1] PROC_TMS C60 XDP_TMS PCH_JTAG_TMS 1 2
TPAD14-OP-GP TP407 1XDP_BPM2 B54 BPM#[2] PROC_TRST# B59 XDP_TRST# 51R2J-2-GP R416
TPAD14-OP-GP TP408 1XDP_BPM3 C56 BPM#[3]
XDP_TCK_JTAGX 1 DY 2
1KR2J-1-GP R417
TP403 1 GPP_E3/CPU_GP0 A6 B56 PCH_JTAG_TCK
TPAD14-OP-GP GPP_E3/CPU_GP0 PCH_JTAG_TCK PCH_JTAG_TDI
[24,55] TOUCH_PANEL_INTR# A7 GPP_E7/CPU_GP1 PCH_JTAG_TDI D59
TOUCHPAD_INTR# PCH_JTAG_TDO XDP_TRST# R402 2 51R2J-2-GP
GPP_B4/CPU_GP3
BA5 GPP_B3/CPU_GP2 PCH_JTAG_TDO A56
PCH_JTAG_TMS XDP_TCLK R406
1 DY
TPAD14-OP-GP TP404 1 AY5 GPP_B4/CPU_GP3 PCH_JTAG_TMS C59 1 2 51R2J-2-GP
3D3V_S5_PCH XDP_TRST# PCH_JTAG_TCK R407 2 51R2J-2-GP
R404 CPU_POPIRCOMP PCH_TRST# C61
XDP_TCK_JTAGX
1 DY
2 1 AT16 PROC_POPIRCOMP JTAGX A59
1 DY 2 49D9R2F-GP 2 R412 1 PCH_POPIRCOMP AU16
49D9R2F-GP 2 R413 EDRAM_OPIO_RCOMP H66 PCH_OPIRCOMP
1 OPCE_RCOMP
100KR2J-1-GP 49D9R2F-GP 2 R414 1 EOPIO_RCOMP H65
3D3V_S0 49D9R2F-GP R415 OPC_RCOMP
R405
SKYLAKE-U-GP
C
1 DS3 2
C
100KR2J-1-GP 071.SKYLA.000U
R410
1NON DS3
2
0R2J-2-GP
[24,65] INT_TP#
DS3 D401
RB751V-40H-GP
K A
83.R2004.G8F Add resistor by NON DS3 function
(#543016) PROCHOT# Routing Guidelines
B B
M1,2,3,4,5: <3 inches

M6: 1-11 inches
MCPU: 0.3-1.5 inches
Mt <0.3 mils
Main route(M1+M2+M3+M4+M5+M6+MCPU): 1-12 inches
A <Core Design> A
Wistron Corporation
Title
CPU_(JTAG/CPU SIDE BAND)
A3 A00
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
Main Func = CPU

DDR4 ball type: Interleaved Type
D D
CPU1C 3 OF 20
CPU1B 2 OF 20
SKYLAKE_ULT M_A_DQ32 AY39 SKYLAKE_ULT AN45

M_A_DQ0 [12] M_A_DQ32 M_A_DQ33 DDR0_DQ[32]/DDR1_DQ[0] DDR1_CKN[0] M_B_CLK#0 [13]
[12] M_A_DQ0 AL71 AU53 [12] M_A_DQ33 AW39 AN46
M_A_DQ1 DDR0_DQ[0] DDR0_CKN[0] M_A_CLK#0 [12] M_A_DQ34 DDR0_DQ[33]/DDR1_DQ[1] DDR1_CKN[1] M_B_CLK#1 [13]
[12] M_A_DQ1 AL68 AT53 [12] M_A_DQ34 AY37 AP45
M_A_DQ2 DDR0_DQ[1] DDR0_CKP[0] M_A_CLK0 [12] M_A_DQ35 DDR0_DQ[34]/DDR1_DQ[2] DDR1_CKP[0] M_B_CLK0 [13]
[12] M_A_DQ2 AN68 AU55 [12] M_A_DQ35 AW37 AP46
M_A_DQ3 DDR0_DQ[2] DDR0_CKN[1] M_A_CLK#1 [12] M_A_DQ36 DDR0_DQ[35]/DDR1_DQ[3] DDR1_CKP[1] M_B_CLK1 [13]
[12] M_A_DQ3 AN69
DDR0_DQ[3] DDR0_CKP[1]
AT55
M_A_CLK1 [12] M_A_DQ[32:39][12] M_A_DQ36 BB39
DDR0_DQ[36]/DDR1_DQ[4]
M_A_DQ[0:7] M_A_DQ4 AL70 M_A_DQ37 BA39 AN56
[12] M_A_DQ4 M_A_DQ5 DDR0_DQ[4] [12] M_A_DQ37 M_A_DQ38 DDR0_DQ[37]/DDR1_DQ[5] DDR1_CKE[0] M_B_CKE0 [13]
[12] M_A_DQ5 AL69 BA56 [12] M_A_DQ38 BA37 AP55
M_A_DQ6 DDR0_DQ[5] DDR0_CKE[0] M_A_CKE0 [12] M_A_DQ39 DDR0_DQ[38]/DDR1_DQ[6] DDR1_CKE[1] M_B_CKE1 [13]
[12] M_A_DQ6 AN70 BB56 [12] M_A_DQ39 BB37 AN55
M_A_DQ7 DDR0_DQ[6] DDR0_CKE[1] M_A_CKE1 [12] M_A_DQ40 DDR0_DQ[39]/DDR1_DQ[7] DDR1_CKE[2]
[12] M_A_DQ7 AN71 AW56 [12] M_A_DQ40 AY35 AP53
M_A_DQ8 DDR0_DQ[7] DDR0_CKE[2] M_A_DQ41 DDR0_DQ[40]/DDR1_DQ[8] DDR1_CKE[3]
[12] M_A_DQ8 AR70 AY56 [12] M_A_DQ41 AW35
M_A_DQ9 DDR0_DQ[8] DDR0_CKE[3] M_A_DQ42 DDR0_DQ[41]/DDR1_DQ[9]
[12] M_A_DQ9 AR68 [12] M_A_DQ42 AY33 BB42
M_A_DQ10 DDR0_DQ[9] M_A_DQ43 DDR0_DQ[42]/DDR1_DQ[10] DDR1_CS#[0] M_B_CS#0 [13]
[12] M_A_DQ10 AU71 AU45 [12] M_A_DQ43 AW33 AY42
M_A_DQ11 DDR0_DQ[10] DDR0_CS#[0] M_A_CS#0 [12] M_A_DQ44 DDR0_DQ[43]/DDR1_DQ[11] DDR1_CS#[1] M_B_CS#1 [13]
[12] M_A_DQ11 AU68
DDR0_DQ[11] DDR0_CS#[1]
AU43
M_A_CS#1 [12] M_A_DQ[40:47][12] M_A_DQ44 BB35
DDR0_DQ[44]/DDR1_DQ[12] DDR1_ODT[0]
BA42
M_B_DIMB_ODT0 [13]
M_A_DQ[8:15] M_A_DQ12 AR71 AT45 M_A_DQ45 BA35 AW42
[12] M_A_DQ12 DDR0_DQ[12] DDR0_ODT[0] M_A_DIMA_ODT0 [12] [12] M_A_DQ45 DDR0_DQ[45]/DDR1_DQ[13] DDR1_ODT[1] M_B_DIMB_ODT1 [13]
M_A_DQ13 AR69 AT43 M_A_DQ46 BA33
[12] M_A_DQ13 DDR0_DQ[13] DDR0_ODT[1] M_A_DIMA_ODT1 [12] [12] M_A_DQ46 DDR0_DQ[46]/DDR1_DQ[14]
M_A_DQ14 AU70 M_A_DQ47 BB33 AY48 M_B_A5 M_B_A5 [13]
[12] M_A_DQ14 M_A_DQ15 DDR0_DQ[14] M_A_A5 [12] M_A_DQ47 M_B_DQ32 DDR0_DQ[47]/DDR1_DQ[15] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] M_B_A9
[12] M_A_DQ15 AU69 BA51 M_A_A5 [12] [13] M_B_DQ32 AU40 AP50 M_B_A9 [13]
M_B_DQ0 DDR0_DQ[15] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] M_A_A9 M_B_DQ33 DDR1_DQ[32]/DDR1_DQ[16] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] M_B_A6
[13] M_B_DQ0 AF65 BB54 M_A_A9 [12] [13] M_B_DQ33 AT40 BA48 M_B_A6 [13]
M_B_DQ1 DDR1_DQ[0]/DDR0_DQ[8]DDR0_DQ[16] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] M_A_A6 M_B_DQ34 DDR1_DQ[33]/DDR1_DQ[17] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] M_B_A8
[13] M_B_DQ1 AF64 BA52 M_A_A6 [12] [13] M_B_DQ34 AT37 BB48 M_B_A8 [13]
M_B_DQ2 DDR1_DQ[1]/DDR0_DQ[9]DDR0_DQ[17] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] M_A_A8 M_B_DQ35 DDR1_DQ[34]/DDR1_DQ[18] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] M_B_A7
[13] M_B_DQ2 AK65 AY52 M_A_A8 [12] [13] M_B_DQ35 AU37 AP48 M_B_A7 [13]
M_B_DQ3 DDR1_DQ[2]/DDR0_DQ[10]DDR0_DQ[18] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] M_A_A7 M_B_DQ36 DDR1_DQ[35]/DDR1_DQ[19] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
[13] M_B_DQ3 AK64
DDR1_DQ[3]/DDR0_DQ[11]DDR0_DQ[19] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
AW52 M_A_A7 [12] M_B_DQ[32:39][13] M_B_DQ36 AR40
DDR1_DQ[36]/DDR1_DQ[20] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
AP52 M_B_BG0 [13]
M_B_DQ[0:7] [13] M_B_DQ4 M_B_DQ4 AF66 AY55 [13] M_B_DQ37 M_B_DQ37 AP40 AN50 M_B_A12 M_B_A12 [13]
DDR1_DQ[4]/DDR0_DQ[12]DDR0_DQ[20] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] M_A_BG0 [12] DDR1_DQ[37]/DDR1_DQ[21] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
[13] M_B_DQ5 M_B_DQ5 AF67 AW54 M_A_A12 M_A_A12 [12] [13] M_B_DQ38 M_B_DQ38 AP37 AN48 M_B_A11 M_B_A11 [13]
M_B_DQ6 DDR1_DQ[5]/DDR0_DQ[13]DDR0_DQ[21]DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] M_A_A11 M_B_DQ39 DDR1_DQ[38]/DDR1_DQ[22] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] M_B_ACT_N
[13] M_B_DQ6 AK67 BA54 M_A_A11 [12] [13] M_B_DQ39 AR37 AN53 M_B_ACT_N [13]
M_B_DQ7 DDR1_DQ[6]/DDR0_DQ[14]DDR0_DQ[22]DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] M_B_DQ40 DDR1_DQ[39]/DDR1_DQ[23] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#
[13] M_B_DQ7 AK66 BA55 M_A_ACT_N [12] [13] M_B_DQ40 AT33 AN52 M_B_BG1 [13]
M_B_DQ8 DDR1_DQ[7]/DDR0_DQ[15]DDR0_DQ[23] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# M_B_DQ41 DDR1_DQ[40]/DDR1_DQ[24] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
[13] M_B_DQ8 AF70 AY54 M_A_BG1 [12] [13] M_B_DQ41 AU33
M_B_DQ9 DDR1_DQ[8]/DDR0_DQ[24] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] M_B_DQ42 DDR1_DQ[41]/DDR1_DQ[25] M_B_A13
[13] M_B_DQ9 AF68 [13] M_B_DQ42 AU30 BA43 M_B_A13 [13]
M_B_DQ10 DDR1_DQ[9]/DDR0_DQ[25] M_A_A13 M_B_DQ43 DDR1_DQ[42]/DDR1_DQ[26] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] M_B_A15
[13] M_B_DQ10 AH71 AU46 M_A_A13 [12] [13] M_B_DQ43 AT30 AY43 M_B_A15 [13]
M_B_DQ11 DDR1_DQ[10]/DDR0_DQ[26] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] M_A_A15 M_B_DQ44 DDR1_DQ[43]/DDR1_DQ[27] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] M_B_A14
[13] M_B_DQ11 AH68
DDR1_DQ[11]/DDR0_DQ[27] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]
AU48 M_A_A15 [12] M_B_DQ[40:47][13] M_B_DQ44 AR33
DDR1_DQ[44]/DDR1_DQ[28] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]
AY44 M_B_A14 [13]
M_B_DQ[8:15] [13] M_B_DQ12 M_B_DQ12 AF71 AT46 M_A_A14 M_A_A14 [12] [13] M_B_DQ45 M_B_DQ45 AP33 AW44 M_B_A16 M_B_A16 [13]
M_B_DQ13 DDR1_DQ[12]/DDR0_DQ[28] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] M_A_A16 M_B_DQ46 DDR1_DQ[45]/DDR1_DQ[29] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]
[13] M_B_DQ13 AF69 AU50 M_A_A16 [12] [13] M_B_DQ46 AR30 BB44 M_B_BA0 [13]
M_B_DQ14 DDR1_DQ[13]/DDR0_DQ[29] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] M_B_DQ47 DDR1_DQ[46]/DDR1_DQ[30] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] M_B_A2
[13] M_B_DQ14 AH70 AU52 M_A_BA0 [12] [13] M_B_DQ47 AP30 AY47 M_B_A2 [13]
M_B_DQ15 DDR1_DQ[14]/DDR0_DQ[30] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] M_A_A2 M_A_DQ48 DDR1_DQ[47]/DDR1_DQ[31] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
[13] M_B_DQ15 AH69 AY51 M_A_A2 [12] [12] M_A_DQ48 AY31 BA44 M_B_BA1 [13]
M_A_DQ16 DDR1_DQ[15]/DDR0_DQ[31] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] M_A_DQ49 DDR0_DQ[48]/DDR1_DQ[32] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] M_B_A10
[12] M_A_DQ16 BB65 AT48 M_A_BA1 [12] [12] M_A_DQ49 AW31 AW46 M_B_A10 [13]
M_A_DQ17 DDR0_DQ[16]/DDR0_DQ[32] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] M_A_A10 M_A_DQ50 DDR0_DQ[49]/DDR1_DQ[33] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] M_B_A1
[12] M_A_DQ17 AW65 AT50 M_A_A10 [12] [12] M_A_DQ50 AY29 AY46 M_B_A1 [13]
M_A_DQ18 DDR0_DQ[17]/DDR0_DQ[33] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] M_A_A1 M_A_DQ51 DDR0_DQ[50]/DDR1_DQ[34] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] M_B_A0
C
[12] M_A_DQ18 AW63
DDR0_DQ[18]/DDR0_DQ[34] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
BB50 M_A_A1 [12] M_A_DQ[48:55][12] M_A_DQ51 AW29
DDR0_DQ[51]/DDR1_DQ[35] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
BA46 M_B_A0 [13] C
M_A_DQ[16:23] M_A_DQ19 AY63 AY50 M_A_A0 M_A_DQ52 BB31 BB46 M_B_A3 M_B_A3 [13]
[12] M_A_DQ19 DDR0_DQ[19]/DDR0_DQ[35] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] M_A_A0 [12] [12] M_A_DQ52 DDR0_DQ[52]/DDR1_DQ[36] DDR1_MA[3]
M_A_DQ20 BA65 BA50 M_A_A3 M_A_A3 [12] M_A_DQ53 BA31 BA47 M_B_A4 M_B_A4 [13]
[12] M_A_DQ20 DDR0_DQ[20]/DDR0_DQ[36] DDR0_MA[3] [12] M_A_DQ53 DDR0_DQ[53]/DDR1_DQ[37] DDR1_MA[4]
M_A_DQ21 AY65 BB52 M_A_A4 M_A_A4 [12] M_A_DQ54 BA29
[12] M_A_DQ21 DDR0_DQ[21]/DDR0_DQ[37] DDR0_MA[4] [12] M_A_DQ54 DDR0_DQ[54]/DDR1_DQ[38]
M_A_DQ22 BA63 M_A_DQ55 BB29 BA38 M_A_DQS_DN4
[12] M_A_DQ22 M_A_DQ23 DDR0_DQ[22]/DDR0_DQ[38] M_A_DQS_DN0 [12] M_A_DQ55 M_A_DQ56 DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQSN[4]/DDR1_DQSN[0] M_A_DQS_DP4 M_A_DQS4
[12] M_A_DQ23 BB63 AM70 [12] M_A_DQ56 AY27 AY38
M_A_DQ24 DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQSN[0] M_A_DQS_DP0 M_A_DQS0 M_A_DQ57 DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQSP[4]/DDR1_DQSP[0] M_A_DQS_DN5
[12] M_A_DQ24 BA61 AM69 [12] M_A_DQ57 AW27 AY34
M_A_DQ25 DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQSP[0] M_A_DQS_DN1 M_A_DQ58 DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQSN[5]/DDR1_DQSN[1] M_A_DQS_DP5 M_A_DQS5
[12] M_A_DQ25 AW61 AT69 [12] M_A_DQ58 AY25 BA34
M_A_DQ26 DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQSN[1] M_A_DQS_DP1 M_A_DQS1 M_A_DQ59 DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQSP[5]/DDR1_DQSP[1] M_B_DQS_DN4
[12] M_A_DQ26 BB59
DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQSP[1]
AT70 M_A_DQ[56:63][12] M_A_DQ59 AW25
DDR0_DQ[59]/DDR1_DQ[43] DDR1_DQSN[4]/DDR1_DQSN[2]
AT38
M_A_DQ[24:31] [12] M_A_DQ27
M_A_DQ27 AW59 AH66 M_B_DQS_DN0
[12] M_A_DQ60
M_A_DQ60 BB27 AR38 M_B_DQS_DP4 M_B_DQS4
M_A_DQ28 DDR0_DQ[27]/DDR0_DQ[43] DDR1_DQSN[0]/DDR0_DQ[2] M_B_DQS_DP0 M_A_DQ61 DDR0_DQ[60]/DDR1_DQ[44] DDR1_DQSP[4]/DDR1_DQSP[2] M_B_DQS_DN5
[12] M_A_DQ28 BB61
DDR0_DQ[28]/DDR0_DQ[44] DDR1_DQSP[0]/DDR0_DQ[2]
AH65 M_B_DQS0 [12] M_A_DQ61 BA27
AT32
[12] M_A_DQ29
M_A_DQ29 AY61 AG69 M_B_DQS_DN1
[12] M_A_DQ62
M_A_DQ62 BA25 AR32 M_B_DQS_DP5 M_B_DQS5
M_A_DQ30 DDR0_DQ[29]/DDR0_DQ[45] DDR1_DQSN[1]/DDR0_DQ[3] M_B_DQS_DP1 M_A_DQ63 DDR0_DQ[62]/DDR1_DQ[46] DDR1_DQSP[5]/DDR1_DQSP[3] M_A_DQS_DN6
[12] M_A_DQ30 BA59
DDR0_DQ[30]/DDR0_DQ[46] DDR1_DQSP[1]/DDR0_DQ[3]
AG70 M_B_DQS1 [12] M_A_DQ63 BB25
BA30
[12] M_A_DQ31
M_A_DQ31 AY59 BA64 M_A_DQS_DN2 [13] M_B_DQ48 M_B_DQ48 AU27 AY30 M_A_DQS_DP6 M_A_DQS6
M_B_DQ16 DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQSN[2]/DDR0_DQSN[4] M_A_DQS_DP2 M_A_DQS2 M_B_DQ49 DDR1_DQ[48] DDR0_DQSP[6]/DDR1_DQSP[4] M_A_DQS_DN7 1D2V_S3
[13] M_B_DQ16 AT66 AY64 [13] M_B_DQ49 AT27 AY26
M_B_DQ17 DDR1_DQ[16]/DDR0_DQ[48] DDR0_DQSP[2]/DDR0_DQSP[4] M_A_DQS_DN3 M_B_DQ50 DDR1_DQ[49] DDR0_DQSN[7]/DDR1_DQSN[5] M_A_DQS_DP7 M_A_DQS7
[13] M_B_DQ17 AU66 AY60 [13] M_B_DQ50 AT25 BA26
M_B_DQ18 DDR1_DQ[17]/DDR0_DQ[49] DDR0_DQSN[3]/DDR0_DQSN[5] M_A_DQS_DP3 M_A_DQS3 M_B_DQ51 DDR1_DQ[50] DDR0_DQSP[7]/DDR1_DQSP[5] M_B_DQS_DN6
[13] M_B_DQ18 AP65
DDR1_DQ[18]/DDR0_DQ[50] DDR0_DQSP[3]/DDR0_DQSP[5]
BA60 M_B_DQ[48:55][13] M_B_DQ51 AU25
DDR1_DQ[51] DDR1_DQSN[6]
AR25
1
M_B_DQ[16:23] [13] M_B_DQ19 M_B_DQ19 AN65 AR66 M_B_DQS_DN2 [13] M_B_DQ52 M_B_DQ52 AP27 AR27 M_B_DQS_DP6 M_B_DQS6
DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQ[52] DDR1_DQSP[6]
[13] M_B_DQ20 M_B_DQ20 AN66
AR65 M_B_DQS_DP2 M_B_DQS2 [13] M_B_DQ53 M_B_DQ53 AN27
DDR1_DQ[53] DDR1_DQSN[7]
AR22 M_B_DQS_DN7 R505
[13] M_B_DQ21 M_B_DQ21 AP66 AR61 M_B_DQS_DN3 [13] M_B_DQ54 M_B_DQ54 AN25 AR21 M_B_DQS_DP7 M_B_DQS7 470R2F-GP
DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQ[54] DDR1_DQSP[7]
[13] M_B_DQ22 M_B_DQ22 AT65
AR60 M_B_DQS_DP3 M_B_DQS3 [13] M_B_DQ55 M_B_DQ55 AP25
DDR1_DQ[55]
[13] M_B_DQ23 M_B_DQ23 AU65 [13] M_B_DQ56 M_B_DQ56 AT22 AN43 M_B_ALERT_N [13]
2
M_B_DQ24 DDR1_DQ[23]/DDR0_DQ[55] M_B_DQ57 DDR1_DQ[56] DDR1_ALERT#
[13] M_B_DQ24 AT61 AW50 M_A_ALERT_N [12] [13] M_B_DQ57 AU22 AP43 M_B_PARITY [13]
M_B_DQ25 DDR1_DQ[24]/DDR0_DQ[56] DDR0_ALERT# M_B_DQ58 DDR1_DQ[57] DDR1_PAR SM_DRAMRST#
[13] M_B_DQ25 AU61
DDR1_DQ[25]/DDR0_DQ[57] DDR0_PAR
AT52 M_A_PARITY [12] M_B_DQ[56:63][13] M_B_DQ58 AU21
DDR1_DQ[58] DRAM_RESET#
AT13 1 R504 2 DDR4_DRAMRST# [12,13]
[13] M_B_DQ26 M_B_DQ26 AP60 [13] M_B_DQ59 M_B_DQ59 AT21 AR18 SM_RCOMP_0 1 R501 2 121R2F-GP 0R0402-PAD
M_B_DQ27 DDR1_DQ[26]/DDR0_DQ[58] M_B_DQ60 DDR1_DQ[59] DDR_RCOMP[0] SM_RCOMP_1
M_B_DQ[24:31] [13] M_B_DQ27 AN60
DDR1_DQ[27]/DDR0_DQ[59] DDR_VREF_CA
AY67 V_SM_VREF_CNTA [12] [13] M_B_DQ60 AN22
DDR1_DQ[60] DDR_RCOMP[1]
AT18 1 R502 2 80D6R2F-L-GP
[13] M_B_DQ28 M_B_DQ28 AN61 AY68 [13] M_B_DQ61 M_B_DQ61 AP22 AU18 SM_RCOMP_2 1 R503 2 100R2F-L1-GP-U
M_B_DQ29 DDR1_DQ[28]/DDR0_DQ[60] DDR0_VREF_DQ M_B_DQ62 DDR1_DQ[61] DDR_RCOMP[2]
[13] M_B_DQ29 AP61 BA67 V_SM_VREF_CNTB [13] [13] M_B_DQ62 AP21
M_B_DQ30 DDR1_DQ[29]/DDR0_DQ[61] DDR1_VREF_DQ M_B_DQ63 DDR1_DQ[62]
[13] M_B_DQ30 AT60 [13] M_B_DQ63 AN21 DDR CH - B
2
M_B_DQ31 DDR1_DQ[30]/DDR0_DQ[62] SM_PGCNTL DDR1_DQ[63]
[13] M_B_DQ31 AU60
DDR1_DQ[31]/DDR0_DQ[63] DDR_VTT_CNTL
AW67 #543016
DDR CH - A
SKYLAKE-U-GP
SKYLAKE-U-GP D502
AZ5725-01FDR7G-GP
071.SKYLA.000U 83.05725.0A0
1
071.SKYLA.000U Layout Note:
Design Guideline:
1D2V_S3 3D3V_S0
SM_RCOMP keep routing length less than 500 mils.
DQ Bit Swapping is allowed within the same byte, and Byte Swapping is allowed within the same channel.
Clock (CLK and CLK#) and Strobe (DQS and DQS#) differential signal swapping within a pair is not allowed. Also differential close to CPU
B B
clock pair to clock pair swapping within a channel is not allowed.
1
R506
220KR2F-GP
2
PDG: DDR/ODT SM_PGCNTL S D
SM_PGCNTL_R [51]
Q501
DMN5L06K-7-GP
2015/11/18 Modify
M_A_DQS_DN[7:0] [12] M_B_DQS_DN[7:0] [13]

M_B_DQS_DN0
M_A_DQS_DN0 M_B_DQS_DN1
M_A_DQS_DN7
M_B_DQS_DP[7:0] [13]
M_B_DQS_DP0
M_B_DQS_DP1
M_B_DQS_DP2
M_A_DQS_DP[7:0] [12]
M_A_DQS_DP0 M_B_DQS_DP3
A M_A_DQS_DP4 M_B_DQS_DP7 A
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7
<Core Design>
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Title
CPU_(DDR)
A2 X02
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
CPU1S 19 OF 20
RESERVED SIGNALS-1
D D
TPAD14-OP-GP TP618 1 CFG0 E68 SKYLAKE_ULT BB68 RSVD_TP_BB68 1
TPAD14-OP-GP TP619 CFG1 CFG[0] RSVD_TP_BB68 RSVD_TP_BB69 TP603 TPAD14-OP-GP
1 B67 BB69 1
TPAD14-OP-GP TP620 CFG2 CFG[1] RSVD_TP_BB69 TP604 TPAD14-OP-GP
1 D65
TPAD14-OP-GP TP621 CFG3 CFG[2] RSVD_TP_AK13
1 D67 AK13 1
TPAD14-OP-GP TP622 CFG4 CFG[3] RSVD_TP_AK13 RSVD_TP_AK12 TP605 TPAD14-OP-GP
1 E70 AK12 1
TPAD14-OP-GP TP623 CFG5 CFG[4] RSVD_TP_AK12 TP606 TPAD14-OP-GP
1 C68
TPAD14-OP-GP TP624 CFG6 CFG[5]
1 D68 BB2
TPAD14-OP-GP TP625 CFG7 CFG[6] RSVD_BB2
1 C67 BA3
TPAD14-OP-GP TP626 CFG8 CFG[7] RSVD_BA3
1 F71
1 G69
TPAD14-OP-GP TP628 CFG10 CFG[9] TP5_AU5
1 F70 AU5 1
TPAD14-OP-GP TP629 CFG11 CFG[10] TP5 TP6_AT5 TP607 TPAD14-OP-GP
1 G68 AT5 1
TPAD14-OP-GP TP630 CFG12 CFG[11] TP6 TP608 TPAD14-OP-GP
1 H70
1 G71
1 H69 D5
TPAD14-OP-GP TP633 CFG15 CFG[14] RSVD_D5
1 G70 D4
CFG[15] RSVD_D4
B2
TPAD14-OP-GP TP634 CFG16 RSVD_B2
1 E63 C2
TPAD14-OP-GP TP635 CFG17 CFG[16] RSVD_C2
1 F63
CFG[17]
B3
TPAD14-OP-GP TP636 CFG18 RSVD_B3
1 E66 A3
TPAD14-OP-GP TP637 CFG19 CFG[18] RSVD_A3
1 F66
CFG[19]
AW1
49D9R2F-GP CFG_RCOMP RSVD_AW1
2 1 R601 E60
CFG_RCOMP
E1
TPAD14-OP-GP TP638 ITP_PMODE RSVD_E1
1 E8 E2
ITP_PMODE RSVD_E2
AY2 BA4
RSVD_AY2 RSVD_BA4
AY1 BB4
RSVD_AY1 RSVD_BB4
D1 A4
RSVD_D1 RSVD_A4
D3 C4
RSVD_D3 RSVD_C4
K46 BB5 TP4_BB5 1
RSVD_K46 TP4 TP609 TPAD14-OP-GP
K45
RSVD_K45
A69
RSVD_A69
AL25 B69
RSVD_AL25 RSVD_B69
AL27
RSVD_AL27
AY3
RSVD_AY3
C71
RSVD_C71
C B70 D71 C
RSVD_B70 RSVD_D71
C70
RSVD_C70
F60
RSVD_F60
C54
RSVD_C54
A52 D54
RSVD_A52 RSVD_D54
1 RSVD_TP_BA70 BA70 AY4 TP1_AY4 1
TPAD14-OP-GP TP601 RSVD_TP_BA68 RSVD_TP_BA70 TP1 TP2_BB3 TP610 TPAD14-OP-GP
1 BA68 BB3 1
TPAD14-OP-GP TP602 RSVD_TP_BA68 TP2 TP611 TPAD14-OP-GP
J71 AY71 VSS_AY71 1 R602 2 0R0402-PAD #54469 CRB.
RSVD_J71 VSS_AY71 ZVM#
J68 AR56 ZVM# [40]
RSVD_J68 ZVM#
1 RSVD_F65 F65 AW71 RSVD_TP_AW71 1
TPAD14-OP-GP TP612 RSVD_G65 VSS_F65 RSVD_TP_AW71 RSVD_AW71 RSVD_TP_AW70 TP614 TPAD14-OP-GP +VCCST_CPU
1 G65 AW70 1
TPAD14-OP-GP TP613 VSS_G65 RSVD_TP_AW70 RSVD_AW70 TP615 TPAD14-OP-GP
F61 AP56 MSM# 1
RSVD_F61 MSM# TP617 TPAD14-OP-GP
E61 C64
RSVD_E61 PROC_SELECT#
PROC_SELECT# 1
R603
DY2
SKYLAKE-U-GP 100KR2J-1-GP
PCH strap pin: 071.SKYLA.000U 2016/01/11 modify

CFG3
1
[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

R604
1KR2J-1-GP 0 : ENABLED
DY CFG[3] SET DFX ENABLED BIT IN DEBUG INTERFACE MSR
2
1 : DISABLED
(#543016)
CFG4
1
DISPLAY PORT PRESENCE STRAP

R605
1KR2J-1-GP
0 : ENABLED
CFG[4]
B An external Display Port device is connected to the Embedded Display Port. B
2
1 : DISABLED (Default)
No Physical Display Port attached to Embedded DisplayPort*. No connect for disable.
SKL(#543016):
Processor strap CFG[4] should be pulled low to enable embedded DisplayPort*
A A
<Core Design>
Wistron Corporation
Title
CPU_(RESERVED)
A2 A00
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
CPU1L 12 OF 20 CPU1M 13 OF 20
VCC_CORE VCC_CORE +VCCGT
CPU POWER 1 OF 4
+VCCGT CPU POWER 2 OF 4
A30 G32 N70
VCC_A30 VCC_G32 VCCGT
A34 G33 A48 N71
VCC_A34 SKYLAKE_ULT VCC_G33 VCCGT SKYLAKE_ULT VCCGT 1D2V_S3
A39 G35 A53 R63
VCC_A39 VCC_G35 VCCGT VCCGT
A44 G37 A58 R64
VCC_A44 VCC_G37 VCCGT VCCGT
AK33 G38 A62 R65
VCC_AK33 VCC_G38 VCCGT VCCGT
AK35 G40 A66 R66
AK37 G42 AA63 R67
AK38 J30 AA64 R68
VCC_AK38 VCC_J30 VCCGT VCCGT
AK40 J33 AA66 R69
VCC_AK40 VCC_J33 VCCGT VCCGT
1
AL33 J37 AA67 R70
VCC_AL33 VCC_J37 VCCGT VCCGT C719 +VCCIO
AL37 J40 AA69 R71
VCC_AL37 VCC_J40 VCCGT VCCGT CPU1N 14 OF 20
AL40 K33 AA70 T62 SC1U10V2KX-1GP
2
VCC_AL40 VCC_K33 VCCGT VCCGT +VCCIO(ICCMAX.=2.73A
AM32 K35 AA71 U65 CPU POWER 3 OF 4
VCC_AM32 VCC_K35 VCCGT VCCGT
AM33 K37 AC64 U68
VCC_AM33 VCC_K37 VCCGT VCCGT
AM35 K38 AC65 U71 AU23 AK28
D VCC_AM35 VCC_K38 VCCGT VCCGT VDDQ_AU23 VCCIO D
AM37 K40 AC66 W63 AU28 AK30
VCC_AM37 VCC_K40 VCCGT VCCGT VDDQ_AU28 SKYLAKE_ULT VCCIO
AM38 K42 AC67 W64 AU35 AL30
VCC_AM38 VCC_K42 VCCGT VCCGT VDDQ_AU35 VCCIO
G30 K43 AC68 W65 AU42 AL42
VCC_G30 VCC_K43 VCCGT VCCGT VDDQ_AU42 VCCIO
AC69 W66 BB23 AM28
TPAD14-OP-GP TP701 +VCCCOREG0 VCCGT VCCGT VDDQ_BB23 VCCIO
1 K32 E32 AC70 W67 BB32 AM30
VCCG0 RSVD_K32 VCC_SENSE VCC_SENSE [46] VCCGT VCCGT VDDQ_BB32 VCCIO +VCCSA
E33 AC71 W68 BB41 AM42
TPAD14-OP-GP TP707 +VCCCOREG1 VSS_SENSE VSS_SENSE [46] VCCGT VCCGT VDDQ_BB41 VCCIO
1 AK32 J43 W69 BB47
VCCG1 RSVD_AK32 H_CPU_SVIDALRT# VCCGT VCCGT +VDDQ_CPU_CLK VDDQ_BB47
B63 J45 W70 BB51 AK23
VIDALERT# H_CPU_SVIDCLK VCCGT VCCGT VDDQ_BB51 VCCSA
AB62 A63 J46 W71 AK25
140mA 3A +V_EDRAM_VR
P62
V62
VCCOPC_AB62
VCCOPC_P62
VIDSCK
VIDSOUT
D64 H_CPU_SVIDDAT +VCCSTG J48
J50
VCCGT
VCCGT
VCCGT
VCCGT
Y62 SC10U6D3V3MX-GP2 1 C715
+VCCST_CPU AM40
VCCSA
VCCSA
G23
G25
VCCOPC_V62 +VCCFUSEPRG VCCGT +VCCGT VDDQC VCCSA
G20 1 R703 2 J52 G27
VCCSTG_G20 VCCGT SC1U10V2KX-1GP 2 VCCSA
+V1.8S_EDRAM H63 J53 AK42 1 C716 0.04 A A18 G28
R702 VCC_OPC_1P8_H63 0R0603-PAD VCCGT VCCGTX_AK42 +VCCSTG VCCST VCCSA
J55 AK43 J22
VCC_EDRAM_FUSEPRG VCCGT VCCGTX_AK43 VCCSA
1 23e
0R2J-2-GP
2 G61
VCC_OPC_1P8_G61
J56
VCCGT VCCGTX_AK45
AK45
SC1U10V2KX-1GP 2
A22
VCCSTG_A22 VCCSA
J23
J58 AK46 1 C717 J27
R704 VCCSENSE_EDRAM_VR VCCGT VCCGTX_AK46 VCCSA
VSSSENSE_EDRAM_VR
AC63
VCCOPC_SENSE
J60
VCCGT VCCGTX_AK48
AK48 DY 1D2V_S3
AL23
VCCPLL_OC VCCSA
K23
1 23e 2 AE63
VSSOPC_SENSE
K48
VCCGT VCCGTX_AK50
AK50
VCCSA
K25
K50 AK52 K20 K27
0R2J-2-GP VCCGT VCCGTX_AK52 SCD1U16V2KX-3GP2 VCCPLL_K20 VCCSA
AE62 K52 AK53 1 C718 K21 K28
3A +V_EOPIO_VR
AG62
VCCEOPIO
VCCEOPIO
K53
K55
VCCGT
VCCGT
VCCGTX_AK53
VCCGTX_AK55
AK55
AK56
VCCPLL_K21 VCCSA
VCCSA
K30
VCCSENSE_EOPIO_VR VCCGT VCCGTX_AK56 +VCCSFR

AL63 K56 AK58 AM23
VSSSENSE_EOPIO_VR VCCEOPIO_SENSE VCCGT VCCGTX_AK58 VCCIO_SENSE
AJ62 K58 AK60 AM22
VSSEOPIO_SENSE VCCGT VCCGTX_AK60 VSSIO_SENSE
K60 AK70
VCCGT VCCGTX_AK70
C720
C721
L62
VCCGT VCCGTX_AL43
AL43 #544669 CRB. 0.12 A VSSSA_SENSE
H21 VSSSA_SENSE [46]
1
SKYLAKE-U-GP L63 AL46 H20
VCCGT VCCGTX_AL46 VCCSA_SENSE VCCSA_SENSE [46]
L64 AL50
VCCGT VCCGTX_AL50 1D2V_S3 +VDDQ_CPU_CLK
071.SKYLA.000U L65 AL53
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
2
2
VCCGT VCCGTX_AL53 SKYLAKE-U-GP
L66 AL56
+V_EDRAM_VR VCCGT VCCGTX_AL56 R705
L67 AL60
VCCGT VCCGTX_AL60
L68
VCCGT VCCGTX_AM48
AM48 1 2 071.SKYLA.000U
L69 AM50
VCCGT VCCGTX_AM50 0R0805-PAD
L70 AM52
VCCGT VCCGTX_AM52
C701
C702
L71 AM53
VCCGT VCCGTX_AM53
1
M62 AM56
VCCGT VCCGTX_AM56
23e 23e N63
VCCGT VCCGTX_AM58
AM58
N64 AU58 2016/02/16 modify
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
2
VCCGT VCCGTX_AU58
N66 AU63
VCCGT VCCGTX_AU63
N67 BB57
VCCGT VCCGTX_BB57
N69 BB66
VCCGT VCCGTX_BB66
[46] VCCGT_SENSE J70 AK62
VCCGT_SENSE VCCGTX_SENSE
[46] VSSGT_SENSE J69 AL61
VSSGT_SENSE VSSGTX_SENSE
+V_EOPIO_VR SKYLAKE-U-GP
+V_EDRAM_VR
071.SKYLA.000U
VCC_CORE
C703
C704
1
23e 23e R724

100R2F-L1-GP-U
23e
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
2
1
R719
2
100R2F-L1-GP-U
VCCSENSE_EDRAM_VR
C VSSSENSE_EDRAM_VR C
2
+VCCSA
VCC_SENSE [46]
1
VSS_SENSE [46]
R725
1
100R2F-L1-GP-U
23e
1
R735
R720 Layout Note: 100R2F-L1-GP-U
2
100R2F-L1-GP-U 1. Place close to CPU

2. VCC_SENSE/ VSS_SENSE
2
2
impedance=50 ohm VCCSA_SENSE
+V_EOPIO_VR VSSSA_SENSE
3. Length match<25mil
1
+VCCGT R734
1
100R2F-L1-GP-U
R729
100R2F-L1-GP-U
23e
2
1
R721
2
100R2F-L1-GP-U
VCCSENSE_EOPIO_VR
VSSSENSE_EOPIO_VR
2
VCCGT_SENSE [46]
1
VSSGT_SENSE [46]
R731
100R2F-L1-GP-U
23e
1
R722
2
100R2F-L1-GP-U
2
SVID_543016:
Layout Note:
SVID DATA The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch).
Route the Alert signal between the Clock and the Data signals.
+VCCST_CPU
#544669
1
CLOSE TO CPU
R726
100R2F-L1-GP-U
2
B B
H_CPU_SVIDDAT 1 R709 2 VR_SVID_DATA [46]
0R0402-PAD
+VCCST_CPU
SVID CLOCK #544669

1
CLOSE TO VR
R723
DY 54D9R2F-L1-GP
2
H_CPU_SVIDCLK 1 R732 2 VR_SVID_CLK [46]

0R0402-PAD
+VCCST_CPU
#544669
1
CLOSE TO CPU
R727
56R2J-4-GP
2
R728
H_CPU_SVIDALRT# 2 1 VR_SVID_ALERT# [46]
220R2J-L2-GP
A A
<Core Design>
Wistron Corporation
Title
CPU(VCC_CORE)
A1
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
D D
CPU1A 1 OF 20
E55 SKYLAKE_ULT C47

[57] HDMI_DATA2# DDI1_TXN[0] EDP_TXN[0] EDP_TX0_DN [55]
[57] HDMI_DATA2 F55 DDI1_TXP[0] EDP_TXP[0] C46 EDP_TX0_DP [55]
[57] HDMI_DATA1# E58 DDI1_TXN[1] EDP_TXN[1] D46 EDP_TX1_DN [55]
[57] HDMI_DATA1 F58 DDI1_TXP[1] EDP_TXP[1] C45 EDP_TX1_DP [55]
[57] HDMI_DATA0# F53 A45
HDMI [57] HDMI_DATA0 G53
DDI1_TXN[2]
DDI1_TXP[2]
EDP_TXN[2]
EDP_TXP[2] B45
EDP_TX2_DN
EDP_TX2_DP
[55]
[55]
[57] HDMI_CLK# F56 DDI1_TXN[3] EDP_TXN[3] A47 EDP_TX3_DN [55]
[57] HDMI_CLK G56 DDI1_TXP[3] EDP_TXP[3] B47 EDP_TX3_DP [55]
[38] PCH_DPC_N0 C50 DDI2_TXN[0] DDI EDP_AUXN E45 EDP_AUX_DN [55]

EDP
Dummy, Vendor suggest [38] PCH_DPC_P0 D50 DDI2_TXP[0] EDP_AUXP F45 EDP_AUX_DP [55]
[38] PCH_DPC_N1 C52
20141117 DP and DP to VGA D52
DDI2_TXN[1]
B52 EDP_DISP_UTIL 1
[38] PCH_DPC_P1 DDI2_TXP[1] EDP_DISP_UTIL
[38] PCH_DPC_N2 A50 TP801 TPAD14-OP-GP
DDI2_TXN[2]
[38] PCH_DPC_P2 B50 DDI2_TXP[2] DDI1_AUXN G50
[38] PCH_DPC_N3 D51 DDI2_TXN[3] DDI1_AUXP F50
[38] PCH_DPC_P3 C51 DDI2_TXP[3] DDI2_AUXN E48 DPB_AUXN [38]
3D3V_S0 F48
DDI2_AUXP DPB_AUXP [38]
DDI3_AUXN G46
DISPLAY SIDEBANDS
SRN2K2J-1-GP DDI3_AUXP F46
C L13 C
1 4 CPU_DP1_CTRL_DATA HDMI [57] CPU_DP1_CTRL_CLK
L12
GPP_E18/DDPB_CTRLCLK
L9
2 DY 3 CPU_DP1_CTRL_CLK
[57] CPU_DP1_CTRL_DATA GPP_E19/DDPB_CTRLDATA GPP_E13/DDPB_HPD0
L7 CPU_DP2_HPD CPU_DP1_HPD [57]
CPU_DP2_CTRL_CLK GPP_E14/DDPC_HPD1
N7 GPP_E20/DDPC_CTRLCLK GPP_E15/DDPD_HPD2 L6 SIO_EXT_SMI# [24]
RN801 CPU_DP2_CTRL_DATA N8 N9
GPP_E21/DDPC_CTRLDATA GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD L10 EDP_HPD [55]
Check +VCCIO N11 GPP_E22/DDPD_CTRLCLK
R801 N12 GPP_E23/DDPD_CTRLDATA EDP_BKLTEN R12 L_BKLT_EN [24]
EDP_BKLTCTL R11 L_BKLT_CTRL [55]
3D3V_S0 1 2 EDP_COMP E52 U13
EDP_RCOMP EDP_VDDEN EDP_VDD_EN [55]
RN803 SKYLAKE-U-GP
24D9R2F-L-GP
2 3 CPU_DP2_CTRL_DATA
1 4 CPU_DP2_CTRL_CLK 071.SKYLA.000U
SRN2K2J-1-GP
(#543016) The Skylake U/Y processor supports only two DDI ports - Port 1 and Port 2.
(#543016) eDP_RCOMP Guideline CPU_DP2_HPD R804 1 2 0R2J-2-GP CPU_DP_HPD_R [37,38]

TypeC
Signal Trace Isolation Resistor Length
2
Width Spacing Value
R803
eDP_RCOMP 20 mils 25 mils 24.9 Ω ±1% Max = 100 mils TypeC 100KR2J-1-GP
1
B B
(#543016) DDI Disabling and Termination Guidelines 3D3V_S0

Port Strap Enable Port Disable Port
PU to 3.3 V with 2.2-k
Port 1 DDPB_CTRLDATA ±5% resistor NC SIO_EXT_SMI# 1 R802 2 10KR2J-3-GP
PU to 3.3 V with 2.2-k

Port 2 DDPC_CTRLDATA ±5% resistor NC
A <Core Design> A
Wistron Corporation
Design Guideline:
Skylake processor signal eDP_RCOMP should be connected to the VCCIO rail via a single 24.9 ±1% Ω resistor. Title
CPU_(DISPLAY)
A3 A00
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
Main Func = CPU
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
(Reserved)
A3 A00
Starload SKL-U
5 4 3 2 1
D
A00
Rev
Wistron Corporation
106
of
CPU_(Power CAP1)
10
Sheet
Starload SKL-U
Thursday, February 18, 2016
Document Number
<Core Design>
1
1
Date:
A1
Title
Size
2
2
3
3
EC1001
Do Not Stuff
DY
1 2
EC1007
Do Not Stuff
DY
1 2
2015/10/16 modify (Power team request)

(#543016 PDG)
Remove PC1033 and PC1035 (power team request)

PC1036
PC1057
PC1070
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
DY
DY
1 2 1 2 1 2
PC1056
PC1069
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
EMI reserve , 20141118
EC1004
DY
Do Not Stuff 1 2 1 2
PC1034
PC1055
PC1068
DY
1 2
DY
DY
1 2 1 2 1 2
EC1003
PC1054
PC1001
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
Do Not Stuff
DY
DY
1 2 1 2 1 2
PC1078
SC22U6D3V3MX-1-GP
EC1002
PC1021
PC1032
EC1006
PC1053
PC1067
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
Do Not Stuff Do Not Stuff
1 2
DY
DY
1 2 1 2 1 2 1 2
DY
DY
1 2 1 2
PC1020
PC1031
PC1052
PC1066
PC1077
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
20140814 DAVID
EC1005
1 2 1 2 SC1U10V2KX-1GP 1 2 1 2 1 2
PC1010
PC1019
PC1030
PC1051
PC1065
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP 1 2 SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
PC1076
SC22U6D3V3MX-1-GP
1 2 1 2 1 2 1 2 1 2
1 2
PC1009
PC1018
PC1029
PC1043
PC1050
PC1064
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
PC1075
1 2 1 2 1 2 1 2 1 2 1 2 SC22U6D3V3MX-1-GP
4
4
PC1008
PC1017
PC1028
PC1042
PC1049
PC1063
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP 1 2
IccMax current-10ms max[A] = 67 A

1 2 1 2 1 2 1 2 1 2 1 2
PC1074
SC22U6D3V3MX-1-GP
PC1007
PC1016
PC1027
PC1041
PC1048
PC1062
1 2
IccMax current-10ms max = 34 A
SLICED GT
1 2 1 2 1 2 1 2 1 2 1 2
PC1006
PC1015
PC1026
PC1040
PC1047
PC1061
PC1073
SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP SC22U6D3V3MX-1-GP
22U 0603 x35 (5 DY)

1 2 1 2 1 2 1 2 1 2 1 2 1 2
22U 0603 x 35(5 DY)
PC1005
PC1014
PC1025
PC1039
PC1046
PC1060
22U 0603 x13 (5 DY)
PC1072
SC22U6D3V3MX-1-GP
U-line 23e 28W

1 2 1 2 1 2 1 2 1 2 1 2
1 2
PC1004
PC1013
PC1024
PC1038
PC1045
PC1059
VCCSA
U-line 23e 28W
PC1071
SC22U6D3V3MX-1-GP
CORE
1 2 1 2 1 2 1 2 1 2 1 2
PC1003
PC1012
PC1023
PC1037
PC1044
PC1058
1 2
+VCCSA
1 2 1 2 1 2 1 2 1 2 1 2
PC1002
PC1011
PC1022
1 2 1 2 1 2
+VCCGT
VCC_CORE
5
5
Main Func = CPU
A
5 4 3 2 1
Main Func = CPU
PCH DERIVED RAILS UNSLICED GT VCCIO

+VCCGT +VCCIO
1D0V_S5
+VCCIO(ICCMAX.=2.73A)
D D
1
+VCCPRIM_CORE C1102 C1103 C1104 C1105 C1106 C1107 1U 0402 x 6 C1108 C1109 C1110 C1111
DY DY DY DY DY
1 R1101 2
2
Do Not Stuff
Do Not Stuff
Do Not Stuff
SC1U10V2KX-1GP
Do Not Stuff
SC1U10V2KX-1GP
Do Not Stuff
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
0R1206-PAD
+V1.00A_SIP
1 R1102 2
C1112
SC22U6D3V3MX-1-GP
Dummy : 20150123 Dummy : 20150123

1
0R0603-PAD
DY
2
3D3V_S5_PCH +V3.3A_SIP
1 R1103 2 +VCCMPHYGTAON_1P0(ICCMAX.=2.12A)
C1113
SC22U6D3V3MX-1-GP
C C
1
0R0603-PAD
DY
2
Layout Note:
+VCCMPHYGTAON_1P0_LS_SIP +VCCMPHYGTAON_1P0_LS_SIP +VCCMPHYGTAON_1P0_LS_SIP +VCCMPHYGTAON_1P0_LS_SIP 1uF:
C1174 near N15
C1114
SC1U10V2KX-1GP
C1115
SC22U6D3V3MX-1-GP
C1116
SC1U10V2KX-1GP
C1117
SC1U10V2KX-1GP
C1118
SC22U6D3V3MX-1-GP
C1119
SC1U10V2KX-1GP
C1121
SC1U10V2KX-1GP
C1180 near K15
1
1
+V1.8A +V1.8A_SIP
SC10U6D3V3MX-GP
C1120
C1173 near AF20
R1104 1
DY DY DY C1172 near N18
2
2
2
C1122
SC22U6D3V3MX-1-GP
C1175 near AB19

1
0R0603-PAD
DY 22uF :
C1182 C1184 near N15
2
10uF:
+VCCPRIM_CORE C1176 near N15
+VCCIO
+VCCIO(ICCMAX.=2.73A)
PC1102
PC1103
PC1104
1
B B
DY 1D2V_S3
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
2
1
Do Not Stuff
PC1105
PC1106
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
2
PC1107
PC1108
PC1109
PC1110
PC1111
PC1112
PC1113
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
1
1
PC1114 SC10U6D3V3MX-GP
PC1101 SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
2
2
Size:0805 change to 0603
20141117 Change to 0.1uF at 20150427 for Power team
+V3.3A_SIP PC1115
1
EC1102 EC1103
SC22U6D3V3MX-1-GP
1
SC2D2U10V2KX-GP
SC2D2U10V2KX-GP
VCC_CORE DY DY DY DY
1U 0402 x 5
2
2
Do Not Stuff
Do Not Stuff
2
1
SC10U6D3V3MX-GP
C1123
DY
2
<Core Design>
A A
1
C1124 C1125 C1126 C1101 C1127
Wistron Corporation
2
2
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP

RF request 2016/01/12 modify
Title
CPU_(Power CAP2)
A3
U-line 23e 28W Starload SKL-U A00
IccMax current-10ms max = 34 A Date: Thursday, February 18, 2016 Sheet 11 of 106
5 4 3 2 1
5 4 3 2 1
DM1A 1 OF 4
DM1D 4 OF 4
[5] M_A_A0 144 8 M_A_DQ0 [5]
A0 DQ0 DM1B 2 OF 4
[5] M_A_A1 133 7 M_A_DQ1 [5] 1 99
A1 DQ1 VSS VSS
[5] M_A_A2 132 20 M_A_DQ2 [5] 2 102
A2 DQ2 M_A_DQS_DN0 VSS VSS
[5] M_A_A3 131 21 M_A_DQ3 [5] 11 5 103
A3 DQ3 DQS0_C M_A_DQS_DP0 VSS VSS
[5] M_A_A4 128 4 M_A_DQ4 [5] 13 6 106
A4 DQ4 DQS0_T M_A_DQS_DN1 VSS VSS
[5] M_A_A5 126 3 M_A_DQ5 [5] 32 9 107
[5] M_A_A6 127 16 M_A_DQ6 [5] 34 10 167
[5] M_A_A7 122 17 M_A_DQ7 [5] 53 14 168
[5] M_A_A8 125 28 M_A_DQ8 [5] 55 15 171
[5] M_A_A9 121 29 M_A_DQ9 [5] 74 18 172
[5] M_A_A10 146 41 M_A_DQ10 [5] 76 19 175
A10/AP DQ10 DQS3_T M_A_DQS_DN4 VSS VSS
[5] M_A_A11 120 42 M_A_DQ11 [5] 177 22 176
[5] M_A_A12 119 24 M_A_DQ12 [5] 179 23 180
[5] M_A_A13 158 25 M_A_DQ13 [5] 198 26 181
[5] M_A_A14 151 38 M_A_DQ14 [5] 200 27 184
WE#/A14 DQ14 DQS5_T M_A_DQS_DN6 VSS VSS
[5] M_A_A15 156 37 M_A_DQ15 [5] 219 30 185
CAS#/A15 DQ15 DQS6_C M_A_DQS_DP6 VSS VSS
[5] M_A_A16 152 50 M_A_DQ16 [5] 221 31 188
RAS#/A16 DQ16 DQS6_T M_A_DQS_DN7 VSS VSS
D 49 M_A_DQ17 [5] 240 35 189 D
DQ17 DQS7_C M_A_DQS_DP7 VSS VSS
[5] M_A_BA0 150 62 M_A_DQ18 [5] 242 36 192
BA0 DQ18 DQS7_T 1D2V_S3 VSS VSS
[5] M_A_BA1 145 63 M_A_DQ19 [5] 95 39 193
BA1 DQ19 DQS8_C VSS VSS
[5] M_A_BG0 115 46 M_A_DQ20 [5] 97 40 196
BG0 DQ20 DQS8_T VSS VSS
[5] M_A_BG1 113 45 M_A_DQ21 [5] 43 197
BG1 DQ21 VSS VSS
58 M_A_DQ22 [5] 12 44 201
DQ22 DM0#/DBI0# VSS VSS
92 59 M_A_DQ23 [5] 33 47 202
CB0/NC DQ23 DM1#/DBI# VSS VSS
91 70 M_A_DQ24 [5] 54 48 205
CB1/NC DQ24 DM2#/DBI2# VSS VSS
101 71 M_A_DQ25 [5] 75 51 206
105 83 M_A_DQ26 [5] 178 52 209
88 84 M_A_DQ27 [5] 199 56 210
87 66 M_A_DQ28 [5] 220 57 213
100 67 M_A_DQ29 [5] 241 60 214
104 79 M_A_DQ30 [5] 96 61 217
CB7/NC DQ30 DM8#/DBI#/NC VSS VSS
80 M_A_DQ31 [5] 64 218
DQ31 VSS VSS
[5] M_A_CLK0 137 174 M_A_DQ32 [5] 65 222
CK0_T DQ32 DDR4-260P-24-GP VSS VSS
[5] M_A_CLK#0 139 173 M_A_DQ33 [5] 68 223
CK0_C DQ33 3D3V_S0 VSS VSS
[5] M_A_CLK1 138 187 M_A_DQ34 [5] 69 226
CK1_T/NF DQ34 1D2V_S3 DM1C 3 OF 4 VSS VSS
[5] M_A_CLK#1 140 186 M_A_DQ35 [5] 72 227
CK1_C/NF DQ35 VSS VSS
170 M_A_DQ36 [5] 73 230
DQ36 VSS VSS
[5] M_A_CKE0 109 169 M_A_DQ37 [5] 111 255 77 231
CKE0 DQ37 VDD VDDSPD VSS VSS
[5] M_A_CKE1 110 183 M_A_DQ38 [5] 112 78 234
CKE1 DQ38 VDD 2D5V_S3 VSS VSS
182 M_A_DQ39 [5] 117 81 235
DQ39 VDD VSS VSS
[5] M_A_CS#0 149 195 M_A_DQ40 [5] 118 257 82 238
1
CS0# DQ40 VDD VPP C1228 R1216 VSS VSS
[5] M_A_CS#1 157 194 M_A_DQ41 [5] 123 259 85 239
CS1# DQ41 VDD VPP VSS VSS
SCD1U16V2KX-L-GP
SC2D2U10V3KX-L-GP
162 207 M_A_DQ42 [5] 124 86 243
C0/CS2#/NC DQ42 VDD VSS VSS
165 208 M_A_DQ43 [5] 129 258 0D6V_S0 DY DY 89 244
2
C1/CS3#/NC DQ43 VDD VTT VSS VSS
191 M_A_DQ44 [5] 130 90 247
DQ44 VDD VSS VSS
[5] M_A_DIMA_ODT0 155 190 M_A_DQ45 [5] 135 93 248
ODT0 DQ45 VDD VSS VSS
[5] M_A_DIMA_ODT1 161 203 M_A_DQ46 [5] 136 94 251
ODT1 DQ46 VDD VSS VSS
204 M_A_DQ47 [5] 141 98 252
SA0_CHA_DIM0 DQ47 VDD VSS VSS
256 216 M_A_DQ48 [5] 142
SA1_CHA_DIM0 SA0 DQ48 VDD
260 215 M_A_DQ49 [5] 147 261
SA2_CHA_DIM0 SA1 DQ49 VDD 261 DDR4-260P-24-GP
166 228 M_A_DQ50 [5] 148 262
SA2 DQ50 VDD 262
229 M_A_DQ51 [5] 153
DQ51 VDD
[13,18] PCH_SMBDATA 254 211 M_A_DQ52 [5] 154
SDA DQ52 VDD
[13,18] PCH_SMBCLK 253 212 M_A_DQ53 [5] 159 NP1
SCL DQ53 VDD NP1
224 M_A_DQ54 [5] 160 NP2
DQ54 VDD NP2
225 M_A_DQ55 [5] 163
DQ55 VDD
[5,13] DDR4_DRAMRST# 108 237 M_A_DQ56 [5]
1D2V_S3 RESET# DQ56
[5] M_A_ACT_N 114
ACT# DQ57
236 M_A_DQ57 [5] DDR4-260P-24-GP
UN 0225
C
[5] M_A_ALERT_N 116 249 M_A_DQ58 [5]
C
TS#_DIMM0_1 ALERT# DQ58
1 DY 2 134
EVENT#/NF DQ59
250 M_A_DQ59 [5] 0D6V_S0 0D6V_S0
R1215 240R2F-1-GP 232
DQ60 M_A_DQ60 [5] 0D6V_S0
[5] M_A_PARITY 143 233 M_A_DQ61 [5]
DDR4_DRAMRST# PARITY DQ61
245 M_A_DQ62 [5]
M_VREF_CA_DIMMA DQ62
164 246 M_A_DQ63 [5]
VREFCA DQ63
1
1
ED1217 DDR4-260P-24-GP C1225 C1226
1
C1229 1D2V_S3 C1223 C1230 C1224 C1227

AZ5725-01FDR7G-GP DY
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
DDR4 SWAP 0212
跟sw確確
062.10011.00U1
2
SCD1U16V2KX-3GP
DY
2
2
1
3D3V_S0 C1208 C1202 C1209 C1203 C1204 C1205 C1206 C1210
Layout note: closed to Dimm DY DY
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
2
2
2 R1204 DY
1 10KR2F-L1-GP SA0_CHA_DIM0
2 R1205 1
1D2V_S3
for placement modifu 2015/10/19
0R0402-PAD
2D5V_S3
RN1201 R1206
1 4 3D3V_S0
2 3 M_VREF_CA_DIMMA 1 2 V_SM_VREF_CNTA [5]
1
C1214 C1215 C1216 C1217 C1218 C1219 C1220 C1221 EC1202
1
SC2D2U10V2KX-GP
SRN1KJ-7-GP 2R2F-GP 2 R1208 1 10KR2F-L1-GP
DY SA1_CHA_DIM0 DY
1
1
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C1222 C1211 C1231 DY C1232 C1212 C1207 C1213
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
SCD022U16V2KX-3GP 2 R1210 1 DY DY DY
SC1U10V2KX-1GP
SC1U10V2KX-L1-GP
0R0402-PAD
2
2
SC4D7U6D3V2MX-1-GP
+V_VREF_PATH1
1
R1209
24D9R2F-L-GP 3D3V_S0

2
B 2 R1211 1 10KR2F-L1-GP
DY SA2_CHA_DIM0 B
2 R1212 1 M_A_DQS_DN[7:0] [5]

0R0402-PAD M_A_DQS_DN0
M_A_DQS_DN1
M_A_DQS_DN2
M_A_DQS_DN3
M_A_DQS_DN4
M_A_DQS_DN5
M_A_DQS_DN6
M_A_DQS_DN7
M_A_DQS_DP[7:0] [5]
M_A_DQS_DP0
M_A_DQS_DP1
M_A_DQS_DP2
M_A_DQS_DP3
M_A_DQS_DP4
M_A_DQS_DP5
M_A_DQS_DP6
M_A_DQS_DP7
A A
<Core Design>
Wistron Corporation
Title
DDR3-SODIMM1
A2
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
By layou modify 20150916 3D3V_S0

DM2A 1 OF 4
144 8 1D2V_S3
[5] M_B_A0 A0 DQ0 M_B_DQ8 [5]
[5] M_B_A1 133 7 M_B_DQ9 [5] DM2C 3 OF 4 DM2D 4 OF 4
A1 DQ1
[5] M_B_A2 132 20 M_B_DQ10 [5]
A2 DQ2
[5] M_B_A3 131 21 M_B_DQ11 [5] 111 255 1 99
A3 DQ3 VDD VDDSPD VSS VSS
[5] M_B_A4 128 4 M_B_DQ12 [5] 112 2 102
A4 DQ4 VDD 2D5V_S3 VSS VSS
[5] M_B_A5 126 3 M_B_DQ13 [5] 117 5 103
A5 DQ5 VDD VSS VSS
[5] M_B_A6 127 16 M_B_DQ14 [5] 118 257 6 106
A6 DQ6 VDD VPP VSS VSS
1
[5] M_B_A7 122 17 M_B_DQ15 [5] 123 259 C1329 C1328 DY 9 107
A7 DQ7 VDD VPP 0D6V_S0 DY VSS VSS
SC2D2U10V3KX-L-GP
SCD1U16V2KX-L-GP
[5] M_B_A8 125 28 M_B_DQ0 [5] 124 10 167
A8 DQ8 VDD VSS VSS
[5] M_B_A9 121 29 M_B_DQ1 [5] 129 258 14 168
2
A9 DQ9 VDD VTT VSS VSS
[5] M_B_A10 146 41 M_B_DQ2 [5] 130 15 171
A10/AP DQ10 VDD VSS VSS
[5] M_B_A11 120 42 M_B_DQ3 [5] 135 18 172
A11 DQ11 VDD VSS VSS
[5] M_B_A12 119 24 M_B_DQ4 [5] 136 19 175
[5] M_B_A13 158 25 M_B_DQ5 [5] 141 22 176
[5] M_B_A14 151 38 M_B_DQ6 [5] 142 23 180
WE#/A14 DQ14 VDD VSS VSS
[5] M_B_A15 156 37 M_B_DQ7 [5] 147 261 26 181
CAS#/A15 DQ15 VDD 261 VSS VSS
D [5] M_B_A16 152 50 M_B_DQ16 [5] 148 262 27 184 D
RAS#/A16 DQ16 VDD 262 VSS VSS
49 M_B_DQ17 [5] 153 30 185
DQ17 VDD VSS VSS
[5] M_B_BA0 150 62 M_B_DQ18 [5] 154 31 188
BA0 DQ18 VDD VSS VSS
[5] M_B_BA1 145 63 M_B_DQ19 [5] 159 NP1 35 189
BA1 DQ19 VDD NP1 VSS VSS
[5] M_B_BG0 115 46 M_B_DQ20 [5] 160 NP2 36 192
BG0 DQ20 VDD NP2 VSS VSS
[5] M_B_BG1 113 45 M_B_DQ21 [5] 163 39 193
BG1 DQ21 VDD VSS VSS
58 M_B_DQ22 [5] 40 196
DQ22 VSS VSS
92 59 M_B_DQ23 [5] 43 197
CB0/NC DQ23 DDR4-260P-23-GP VSS VSS
91 70 M_B_DQ24 [5] 44 201
CB1/NC DQ24 VSS VSS
101 71 M_B_DQ25 [5] 47 202
CB2/NC DQ25 VSS VSS
105 83 M_B_DQ26 [5] 48 205
CB3/NC DQ26 VSS VSS
88 84 M_B_DQ27 [5] 51 206
CB4/NC DQ27 VSS VSS
87 66 M_B_DQ28 [5] 52 209
CB5/NC DQ28 VSS VSS
100
CB6/NC DQ29
67 M_B_DQ29 [5] By layou modify 20150916 56
VSS VSS
210
104 79 M_B_DQ30 [5] 57 213
CB7/NC DQ30 DM2B 2 OF 4 VSS VSS
80 M_B_DQ31 [5] 60 214
DQ31 VSS VSS
[5] M_B_CLK0 137 174 M_B_DQ32 [5] 61 217
CK0_T DQ32 M_B_DQS_DN1 VSS VSS
[5] M_B_CLK#0 139 173 M_B_DQ33 [5] 11 M_B_DQS_DN1 [5] 64 218
CK0_C DQ33 DQS0_C M_B_DQS_DP1 VSS VSS
[5] M_B_CLK1 138 187 M_B_DQ34 [5] 13 M_B_DQS_DP1 [5] 65 222
CK1_T/NF DQ34 DQS0_T M_B_DQS_DN0 VSS VSS
[5] M_B_CLK#1 140 186 M_B_DQ35 [5] 32 M_B_DQS_DN0 [5] 68 223
CK1_C/NF DQ35 DQS1_C M_B_DQS_DP0 VSS VSS
170 M_B_DQ36 [5] 34 M_B_DQS_DP0 [5] 69 226
DQ36 DQS1_T M_B_DQS_DN2 VSS VSS
[5] M_B_CKE0 109 169 M_B_DQ37 [5] 53 M_B_DQS_DN2 [5] 72 227
CKE0 DQ37 DQS2_C M_B_DQS_DP2 VSS VSS
[5] M_B_CKE1 110 183 M_B_DQ38 [5] 55 M_B_DQS_DP2 [5] 73 230
CKE1 DQ38 DQS2_T M_B_DQS_DN3 VSS VSS
182 M_B_DQ39 [5] 74 M_B_DQS_DN3 [5] 77 231
DQ39 DQS3_C M_B_DQS_DP3 VSS VSS
[5] M_B_CS#0 149 195 M_B_DQ40 [5] 76 M_B_DQS_DP3 [5] 78 234
CS0# DQ40 DQS3_T M_B_DQS_DN4 VSS VSS
[5] M_B_CS#1 157 194 M_B_DQ41 [5] 177 M_B_DQS_DN4 [5] 81 235
CS1# DQ41 DQS4_C M_B_DQS_DP4 VSS VSS
162 207 M_B_DQ42 [5] 179 M_B_DQS_DP4 [5] 82 238
C0/CS2#/NC DQ42 DQS4_T M_B_DQS_DN5 VSS VSS
165 208 M_B_DQ43 [5] 198 M_B_DQS_DN5 [5] 85 239
C1/CS3#/NC DQ43 DQS5_C M_B_DQS_DP5 VSS VSS
191 M_B_DQ44 [5] 200 M_B_DQS_DP5 [5] 86 243
DQ44 DQS5_T M_B_DQS_DN6 VSS VSS
[5] M_B_DIMB_ODT0 155 190 M_B_DQ45 [5] 219 M_B_DQS_DN6 [5] 89 244
ODT0 DQ45 DQS6_C M_B_DQS_DP6 VSS VSS
[5] M_B_DIMB_ODT1 161 203 M_B_DQ46 [5] 221 M_B_DQS_DP6 [5] 90 247
ODT1 DQ46 DQS6_T M_B_DQS_DN7 VSS VSS
204 M_B_DQ47 [5] 240 M_B_DQS_DN7 [5] 93 248
SA0_CHB_DIM0 DQ47 DQS7_C M_B_DQS_DP7 VSS VSS
256 216 M_B_DQ48 [5] 242 M_B_DQS_DP7 [5] 94 251
SA1_CHB_DIM0 SA0 DQ48 DQS7_T VSS VSS
260 215 M_B_DQ49 [5] 95 98 252
SA2_CHB_DIM0 SA1 DQ49 DQS8_C 1D2V_S3 VSS VSS
166 228 M_B_DQ50 [5] 97
SA2 DQ50 DQS8_T
229 M_B_DQ51 [5]
DQ51 DDR4-260P-23-GP
[12,18] PCH_SMBDATA 254 211 M_B_DQ52 [5] 12
SDA DQ52 DM0#/DBI0#
[12,18] PCH_SMBCLK 253 212 M_B_DQ53 [5] 33
SCL DQ53 DM1#/DBI#
224 M_B_DQ54 [5] 54
DQ54 DM2#/DBI2#
225 M_B_DQ55 [5] 75
DQ55 DM3#/DBI3#
[5,12] DDR4_DRAMRST# 108 237 M_B_DQ56 [5] 178
1D2V_S3 RESET# DQ56 DM4#/DBI4#
C
[5] M_B_ACT_N 114 236 M_B_DQ57 [5] 199 C
ACT# DQ57 DM5#/DBI5#
[5] M_B_ALERT_N 116
ALERT# DQ58
249 M_B_DQ58 [5] DM6#/DBI6#
220 UN 0225
1 R1312 2 TS#_DIMM1_1 134 250 M_B_DQ59 [5] 241
EVENT#/NF DQ59 DM7#/DBI7#
DY 240R2F-1-GP DQ60
232 M_B_DQ60 [5] DM8#/DBI#/NC
96
[5] M_B_PARITY 143 233 M_B_DQ61 [5]
PARITY DQ61 0D6V_S0 0D6V_S0 0D6V_S0 2D5V_S3
245 M_B_DQ62 [5]
M_VREF_CA_DIMMB DQ62 DDR4-260P-23-GP
164 246 M_B_DQ63 [5]
VREFCA DQ63
跟sw確確
DDR4-260P-23-GP
DDR4 SWAP 0212
1
1
C1301 1D2V_S3 C1312 C1313 C1314
062.10011.00T1
1
DDR4_DRAMRST# C1324 C1325 C1311 C1330 DY C1331 DY DY
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
SCD1U16V2KX-3GP
SC1U10V2KX-1GP
SC1U10V2KX-L1-GP
C1326 C1327
2
2
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC4D7U6D3V2MX-1-GP
SC4D7U6D3V2MX-1-GP
DY
2
1
3D3V_S0
SC1U10V2KX-1GP
SC1U10V2KX-1GP
2
2
ED1302
AZ5725-01FDR7G-GP DY
1
2 R1302 110KR2F-L1-GP SA0_CHB_DIM0 C1303 C1304 C1305 C1306 C1307 C1308 C1309 C1310
DY DY DY
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
2 R1303 1
2
2
0R0402-PAD
Layout note: closed to Dimm 3D3V_S0
2 R1306 1 10KR2F-2-GP SA1_CHB_DIM0 EC1303

1
1
C1315 C1316 C1317 C1318 C1319 C1320 C1321 C1322
SC2D2U10V2KX-GP
2 R1307DY
1 0R2J-L-GP M_B_DQS_DN[7:0] [5]
1
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
DY M_B_DQS_DN0
2
2
M_B_DQS_DN1
M_B_DQS_DN2
2
M_B_DQS_DN3
3D3V_S0 M_B_DQS_DN4
M_B_DQS_DN5
1D2V_S3 M_B_DQS_DN6
DY
2 R1310 110KR2F-L1-GP SA2_CHB_DIM0 M_B_DQS_DN7
RN1301 R1305 2 R1311 1 M_B_DQS_DP[7:0] [5]

1 4 M_B_DQS_DP0
B 2 3 M_VREF_CA_DIMMB 1 2 0R0402-PAD RF request 2016/01/12 modify M_B_DQS_DP1 B
V_SM_VREF_CNTB [5] M_B_DQS_DP2
SRN1KJ-7-GP 2R2F-GP 3D3V_S5 M_B_DQS_DP3
1
C1323 M_B_DQS_DP4
SCD022U16V2KX-3GP M_B_DQS_DP5
EC1302 M_B_DQS_DP6
2
1
SC2D2U10V2KX-GP
DY M_B_DQS_DP7
+V_VREF_PATH2
1
R1309
2
24D9R2F-L-GP
2
A A
<Core Design>
Wistron Corporation
Title
DDR3-SODIMM1
A2
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
C
(Blanking) C
B B
<Core Design>
A
Wistron Corporation A
Title
(Reserved)_SODIMM _SODIMM4
A4 A00
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
Main Func = PCH

3D3V_S0
R1503
CPU1I 9 OF 20 W IFI_RF_EN 2 DY 1
CSI-2 SKYLAKE_ULT 10KR2J-3-GP
A36 CSI2_DN0 CSI2_CLKN0 C37

B36 CSI2_DP0 CSI2_CLKP0 D37
D C38 C32 Change to Dummy 20150402 D
CSI2_DN1 CSI2_CLKN1
D38 CSI2_DP1 CSI2_CLKP1 D32
C36 CSI2_DN2 CSI2_CLKN2 C29
D36 CSI2_DP2 CSI2_CLKP2 D29 DC resistance < 0.5ohm.
A38 CSI2_DN3 CSI2_CLKN3 B26
B38 CSI2_DP3 CSI2_CLKP3 A26
C31 E13 CSI2_COMP 1 R1501 2 100R2F-L1-GP-U

CSI2_DN4 CSI2_COMP
D31 CSI2_DP4 GPP_D4/FLASHTRIG B7 W IFI_RF_EN [66]
C33 CSI2_DN5
D33 CSI2_DP5 EMMC
A31 CSI2_DN6
B31 CSI2_DP6 GPP_F13/EMMC_DATA0 AP2
A33 CSI2_DN7 GPP_F14/EMMC_DATA1 AP1 [#545659 Rev0.7]
B33 CSI2_DP7 GPP_F15/EMMC_DATA2 AP3
GPP_F16/EMMC_DATA3 AN3 GPP_F: VCCPGPPF = 1.8V Only
A29 CSI2_DN8 GPP_F17/EMMC_DATA4 AN1
B29 CSI2_DP8 GPP_F18/EMMC_DATA5 AN2
C28 CSI2_DN9 GPP_F19/EMMC_DATA6 AM4
D28 CSI2_DP9 GPP_F20/EMMC_DATA7 AM1
A27 CSI2_DN10
B27 CSI2_DP10 GPP_F21/EMMC_RCLK AM2
C27 CSI2_DN11 GPP_F22/EMMC_CLK AM3
D27 CSI2_DP11 GPP_F12/EMMC_CMD AP4 R1502
AT1 EMMC_RCOMP 1 2
EMMC_RCOMP
SKYLAKE-U-GP 200R2F-L-GP
C C
071.SKYLA.000U
B B
A <Core Design> A
Wistron Corporation
Title
CPU_(CS-2/EMMC)
A3 A00
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
Main Func = PCH

#543016:
CPU1H 8 OF 20
220 nF nominal capacitors are recommended for Gen 3.
100 nF nominal capacitors are recommended for Gen 2. SKYLAKE_ULT
SSIC / USB3
PCIE/USB3/SATA
USB3_1_RXN
H8
USB30_RX_CPU_N1 [36]
(#545659) The xHCI controller supports USB Debug port on all USB3.0 capable ports.
G8
USB3_1_RXP USB30_RX_CPU_P1 [36]
[66] CPU_RXN_C_dGPU_TXN0 H13 C13 USB30_TX_CPU_N1 [36]
SCD22U10V2KX-1GP PCIE1_RXN/USB3_5_RXN USB3_1_TXN
[66] CPU_RXP_C_dGPU_TXP0 G13 D13 USB30_TX_CPU_P1 [36]
C1606 1 PEG_TX_CPU_N0 PCIE1_RXP/USB3_5_RXP USB3_1_TXP
[66] dGPU_RXN_C_CPU_TXN0 2OPS B17
C1605 1 PEG_TX_CPU_P0 PCIE1_TXN/USB3_5_TXN
[66] dGPU_RXP_C_CPU_TXP0 2OPS A17 J6
SCD22U10V2KX-1GP PCIE1_TXP/USB3_5_TXP USB3_2_RXN/SSIC_1_RXN USB30_RX_CPU_N2 [36]
H6
USB3_2_RXP/SSIC_1_RXP USB30_RX_CPU_P2 [36]
[66] CPU_RXN_C_dGPU_TXN1 G11 B13 USB30_TX_CPU_N2 [36]
SCD22U10V2KX-1GP PCIE2_RXN/USB3_6_RXN USB3_2_TXN/SSIC_1_TXN
[66] CPU_RXP_C_dGPU_TXP1 F11 A13 USB30_TX_CPU_P2 [36]
C1608 1 PEG_TX_CPU_N1 PCIE2_RXP/USB3_6_RXP USB3_2_TXP/SSIC_1_TXP
[66] dGPU_RXN_C_CPU_TXN1 2OPS D16
C1607 1 PEG_TX_CPU_P1 PCIE2_TXN/USB3_6_TXN
[66] dGPU_RXP_C_CPU_TXP1 2OPS C16 J10
SCD22U10V2KX-1GP PCIE2_TXP/USB3_6_TXP USB3_3_RXN/SSIC_2_RXN
H10
USB3_3_RXP/SSIC_2_RXP
GPU [66] CPU_RXN_C_dGPU_TXN2 H16
PCIE3_RXN USB3_3_TXN/SSIC_2_TXN
B15 Cutomer remove IO board USB3.0
[66] CPU_RXP_C_dGPU_TXP2 SCD22U10V2KX-1GP G16 A15
C1610 1 PEG_TX_CPU_N2 PCIE3_RXP USB3_3_TXP/SSIC_2_TXP
[66] dGPU_RXN_C_CPU_TXN2 2OPS D17
C1609 1 PEG_TX_CPU_P2 PCIE3_TXN
[66] dGPU_RXP_C_CPU_TXP2 2OPS C17 E10
SCD22U10V2KX-1GP PCIE3_TXP USB3_4_RXN USB30_RX_CPU_N4 [38]
F10
USB3_4_RXP USB30_RX_CPU_P4 [38]
[66] CPU_RXN_C_dGPU_TXN3 G15 C15 USB30_TX_CPU_N4 [38]
D SCD22U10V2KX-1GP PCIE4_RXN USB3_4_TXN D
[66] CPU_RXP_C_dGPU_TXP3 F15 D15 USB30_TX_CPU_P4 [38]
C1612 1 PEG_TX_CPU_N3 PCIE4_RXP USB3_4_TXP
[66] dGPU_RXN_C_CPU_TXN3 2OPS B19
C1611 1 PEG_TX_CPU_P3 PCIE4_TXN
[66] dGPU_RXP_C_CPU_TXP3 2OPS A19 AB9 USB_CPU_PN0 [34]
SCD22U10V2KX-1GP PCIE4_TXP USB2N_1
USB2P_1
AB10 USB_CPU_PP0 [34] USB3.0 port1
[66] PCIE_RX_CPU_N5 F16
SCD1U16V2KX-3GP PCIE5_RXN
[66] PCIE_RX_CPU_P5 E16 AD6 USB_CPU_PN1 [36]
C1601 1 PCIE_TX_CPU_N5 PCIE5_RXP USB2N_2
WLAN [66] PCIE_TX_WLAN_N5 2 C19
PCIE5_TXN USB2P_2
AD7 USB_CPU_PP1 [36] USB3.0 port2
[66] PCIE_TX_WLAN_P5 C1602 1 2 PCIE_TX_CPU_P5 D19
SCD1U16V2KX-3GP PCIE5_TXP
AH3 USB_CPU_PN2 [66]
USB2N_3
G18
PCIE6_RXN USB2P_3
AJ3 USB_CPU_PP2 [66] USB3.0 port3
F18
PCIE6_RXP
TBD
D20 AD9 USB_CPU_PN3 [38]
PCIE6_TXN USB2N_4
C20
PCIE6_TXP USB2P_4
AD10 USB_CPU_PP3 [38] Type C
[60] SATA_RX_CPU_N0 F20 AJ1 USB_CPU_PN4 [55]
PCIE7_RXN/SATA0_RXN USB2N_5
HDD1 [60] SATA_RX_CPU_P0 E20
PCIE7_RXP/SATA0_RXP USB2P_5
AJ2 USB_CPU_PP4 [55] CAMERA
[60] SATA_TX_CPU_N0 B21 USB2
PCIE7_TXN/SATA0_TXN
[60] SATA_TX_CPU_P0 A21 AF6 USB_CPU_PN5 [66]
PCIE7_TXP/SATA0_TXP USB2N_6
USB2P_6
AF7 USB_CPU_PP5 [66] WLAN
[63] SATA_RX_CPU_N1 G21
PCIE8_RXN/SATA1A_RXN
[63] SATA_RX_CPU_P1 F21 AH1 USB_CPU_PN6 [55]
SSD [63] SATA_TX_CPU_N1 D21
PCIE8_RXP/SATA1A_RXP
PCIE8_TXN/SATA1A_TXN
USB2N_7
USB2P_7
AH2 USB_CPU_PP6 [55] Touch Panel
[63] SATA_TX_CPU_P1 C21
PCIE8_TXP/SATA1A_TXP 3D3V_S0
AF8 USB_CPU_PN7 [66]
USB2N_8
E22
PCIE9_RXN USB2P_8
AF9 USB_CPU_PP7 [66] Card Reader
1. Trace Width: 4 mils min (breakout) 12-15 mils (trace) E23
PCIE9_RXP
B23 AG1
Layout Note: Note: Must maintain low DC resistance routing (<0.1 ohm).
A23
PCIE9_TXN USB2N_9
AG2
USB_CPU_PN8 [69]
Sensor HUB
2. Isolation Spacing: At least 12 mils to any adjacent PCIE9_TXP USB2P_9 USB_CPU_PP8 [69]
SIO_EXT_SCI# 2 1
high speed I/O. F25 AH7 R1608 10KR2J-3-GP
PCIE10_RXN USB2N_10
E25
PCIE10_RXP USB2P_10
AH8 DC resistance < 0.5ohm.
D23
PCIE10_TXN USBCOMP
C23 AB6 1 R1603 2 113R2F-GP
PCIE10_TXP USB2_COMP USB2_ID
AG3
PCIE_RCOMPN USB2_ID USB2_VBUSSENSE
F5 AG4
R1604 1 PCIE_RCOMPP PCIE_RCOMPN USB2_VBUSSENSE
2 E5
100R2F-L1-GP-U PCIE_RCOMPP
A9
TPAD14-OP-GP TP1605 XDP_PRDY# GPP_E9/USB2_OC0# USB_OC0# [34,35]
1 D56 C9
TPAD14-OP-GP TP1606 XDP_PREQ# PROC_PRDY# GPP_E10/USB2_OC1# USB_OC2# USB_OC1# [66]
1 D61 D9
PIRQA# PROC_PREQ# GPP_E11/USB2_OC2# USB_OC3#
BB11 B9
GPP_A7/PIRQA# GPP_E12/USB2_OC3#
E28
PCIE11_RXN/SATA1B_RXN GPP_E4/DEVSLP0
J1 HDD_DEVSLP [60] (#543016) When used as DEVSLP, no external pull-up or pull-down
E27 J2 SIO_EXT_SCI# termination required from SATA Host DEVSLP.
PCIE11_RXP/SATA1B_RXP GPP_E5/DEVSLP1 SIO_EXT_SCI# [24]
D24 J3 MSATA_DEVSLP [63]
PCIE11_TXN/SATA1B_TXN GPP_E6/DEVSLP2
C24
PCIE11_TXP/SATA1B_TXP GPP_E0/SATAXPCIE0/SATAGP0 TP1602 TPAD14-OP-GP
E30 H2 1
3D3V_S0 PCIE12_RXN/SATA2_RXN GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 TP1603 TPAD14-OP-GP 3D3V_S5_PCH
F30 H3 1
PCIE12_RXP/SATA2_RXP GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2 TP1604 TPAD14-OP-GP
A25 G4 1
PCIE12_TXN/SATA2_TXN GPP_E2/SATAXPCIE2/SATAGP2 RN1601
B25
PCIE12_TXP/SATA2_TXP SATA_ACT# USB_OC2#
H1 SATA_ACT# [64] 8 1
R1607 GPP_E8/SATALED#
1 2 10KR2J-3-GP PIRQA# USB_OC3# 7 2
USB_OC0# 6 3
SKYLAKE-U-GP USB_OC1# 5 4
071.SKYLA.000U USB2_ID
RN1602
1 4
USB2_VBUSSENSE 2 3 SRN10KJ-6-GP
3D3V_S0
SRN0J-6-GP
C C
R1606
Follow SKL PDG design guide SATA_ACT# 2 1
10KR2J-3-GP
(#543016) Unused SATAGP[2:0]/GPP_E[2:0] pins must be terminated to either 3.3 V rail or GND
USB 2.0 Table using 8.2 KΩ to 10 KΩ on the motherboard. (#543611)
Do not use both pull-up and pull-down. Either pull-up or pull-down is acceptable. The SATALED# signal is open-collector and requires a weak external pull-up (8.2 kΩ to 10 kΩ) to Vcc3_3.
Pair Device
0 USB3.0 port1
1 USB3.0 Port2 (Debug Port/IOBD)
2 USB3.0 Port3 (IOBD)
3 Sensor HUB
4 CAMERA
5 WLAN
6 Touch Panel
7 Card Reader
#545659 (SKL_PCH_U_Y_EDS Rev0.7)
B B
A A
<Core Design>
Wistron Corporation
Title
CPU_(PCIE/SATA/USB)
A1
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = PCH

Remove Power rail +V3.3A_SIP and R1712(DY), 20141118
R1709,R1723,R1703,R1724 merge to RN1704

3D3V_S5
RN1704
1 8 AC_PRESENT 3D3V_S5 +VCCPDSW_3P3
2 7 PCH_WAKE#
3 6 PCH_BATLOW# 1 R1711 2
4 5 GPD11/LANPHYPC
0R0603-PAD
GPD11 pull high by Intel PDG1.3 request
SRN10KJ-6-GP Layout note: 3 PAD SHARING
D D
RTC_AUX_S5 +V3.3A_SIP
R1730 #544669 (CRB): 330k.

330KR2J-L1-GP
1
1 2 SM_INTRUDER#
R1701
CPU1K 11 OF 20
10KR2J-3-GP
[#543016 Rev0.7] SYSTEM POWER MANAGEMENT
2
+V3.3A_SIP EXT_PWR_GATE#: Due to a bug on A0, a temporary pull-up resistor will be required to overcome the internal 20k AT11
GPP_B12/SLP_S0# SIO_SLP_S0# [24,60]
pull-down that is active during the early portion of the power up sequence SKYLAKE_ULT AP15
GPD4/SLP_S3# SIO_SLP_S3# [24,27,40,51,54]
PCH_PLTRST# AN10 BA16 SIO_SLP_S4# [24,40,54]
XDP_DBRESET# GPP_B13/PLTRST# GPD5/SLP_S4# SIO_SLP_S5#
R1731 1 B5 AY16 1 TP1703 TPAD14-OP-GP
TP1709 PM_RSMRST# SYS_RESET# GPD10/SLP_S5#
AY17
EXT_PWR_GATE# TPAD14-OP-GP RSMRST#
1 2 AN15 SIO_SLP_SUS# [52,54]
H_CPUPWRGD SLP_SUS# SLP_LAN#
1 A68 AW15 1 TP1704 TPAD14-OP-GP
H_VCCST_PWRGD PROCPWRGD SLP_LAN# AUX_EN_WOWL
#544669 Rev0.52 CRB: TP1705 B65 BB17 1 TP1710 TPAD14-OP-GP
20KR2J-L2-GP TPAD14-OP-GP VCCST_PWRGD GPD9/SLP_WLAN# SIO_SLP_A#
No PL resistor on THERMTRIP#. AN16 1 TP1706 TPAD14-OP-GP
SYS_PWROK GPD6/SLP_A#
[24] SYS_PWROK B6
H_CPUPWRGD R1706 PM_PCH_PWROK SYS_PWROK
[24,26] RESET_OUT# 1 2 0R0402-PAD BA20 BA15 SIO_PWRBTN# [24]
PM_RSMRST# R1704 0R2J-2-GP PCH_DPWROK PCH_PWROK GPD3/PWRBTN# AC_PRESENT
1 2 BB20 AY15
DSW_PWROK GPD1/ACPRESENT
1
PCH_BATLOW#
EC1701
NON DS3 AU13
AZ5725-01FDR7G-GP
ME_SUS_PWR_ACK_R AR13 GPD0/BATLOW#
1
[20] ME_SUS_PWR_ACK_R GPP_A13/SUSWARN#/SUSPWRDNACK
BATLOW#:
SUSACK#_R AP11 Pull-up required even if not implemented.
GPP_A15/SUSACK# PME#
AU11 1
PCH_WAKE# GPP_A11/PME# SM_INTRUDER# TP1707 TPAD14-OP-GP
R1714
DY R1707 GPD2/LAN_WAKE#
BB15
WAKE# INTRUDER#
AP16
+VCCPDSW_3P3 1 2 10KR2J-3-GP AM15
2
10KR2J-3-GP GPD11/LANPHYPC GPD2/LAN_WAKE# EXT_PWR_GATE#
AW17 AM10
2
GPD11/LANPHYPC GPP_B11/EXT_PWR_GATE# GPP_B2/VRALERT# AC_PRESENT

AT15 AM11 1
GPD7/USB2_WAKEOUT# GPP_B2/VRALERT# TP1708 TPAD14-OP-GP
RN1703
1 4 PM_RSMRST# (PDG#543016) EC1707
1
PM_PCH_PWROK SKYLAKE-U-GP
2 3
EMI DVT1 0210
WAKE#: Ensure that WAKE# signal Trise (Maximum) is <100 ns. 071.SKYLA.000U DY
SCD1U16V2KX-3GP
SRN10KJ-5-GP
2
R1717 2 DY 1 10KR2J-3-GP SYS_PWROK 3D3V_S5
R1732
1
1 2 GPD2/LAN_WAKE# C1703
[24] EC_WAKE# 3D3V_S5
0R0402-PAD SCD1U16V2KX-3GP DY
SCD1U16V2KX-3GP
2
C C1702 C
U1703 +VCCSTG
1
1
NC#1 VCC
5 DY
2
[24,27,40,51,54] SIO_SLP_S3# 2 DY
1
A
3 4 U1701 R1722
GND Y
DY 100KR2J-1-GP
1
NC#1 VCC
5 Dis-wire with XDP_PM_RSMRST_PWRGD_XDP
74LVC1G07GW-GP
2
[24,40] ALL_SYS_PWRGD 2
A R1713
DY H_VCCST_PWRGD PCH_PLTRST#
AOZ Power switch, P/N: 074.01334.0093 R1733 3
GND Y
4 [24,66,68] PLT_RST# 1 2
1 DY 2 0R0402-PAD
Low Rds(on)= 5m Ohm
1
0R2J-2-GP
EC1708
AZ5725-01FDR7G-GP
1
1
Turn on rise time = 10us
C1711
74LVC1G07GW-GP R1715 C1701
SCD01U50V2KX-1GP
For sequence fine tune 2016/01/04 73.01G07.0HG 100KR2J-1-GP DY DY SC220P50V2KX-3GP
DY
2
2
3D3V_S5
+VCCMPHYGTAON_1P0
2
1 2 R1722 & EC1708 modify to 100k and 0.01uF at DVT1
R1716
SKL: 1.0V
1
EC1713 100KR2F-L1-GP
EC1709
AZ5725-01FDR7G-GP
1
1
SC2D2U10V2KX-GP
+VCCMPHYGTAON_1P0(ICCMAX.=3.5A)
DY R1719
47KR2F-GP #543016 Rev0.7
2
EMI DVT1 0210 1. VCCST_PWRGD is only 1.0 V tolerant.
1D0V_S5 +VCCMPHYGTAON_1P0_LS_SIP
2. VCCST_PWRGD must go low during Sx pwr states, regardless of the voltage level of VCCST
2
EMI DVT1 0210
R1724
1 2 RF request 2016/01/12 modify
EC1710 0R0805-PAD
1
SC2D2U10V2KX-GP
DY C1704
1
SC10U6D3V3MX-GP
2
1 R1735 2 4th = 84.DMN66.03F

3rd = 75.00601.07C
2
0R0805-PAD XDP_DBRESET# 2nd = 84.2N702.E3F D1701

B SYS_PWROK 84.2N702.A3F RB751V-40H-GP B
PLT_RST#
RESET_OUT# A K ACOK_IN_M [43,44]
RF request 2016/01/12 modify Follow Iris SKL 3V_5V_POK Q1702
3D3V_AUX_S5 2N7002KDW-GP
2015/11/30 modify
83.R2004.G8F
1
EC1702
EC1703
EC1704
EC1705
AZ5725-01FDR7G-GP
AZ5725-01FDR7G-GP
AZ5725-01FDR7G-GP
AZ5725-01FDR7G-GP
1 4 3 AC_PRESENT
EC1706
DY PM_RSMRST#_R 1NON PM_RSMRST#
DS32
NON DS3 DS3 BOM Option EMI DVT1 0210 R1737
5NON DS3
2
SC1KP50V2KX-1GP
2
1NON DS3
2 PM_RSMRST#_M 6 1 R1720
2
2
R1708 0R2J-2-GP
ME_SUS_PWR_ACK_R 1 2 SUSACK#_R R1718 1 DY 2 0R2J-2-GP 100KR2J-1-GP
[24] PCH_DPWROK 3V_5V_POK [40,45,52,54]
0R2J-2-GP
RN1702 Change dummy property from DS3 to DY
TPAD14-OP-GP TP1711 1 SUSACK# 2 DS3 34 SUSACK#_R
1
TPAD14-OP-GP TP1712 1ME_SUS_PWR_ACK ME_SUS_PWR_ACK_R

EC1711
1
AZ5725-01FDR7G-GP
SRN0J-6-GP Reserve by NON DS3 function 20150413

2
3D3V_AUX_S5 R1727
100KR2J-1-GP
1 2 Change location to net PCH_DPWROK
NON DS3
2
R1726
10KR2J-3-GP
1KR2J-1-GP
Q1701
1
R1702
4 3 PM_RSMRST# 1 2 PCH_RSMRST# [24]
R1728
3V_5V_POK# 5 2 3V_5V_POK_C 1 2 3V_5V_POK [40,45,52,54]
NON DS3 EC1712
6 1
1
0R2J-2-GP
C1710
DY
SCD47U10V2KX-GP
DS3 DY
SCD1U16V2KX-3GP
A 2N7002KDW-GP R1729 1 SIO_SLP_SUS# A

2
2
0R2J-2-GP
84.2N702.A3F
2nd = 84.2N702.E3F <Core Design>
3rd = 75.00601.07C Dummy C1710 by it's useless
4th = 84.DMN66.03F
Wistron Corporation
EC1711 modify to 100k and 0.01uF at DVT1 20150203
Title
CPU_(POWER MANAGEMENT)
A2 A00
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
Main Func = PCH PCH strap pin: PCH Prim

PCH strap pin: PCH Prim
eSPI or LPC Sampled at rising edge of RSMRST# 3D3V_S5_PCH
BOOT HALT 3D3V_S5_PCH
SML0ALERT# / This signal has a weak internal pull-down. 3D3V_S5_PCH
1
0 = LPC Is selected for EC. SPI0_MOSI 0 = ENABLED
GPP_C5
1
1 = eSPI Is selected for EC. DY R1822 1 = DISABLED
1KR2J-1-GP WEAK INTERNAL PU DY R1824 RN1807
This signal has a weak internal pull-down. 1KR2J-1-GP SML1_SMBDATA 8 1
This signal has a weak internal pull-up. SML1_SMBCLK 7 2
2
SML0_SMBDATA 6 3
2
GPP_C5/SML0ALERT# SML0_SMBCLK 5 4
SPI_SI_CPU
1
SRN2K2J-4-GP
1
DY R1823
R1825 DVT1 0210, Reserve by Intel MOW
1KR2J-1-GP DY
1KR2J-1-GP
D GPP_B23/SML1ALERT# 2 1 D
2
150KR2J-GP R1837
2
R1835 and R1834 merge to RN1802
2015/10/06 modify R1836
GPP_C2/SMBALERT# 2 1
3D3V_S5_PCH 2K2R2J-2-GP
SRN2K2J-1-GP
RN1802
1 4 SPI_HOLD_ROM MEM_SMBCLK 3 2
2 3 SPI_WP_ROM MEM_SMBDATA 4 1
SRN1KJ-7-GP RN1811
LPC_LAD[3..0]
[24,68] LPC_LAD[3..0]
RN1806
LPC_LAD0 8 1 LPC_LAD0_R
R1806,R1807,R1808,R1809 merge to RN1803 LPC_LAD1 7 2 LPC_LAD1_R
2015/10/06 modify LPC_LAD2 6 3 LPC_LAD2_R
LPC_LAD3 5 4 LPC_LAD3_R
RN1803 SRN0J-7-GP-U
3D3V_S0 1 8 CPU1E 5 OF 20
[24,25] SPI_CLK_ROM
[24,25] SPI_SO_ROM 2 7
SPI - FLASH
R1820 [24,25] SPI_SI_ROM 3 6 SMBUS, SMLINK
4 5 SPI_CLK_CPU AV2 SKYLAKE_ULT R7 MEM_SMBCLK 3D3V_S5_PCH
[25] SPI_WP_ROM SPI0_CLK GPP_C0/SMBCLK
1 2 SIO_RCIN# SPI_SO_CPU AW3 R8 MEM_SMBDATA
10KR2J-3-GP SRN10J-1-GP SPI_SI_CPU SPI0_MISO GPP_C1/SMBDATA GPP_C2/SMBALERT#
AV3 Strap R10
SPI_WP_CPU SPI0_MOSI GPP_C2/SMBALERT# R1814
R1821 AW2
10R2F-L-GP 1 SPI_HOLD_CPU SPI0_IO2 SML0_SMBCLK SUS_STAT#/LPCPD#
[25] SPI_HOLD_ROM 2 R1811 AU4 R9 2 DY 1
SERIRQ 0R0402-PAD 1 SPI_CS_CPU_N0 SPI0_IO3 GPP_C3/SML0CLK SML0_SMBDATA
1 2 [24,25] SPI_CS_ROM_N0 2 R1812 AU3 W2
10KR2J-3-GP SPI0_CS0# GPP_C4/SML0DATA GPP_C5/SML0ALERT# 10KR2J-3-GP
AU2 W1
AU1
SPI0_CS1# Strap GPP_C5/SML0ALERT# 3D3V_S0
SPI0_CS2# SML1_SMBCLK
SERIRQ PH: GPP_C6/SML1CLK
W3 SML1_SMBCLK [24,26,66]
R1818
PDG: 8.2k V3 SML1_SMBDATA 8K2R2F-1-GP
SPI - TOUCH GPP_C7/SML1DATA SML1_SMBDATA [24,26,66]
AM7 GPP_B23/SML1ALERT# CLKRUN#_R 1 2
CRB: 10k TPAD14-OP-GP TP1801 CPU_D1_TP GPP_B23/SML1ALERT#/PCHHOT#
1 M2
GPP_D1/SPI1_CLK
[70] HDD_FALL_INT M3
GPP_D2/SPI1_MISO
J4
[60] HDD_EN_PCH TPAD14-OP-GP TP1804 CPU_D4_TP GPP_D3/SPI1_MOSI
1 V1
TPAD14-OP-GP TP1805 CPU_D5_TP GPP_D21/SPI1_IO2
1 V2
TPAD14-OP-GP TP1806 CPU_D6_TP GPP_D22/SPI1_IO3 LPC_LAD0_R
1 M1 LPC AY13
GPP_D0/SPI1_CS# GPP_A1/LAD0/ESPI_IO0 LPC_LAD1_R
C BA13 C
GPP_A2/LAD1/ESPI_IO1 LPC_LAD2_R
BB13
C LINK GPP_A3/LAD2/ESPI_IO2 LPC_LAD3_R
AY12
GPP_A4/LAD3/ESPI_IO3 LPC_LFRAME#_R 3D3V_S0
G3 BA12 2 R1801 1 LPC_LFRAME# [24,68]
CL_CLK GPP_A5/LFRAME#/ESPI_CS# SUS_STAT#/LPCPD# 0R0402-PAD
G2 BA11
CL_DATA GPP_A14/SUS_STAT#/ESPI_RESET#
G1
CL_RST# RN1810
AW9 PCI_CLK_LPC0 3 2
GPP_A9/CLKOUT_LPC0/ESPI_CLK 3D3V_S0
RCIN#: [24] SIO_RCIN# AW13 AY9 PCI_CLK_LPC1 R1819 4 1
GPP_A0/RCIN# GPP_A10/CLKOUT_LPC1 CLKRUN#_R
Frequency to Avoid: 33 MHz AW11 1 2 CLKRUN# [24]
GPP_A8/CLKRUN# 0R0402-PAD SRN10KJ-5-GP
[24] SERIRQ AY11
GPP_A6/SERIRQ
2N7002KDW-GP
SKYLAKE-U-GP MEM_SMBDATA 6 1 PCH_SMBDATA [12,13]
071.SKYLA.000U
84.2N702.A3F 5 2
20140820 DAIVD 2nd = 84.2N702.E3F
3rd = 75.00601.07C 4 3
4th = 84.DMN66.03F
Q1801
PCI_CLK_LPC0 R1804 2 22R2J-2-GP
PCI_CLK_LPC1 R1805
1 LPC CLK_PCI_LPC [68]
1 2 22R2J-2-GP CLK_PCI_LPC_MEC [24] PCH_SMBCLK [12,13]
MEM_SMBCLK
EC1801
SC10P50V2JN-4GP
EC1802
SC10P50V2JN-4GP
1
1
DY DY
2
EE for DVT1 0212
B B
RTC_X1 C1801
XTAL24_IN 2 1
1 2 RTC_X2
3D3V_S0 R1815 10MR2J-L-GP
SC15P50V2JN-2-GP
X1802
1
X1801
1
RN1812 1 4 XTAL-24MHZ-81-GP
1 8 CLKREQ_PCIE#3 R1802
2 7 CLKREQ_PEG#0 1MR2J-1-GP 82.30004.841
3 6 CLKREQ_PCIE#4 C1804 C1803
4
2
2
4 5 SC3P50V2CN-1-GP 2 3 SC3P50V2CN-1-GP
2
C1802
R1810
1
SRN10KJ-6-GP XTAL24_OUT 1 2 XTAL24_OUT_R 2 1
CPU1J 10 OF 20 XTAL-32D768KHZ-67-GP 0R0402-PAD
CLKREQ_PCIE#5 SC15P50V2JN-2-GP
1 8 CLOCK SIGNALS
2 7 CLKREQ_PCIE#1 DVT1 0212 for Vendor suggest
3 6 CLKREQ_PCIE#2 D42
[66] CLK_PCIE_VGA# CLKOUT_PCIE_N0 SKYLAKE_ULT
4 5 [66] CLK_PCIE_VGA C42
CLKREQ_PEG#0 CLKOUT_PCIE_P0 DVT1 0212 for Vendor suggest (change 3p)
[66] CLKREQ_PEG#0 AR10
GPP_B5/SRCCLKREQ0#
RN1813
SRN10KJ-6-GP WLAN [66] PEG_CLK1_CPU#
[66] PEG_CLK1_CPU
B42
A42
CLKOUT_PCIE_N1
CLKOUT_PCIE_P1 CLKOUT_ITPXDP#
F43 PCIE_CLK_XDP_N 1 TP1802 TPAD14-OP-GP SUSCLK_R
AT7 E43 PCIE_CLK_XDP_P 1 TP1803 TPAD14-OP-GP
[66] CLKREQ_PCIE#1
2
GPP_B6/SRCCLKREQ1# CLKOUT_ITPXDP_P
SUSCLK_R 1 R1813 2 SUSCLK TP1807 TPAD14-OP-GP RTC_AUX_S5 EC1803
D41
CLKOUT_PCIE_N2 GPD8/SUSCLK
BA17 1 DY
C41 0R0402-PAD
1
CLKOUT_PCIE_P2
SC4D7P50V2BN-GP
CLKREQ_PCIE#2 AT8 E37 XTAL24_IN +V1.00A_SIP
GPP_B7/SRCCLKREQ2# XTAL24_IN XTAL24_OUT +V1.05S_AXCK_LCPLL
E35
XTAL24_OUT
D40
CLKOUT_PCIE_N3
2
1
C40 E42 XCLK_BIASREF 1 R1803 2
CLKREQ_PCIE#3 CLKOUT_PCIE_P3 XCLK_BIASREF 2K7R2F-GP RN1801
AT10
GPP_B8/SRCCLKREQ3# RTC_X1
AM18 SRN20KJ-1-GP
RTCX1 RTC_X2 Intel recommend: 2.71k ohm 1%
B40 AM20
CLKOUT_PCIE_N4 RTCX2
A40
CLKREQ_PCIE#4 CLKOUT_PCIE_P4 SRTC_RST#
AU8 AN18
3
4
GPP_B9/SRCCLKREQ4# SRTCRST# RTC_RST#
AM16
A RTCRST# Q1802 A
E40
CLKOUT_PCIE_N5
E38 [24] RTCRST_ON G
CLKREQ_PCIE#5 CLKOUT_PCIE_P5 SRTC_RST#
AU7
GPP_B10/SRCCLKREQ5#
1
D RTC_RST#
R1816
SC1U10V2KX-1GP
2
10KR2J-3-GP S
1
<Core Design>
C1806
G1801
1
1
SCD1U16V2KX-3GP
SKYLAKE-U-GP 2N7002K-2-GP C1805

2
1
EC1808
GAP-OPEN
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
071.SKYLA.000U DY 84.2N702.J31 SC1U10V2KX-1GP
Wistron Corporation
EC1806
EC1807
2ND = 84.2N702.031 DY DY
2
2
3rd = 84.07002.I31 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2
(#514849)
Title
Layout: Place at the open door area. Size

CPU_(LPC/SPI/SMBUS/CL/CLK)
Document Number Rev
A2 A00
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
Main Func = PCH Strap pin:

Port B /
Sampled at rising edge of PCH_PWROK
Port C Detected
0 = Port B is not detected.

DDPB_CTRLDATA * 1 = Port B is detected.
0 = Port C is not detected.

DDPC_CTRLDATA * 1 = Port C is detected.
D D
CPU1G 7 OF 20
These two signals have weak internal pull-down.
AUDIO
SKYLAKE_ULT
HDA_SYNC BA22
HDA_BITCLK HDA_SYNC/I2S0_SFRM
AY22 HDA_BLK/I2S0_SCLK
HDA_SDOUT BB22 SDIO/SDXC
HDA_SDO/I2S0_TXD
[27] HDA_SDIN0 BA21 HDA_SDI0/I2S0_RXD
AY21 HDA_SDI1/I2S1_RXD GPP_G0/SD_CMD AB11
HDA_RST# AW22 AB13
HDA_RST#/I2S1_SCLK GPP_G1/SD_DATA0
J5 GPP_D23/I2S_MCLK GPP_G2/SD_DATA1 AB12
AY20 I2S1_SFRM GPP_G3/SD_DATA2 W12
AW20 I2S1_TXD GPP_G4/SD_DATA3 W11
GPP_G5/SD_CD# W10
AK7 GPP_F1/I2S2_SFRM GPP_G6/SD_CLK W8 KB_LED_BL_DET_R [65]
AK6 GPP_F0/I2S2_SCLK GPP_G7/SD_WP W7
AK9 GPP_F2/I2S2_TXD
AK10 GPP_F3/I2S2_RXD GPP_A17/SD_PWR_EN#/ISH_GP7 BA9
BB9 CPU_A16_TP 1
GPP_A16/SD_1P8_SEL TP1902 TPAD14-OP-GP
H5 AB7 SD_RCOMP 1 R1901 2
GPP_D19/DMIC_CLK0 SD_RCOMP
D7 GPP_D20/DMIC_DATA0
200R2F-L-GP
D8 GPP_D17/DMIC_CLK1 GPP_F23 AF13
C8 GPP_D18/DMIC_DATA1
[27] SPKR AW5 GPP_B14/SPKR
C C
SKYLAKE-U-GP
PCH strap pin:
PCH strap pin: 071.SKYLA.000U
Flash Descriptor Security Overide/ NO REBOOT
3D3V_S0
Intel ME Debug Mode 1KR2J-1-GP
Low = Default * Low = Enable (Default) R2006
HDA_SDOUT High = Enable HDA_SPKR
* 1 DY 2 SPKR
High = Disable
The internal pull-down is disabled after
PLTRST# deasserts The internal pull-down is disabled after
PLTRST# deasserts
[27] HDA_CODEC_SYNC R1908 1 2 0R0402-PAD HDA_SYNC
1 HDA_RST#_R R1911 1 2 0R0402-PAD HDA_RST#

TPAD14-OP-GP TP1903
EC1901
1 2 HDA_CODEC_BITCLK
B B
DY
SC10P50V2JN-4GP
SRN33J-5-GP-U
[27] HDA_CODEC_BITCLK 2 3 HDA_BITCLK

HDA_RST# [27] HDA_CODEC_SDOUT 1 4 HDA_SDOUT
RN1902
1
DY EC1902 [24] ME_FW P_EC R1909 1 2 1KR2J-1-GP

SCD1U16V2KX-3GP
2
R1907,R1912 merge to RN1902

2015/10/06 modify
A <Core Design> A
Wistron Corporation
Title
CPU_(AUDIO/SDIO/SDXC)
A3 A00
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
Main Func = PCH 3D3V_S0
RN2007
SRN1KJ-7-GP
I2C0_SCL 1 4
EC2002 2 1 I2C0_SDA 2 3
DGPU_HOLD_RST# [66]
SC1KP50V2KX-1GP SRN2K2J-1-GP
RN2009 CPU1F 6 OF 20 I2C1_SCL 2 3

1 4 DGPU_HOLD_RST# I2C1_SDA 1 DY 4
DGPU_PWR_EN LPSS ISH
2 OPS 3
SKYLAKE_ULT
RN2008
SRN10KJ-5-GP R2003 1GC6_202 0R2J-2-GP GPU_EVENT_MCP# AN8 P2 USB_UART_SEL_D9 1 TP2006 TPAD14-OP-GP
[66] GPU_EVENT# GPP_B15/GSPI0_CS# GPP_D9/ISH_SPI_CS#
R2004 1GC6_202 0R2J-2-GP GC6_FB_EN_MCP AP7 P3 DGPU_HOLD_RST#
[66] GC6_FB_EN GPP_B16/GSPI0_CLK GPP_D10/ISH_SPI_CLK
VRAM_ID1 AP8 P4 (PDG#543016) Ensure that all I2C interface on-board terminations are pulled up
GPP_B18/GSPI0_MOSI GPP_B17/GSPI0_MISO GPP_D11/ISH_SPI_MISO RTC_DET#
AR7 P1 RTC_DET# [25] to the same voltage rail as the device/end point.
GPP_B18/GSPI0_MOSI GPP_D12/ISH_SPI_MOSI
3D3V_S0
Strap
I2C0_SDA R2021 2 0R2J-2-GP
[55] DBC_PANEL_EN AM5
GPP_B19/GSPI1_CS# GPP_D5/ISH_I2C0_SDA
M4
I2C0_SCL R2020
1 ISH SENSOR_I2C_SDA [55,69,70]
D AN7 N3 1 ISH 2 0R2J-2-GP SENSOR_I2C_SCL [55,69,70] D
GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL
AP5
TP2018 GPP_B22 GPP_B21/GSPI1_MISO I2C1_SDA
1 AN5 N1
TPAD14-OP-GP GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA I2C1_SCL
N2
51KR2J-1-GP LPSS_UART2_RXD GPP_D8/ISH_I2C1_SCL
1 DY 2 R2048 AB1
51KR2J-1-GP LPSS_UART2_TXD [29] SPK_DET# GPP_C8/UART0_RXD 1.8V Only
1 DY 2 R2049 [66] BLUETOOTH_EN AB2 AD11
GPP_C9/UART0_TXD GPP_F10/I2C5_SDA/ISH_I2C2_SDA
W4 AD12
[55] IR_CAMERA_DET# BOARD_ID2 GPP_C10/UART0_RTS# GPP_F11/I2C5_SCL/ISH_I2C2_SCL
AB3
Change to Dummy 20150402 GPP_C11/UART0_CTS#
10KR2J-3-GP 1 DY 2 R2042 BLUETOOTH_EN LPSS_UART2_RXD AD1 U1
GPP_C20/UART2_RXD GPP_D13/ISH_UART0_RXD/SML0BDATA DGPU_PWR_EN [66]
10KR2J-3-GP 1 2 R2043 DBC_PANEL_EN LPSS_UART2_TXD AD2 U2 UART0_TXD 1
GPP_C21/UART2_TXD GPP_D14/ISH_UART0_TXD/SML0BCLK TP2012 TPAD14-OP-GP
10KR2J-3-GP 1 2 R2044 FFS_INT2 AD3 U3 UART0_RTS# 1
[24] SIO_EXT_WAKE# GPP_C22/UART2_RTS# GPP_D15/ISH_UART0_RTS# TP2013 TPAD14-OP-GP
10KR2J-3-GP 1 2 R2045 KB_DET# AD4 U4 UART0_CTS# 1
[65] KB_DET# GPP_C23/UART2_CTS# GPP_D16/ISH_UART0_CTS#/SML0BALERT# TP2014 TPAD14-OP-GP
10KR2J-3-GP 1 2 R2046 IR_CAMERA_DET#
10KR2J-3-GP 1 2 R2047 SPK_DET# AC1 BOARD_ID1
GPP_C12/UART1_RXD/ISH_UART1_RXD
[65] I2C0_SDA_TCH_PAD U7 AC2
GPP_C16/I2C0_SDA GPP_C13/UART1_TXD/ISH_UART1_TXD UART1_RTS# FFS_INT2 [70]
[65] I2C0_SCL_TCH_PAD U6 AC3 1 TP2016 TPAD14-OP-GP
GPP_C17/I2C0_SCL GPP_C14/UART1_RTS#/ISH_UART1_RTS# UART1_CTS#
AB4 1 TP2017 TPAD14-OP-GP
GPP_C15/UART1_CTS#/ISH_UART1_CTS#
U8
PTP U9
GPP_C18/I2C1_SDA
GPP_C19/I2C1_SCL GPP_A18/ISH_GP0
AY8 ISH_KB_DISABLE R2022 1 2 0R0402-PAD
KB_DISABLE [24,69]
BA8 GSEN_INT1_ISH R2023 1 2 0R0402-PAD
PCH strap pin: PCH Prim AH9
GPP_A19/ISH_GP1
BB7 GSEN_INT2_ISH R2024 1 2 0R0402-PAD
GSEN_INT1 [55,69]
GPP_F4/I2C2_SDA GPP_A20/ISH_GP2 GSEN2_INT1_ISH GSEN_INT2 [55,69]
AH10 BA7 R2025 1 2 0R0402-PAD
GPP_F5/I2C2_SCL GPP_A21/ISH_GP3 GSEN2_INT2_ISH GSEN2_INT1_C [69,70] (PDG#543016) If the UART/GPIO functionality is also not used,
AY7 R2026 1 2 0R0402-PAD
No Reboot Sampled at rising edge of PCH_PWROK 3D3V_S5_PCH GPP_A22/ISH_GP4 GYRO_INT_ISH
GSEN2_INT2_C [69,70]
AH11 AW7 R2027 1 2 0R0402-PAD the signals can be left as no-connect.
GPP_F6/I2C3_SDA GPP_A23/ISH_GP5 GYRO_INT_C [69,70]
AH12 AP13 GYRO_DRDY_ISH R2028 1 2 0R0402-PAD
0 = Disable “No Reboot” mode. GPP_F7/I2C3_SCL GPP_A12/BM_BUSY#/ISH_GP6 GYRO_DRDY [55,69]
GSPI0_MOSI /
1
GPP_B18 1 = Enable “No Reboot” mode (PCH will disable the TCO AF11
GPP_F8/I2C4_SDA
Timer system reboot feature). This function is useful DY R2007 AF12
GPP_F9/I2C4_SCL
when running ITP/XDP. 1KR2J-1-GP
SKYLAKE-U-GP
2
The signal has a weak internal pull-down.

GPP_B18/GSPI0_MOSI
071.SKYLA.000U
1
DY R2019
1KR2J-1-GP
2
C C
3D3V_S5_PCH 3D3V_S0 3D3V_S0 3D3V_S0
1
GPP_C11
R2039 1 DY 2 10KR2J-3-GP R2005 BIOS strap pin: R2029 R2010
ME_SUS_PWR_ACK_R [17] OPS 10KR2J-3-GP DY 10KR2J-3-GP BBY 10KR2J-3-GP
BIOS UMA/DIS Strap pin BOARD_ID2
2
2
R2040 1 2 10KR2J-3-GP RTC_DET#
R2041 1 2 10KR2J-3-GP SIO_EXT_WAKE# BOARD_ID2 UMA 0 VRAM_ID1 BOARD_ID1
1
1
DIS 1
R2008 R2030 R2009
10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP
UMA DY ROR
2
2
B B
A A
<Core Design>
Wistron Corporation
Title
CPU_(LPSS/ISH)
A2 A00
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
Main Func = PCH
D D
+V1.00A_SIP
CPU1O 15 OF 20
+V3.3A_SIP
CPU POWER 4 OF 4
AB19
VCCPRIM_1P0
AB20 AK15
+VCCPRIM_CORE VCCPRIM_1P0 SKYLAKE_ULT VCCPGPPA +VCCPRTC_3P3
P18
VCCPRIM_1P0 VCCPGPPB
AG15 Layout Note:
Y16
VCCPGPPC
2.57A AF18
VCCPRIM_CORE VCCPGPPD
Y15 0.1uF:
C2118
SCD1U16V2KX-3GP
C2117
SC1U10V2KX-1GP
AF19 T16
VCCPRIM_CORE VCCPGPPE C2118 near AK19
1
V20 1.8V Only AF16 +V1.8A_SIP
VCCPRIM_CORE VCCPGPPF
+VCCDSW_1P0
V21
VCCPRIM_CORE VCCPGPPG
AD15 +V3.3A_SIP 1uF:
C2117 near Ak19
2
C2120 AL1 V19
1
+V1.00A_SIP DCPDSW_1P0 VCCPRIM_3P3_V19

SC1U10V2KX-1GP
EC2101 DY
K17 T1 +V1.00A_SIP
VCCMPHYAON_1P0 VCCPRIM_1P0_T1
SCD1U25V2KX-GP
L1
2
+VCCMPHYGTAON_1P0_LS_SIP VCCMPHYAON_1P0
AA1 +V1.8A_SIP
VCCATS_1P8
N15
VCCMPHYGT_1P0_N15
N16 AK17 +V3.3A_SIP
VCCMPHYGT_1P0_N16 VCCRTCPRIM_3P3 +VCCPRTC_3P3
N17
VCCMPHYGT_1P0_N17
P15 AK19
VCCMPHYGT_1P0_P15 VCCRTC_AK19
P16 BB14
+VCCAMPHYPLL_1P0 VCCMPHYGT_1P0_P16 VCCRTC_BB14
K15 BB10 VCCRTCEXT C2112 1 2 SCD1U16V2KX-3GP
VCCAMPHYPLL_1P0 DCPRTC
L15
+VCCAPLL_1P0 VCCAMPHYPLL_1P0
A14 +V1.00A_SIP
VCCCLK1
V15
+V1.00A_SIP VCCAPLL_1P0
K19 +VCCCLK2
VCCCLK2
AB17
VCCPRIM_1P0_AB17
Y18 L21 +V1.00A_SIP
1D5V_S0 +VCCPDSW_3P3 VCCPRIM_1P0_Y18 VCCCLK3
AD17 N20 +VCCCLK4
R2102 VCCDSW_3P3_AD17 VCCCLK4
+V3.3A_SIP 0R2J-2-GP
1 DY 2 AD18
VCCDSW_3P3_AD18 RTC_AUX_S5 +VCCPRTC_3P3
AJ17 L19 +VCCCLK5
+VCCPAZIO VCCDSW_3P3_AJ17 VCCCLK5
R2101 1 2 AJ19 A10 +V1.00A_SIP 1 R2106 2
VCCHDA VCCCLK6
0R0402-PAD +V3.3A_SIP AJ16 AN11 V0.85A_VID0 1 TP2101 TPAD14-OP-GP 0R0603-PAD
VCCSPI GPP_B0/CORE_VID0
AN13 V0.85A_VID1 1 TP2102 TPAD14-OP-GP
GPP_B1/CORE_VID1 +VCCMPHYGTAON_1P0_LS_SIP +VCCAMPHYPLL_1P0
C
+VCCMPHYGTAON_1P0_LS_SIP AF20 C
VCCSRAM_1P0
AF21
VCCSRAM_1P0
T19 1 R2107 2
VCCSRAM_1P0
T20
+V3.3A_SIP VCCSRAM_1P0 0R0603-PAD
AJ21
+V1.00A_SIP VCCPRIM_3P3_AJ21
AK20 +V1.00A_SIP +VCCAPLL_1P0
VCCPRIM_1P0_AK20
071.SKYLA.000U
+VCCMPHYGTAON_1P0_LS_SIP N18 1 R2108 2
VCCAPLLEBB
0R0603-PAD
SKYLAKE-U-GP +V1.00A_SIP +VCCCLK2
1 R2109 2
0R0603-PAD
+V1.00A_SIP +VCCCLK4
1 R2110 2
0R0603-PAD
+V1.00A_SIP +VCCCLK5
1 R2111 2
0R0603-PAD
+V3.3A_SIP +V1.8A_SIP +VCCPRIM_CORE +VCCDSW_1P0 +V1.00A_SIP

Layout Note:
Layout Note:
1uF:
1uF: C2101 near AB19
C2105
C2106
C2107
C2109
C2110
C2111
C2108
C2102
C2103
C2101
C2104
C2121
B B
C2105 near V19
1
1
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
SC1U10V2KX-1GP
C2104 near K17
C2106 near AK17 DY C2116 near A10
C2107 near AG15
2
2
C2121 near AL1
C2109 near Y16
C2110 near T16
C2111 near AJ19
+VCCAMPHYPLL_1P0 +VCCAPLL_1P0 +V1.00A_SIP +VCCCLK2 +VCCCLK4 +VCCCLK5

Layout Note:
Layout Note: Layout Note:
1uF:
22uF: 22uF: C2116 near A10
C2113 near K15 C2113 near K15
C2113
SC22U6D3V3MX-1-GP
C2114
SC22U6D3V3MX-1-GP
C2116
SC1U10V2KX-1GP
C2115
SC22U6D3V3MX-1-GP
C2119
SC22U6D3V3MX-1-GP
C2122
SC22U6D3V3MX-1-GP
22uF:
1
C2115 near K19

DY DY DY DY DY
C2119 near N20
2
C2122 near L19
A A
<Core Design>
Wistron Corporation
Title
CPU_(POWER1)
A2 A00
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
Main Func = PCH
D D
CPU1T 20 OF 20
SKYLAKE_ULT
SPARE
AW69 RSVD_AW69 RSVD_F6 F6

AW68 RSVD_AW68 RSVD_E3 E3
AU56 RSVD_AU56 RSVD_C11 C11
AW48 RSVD_AW48 RSVD_B11 B11
C7 RSVD_C7 RSVD_A11 A11
U12 RSVD_U12 RSVD_D12 D12
U11 RSVD_U11 RSVD_C12 C12
H11 RSVD_H11 RSVD_F52 F52
SKYLAKE-U-GP
C C
071.SKYLA.000U
B B
<Core Design>
A
Title
CPU_(RSVD)
A4 A00
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
Main Func = PCH
CPU1Q 17 OF 20
GND 2 OF 3 CPU1R 18 OF 20
CPU1P 16 OF 20
AT63 SKYLAKE_ULT BA49 GND 3 OF 3
GND 1 OF 3 VSS VSS
D AT68 VSS VSS BA53 F8 VSS VSS L18 D
AT71 VSS VSS BA57 G10 VSS VSS L2
1 A5_TP A5 SKYLAKE_ULT AL65 AU10 BA6 G22 SKYLAKE_ULT L20
TPAD14-OP-GP TP2309 VSS VSS VSS VSS VSS VSS
TPAD14-OP-GP TP2311 1 A67_TP A67 AL66 AU15 BA62 G43 L4
A70_TP A70 VSS VSS VSS VSS VSS VSS
TPAD14-OP-GP TP2310 1 VSS VSS AM13 AU20 VSS VSS BA66 G45 VSS VSS L8
AA2 AM21 AU32 BA71 BA71_TP 1 TP2303 TPAD14-OP-GP G48 N10
VSS VSS VSS VSS VSS VSS
AA4 VSS VSS AM25 AU38 VSS VSS BB18 G5 VSS VSS N13
AA65 AM27 TPAD14-OP-GP TP2307 1 AV1_TP AV1 BB26 G52 N19
AA68 VSS VSS AM43 AV68 VSS VSS BB30 G55 VSS VSS N21
AB15 VSS VSS AM45 AV69 VSS VSS BB34 G58 VSS VSS N6
AB16 VSS VSS AM46 AV70 VSS VSS BB38 G6 VSS VSS N65
AB18 AM55 TPAD14-OP-GP TP2304 1 AV71_TP AV71 BB43 G60 N68
AB21 VSS VSS AM60 AW10 VSS VSS BB55 G63 VSS VSS P17
AB8 VSS VSS AM61 AW12 VSS VSS BB6 G66 VSS VSS P19
AD13 VSS VSS AM68 AW14 VSS VSS BB60 H15 VSS VSS P20
AD16 VSS VSS AM71 AW16 VSS VSS BB64 H18 VSS VSS P21
AD19 AM8 AW18 BB67 BB67_TP 1 TP2302 TPAD14-OP-GP H71 R13
VSS VSS VSS VSS BB70_TP 1 VSS VSS
AD20 VSS VSS AN20 AW21 VSS VSS BB70 TP2301 TPAD14-OP-GP J11 VSS VSS R6
AD21 AN23 AW23 C1 C1_TP 1 TP2308 TPAD14-OP-GP J13 T15
AD62 VSS VSS AN28 AW26 VSS VSS C25 J25 VSS VSS T17
AD8 VSS VSS AN30 AW28 VSS VSS C5 J28 VSS VSS T18
AE64 VSS VSS AN32 AW30 VSS VSS D10 J32 VSS VSS T2
AE67 VSS VSS AN37 AW36 VSS VSS D18 J42 VSS VSS U10
AE68 VSS VSS AN38 AW38 VSS VSS D22 J8 VSS VSS U63
AE69 VSS VSS AN40 VSS D25 K16 VSS VSS U64
AF1 VSS VSS AN42 AW41 VSS VSS D26 K18 VSS VSS U66
AF10 VSS VSS AN58 AW43 VSS VSS D30 K22 VSS VSS U67
C AF15 AN63 AW45 D34 K61 U69 C
AF17 VSS VSS AP10 AW47 VSS VSS D39 K63 VSS VSS U70
AF2 VSS VSS AP18 AW49 VSS VSS D44 K64 VSS VSS V16
AG16 VSS VSS AP28 AW55 VSS VSS D48 K67 VSS VSS W13
AG19 VSS VSS AP38 AW60 VSS VSS D6 K71 VSS VSS Y17
AG20 VSS VSS AP42 AW62 VSS VSS D62 L11 VSS VSS Y19
AH13 VSS VSS AP68 AW8 VSS VSS E11
AH6 VSS VSS AP70 AY66 VSS VSS E15
AH63 VSS VSS AR11 B10 VSS VSS E18
AH64 VSS VSS AR15 B14 VSS VSS E21
AH67 AR16 B18 E46 SKYLAKE-U-GP
VSS VSS VSS VSS
AJ15 VSS VSS AR20 B22 VSS VSS E50
AJ20 VSS VSS AR28 B34 VSS VSS E56 071.SKYLA.000U
AK11 VSS VSS AR42 B44 VSS VSS E65
AK16 AR43 B48 E71 E71_TP 1 TP2313 TPAD14-OP-GP
VSS VSS VSS VSS
AK18 VSS VSS AR45 B53 VSS VSS F1
AK63 AR50 TPAD14-OP-GP TP2312 1 B71_TP B71 F23
VSS VSS BA1_TP VSS VSS
AK68 VSS VSS AR52 TPAD14-OP-GP TP2305 1 BA1 VSS VSS F27
B B
AK69 VSS VSS AR53 BA10 VSS VSS F28
AK8 VSS VSS AR55 BA14 VSS VSS F32
AL2 VSS VSS AR58 BA18 VSS VSS F33
AL28 AR63 TPAD14-OP-GP TP2306 1 BA2_TP BA2 F35
VSS VSS VSS VSS
AL32 VSS VSS AR8 BA23 VSS VSS F37
AL35 VSS VSS AT2 BA28 VSS VSS F38
AL45 VSS VSS AT28 F68 VSS VSS F42
AL48 VSS VSS AT35 BA45 VSS VSS BA41
AL52 VSS VSS AT4
AL55 VSS VSS AT42
AL58 VSS VSS AT56
AL64 VSS VSS AT58
SKYLAKE-U-GP
071.SKYLA.000U
SKYLAKE-U-GP
071.SKYLA.000U
A <Core Design> A
Wistron Corporation
Title
CPU_(VSS)
A3 A00
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
Main Func = KBC 3D3V_S5

MODEL_ID_DET(GPIO07) PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
3D3V_S5 3D3V_S5_KBC 3D3V_S5_KBC BOARD_ID VERSION A/D PULL-LOW RESISTOR PULL-HIGH RESISTOR VOLTAGE
3D3V_S5_KBC Starlord_UMA_ROR 100.0K 10.0K(64.10025.6DL) 3.0V
EVT (SA) 100.0K 10.0K 3.0V R2442 TBD 100.0K 22.1K(64.22125.6DL) 2.702V
1
64K9R2F-1-GP Starload_UMA_BBY 100.0K 32.4K(64.32425.6DL) 2.492V
1
1D0V_S5 1 R2446 2 R2443 DVT1 (SB) 100.0K 20.0K 2.75V TBD 100.0K 49.9K(64.49925.6DL) 2.201V
DVT2 33KR2F-GP MODEL_ID Starload_DIS_BBY 100.0K 64.9K(64.64925.6DL) 2.001V
1 R2402 2 EC_VTT 0R0603-PAD PCB_REV DVT2 (SC) 100.0K 33.0K 2.48V Starload_17"_UMA 100.0K 93.1K(64.93125.6DL) 1.709V
2
TBD 100.0K 120K(64.12035.6DL) 1.499V
2
0R0402-PAD C2406 R2462 DVT3 (SD) 100.0K 47.0K 2.24V TBD 100.0K 200K(64.20035.6DL) 1.099V
2
0R0402-PAD MODEL_ID
SCD1U16V2KX-3GP
2
BOARD_ID X-build (1) 100.0K 64.9K 2.0V
1
1
2
Just for Starload placement Reserved 100.0K 76.8 1.87V R2441
C2408 R2444 C2407 100KR2F-L1-GP
2015/09/23 modify
2
100KR2F-L1-GP Reserved 100.0K 100.0K 1.65V
SCD1U16V2KX-3GP
1
If don't need RTC alarm wake up,
SCD1U16V2KX-3GP
2
can change to 3D3V_AUX_S5
C2421
C2416
C2420
C2412
C2411
C2410
C2414
C2413
Reserved 100.0K 143.0K 1.358V
2
1
1
Reserved 100.0K 174.0K 1.204V
EC_AGND
SCD1U16V2KX-3GP 2
SCD1U16V2KX-3GP 2
SCD1U16V2KX-3GP 2
SCD1U16V2KX-3GP 2
SCD1U16V2KX-3GP 2
SCD1U16V2KX-3GP 2
SCD1U16V2KX-3GP 2
SCD1U16V2KX-3GP 2
Reserved 100.0K 215.0K 1.048V
EC_AGND
C2423
Layout Note:
1
RTC_AUX_S5
D D
Need very close to EC
SCD1U16V2KX-3GP 2
2
R2472
0R0402-PAD
Just for Starload placement
1
2015/09/23 modify ECVBAT
1
3D3V_AUX_KBC_33
C2428
2
SCD1U16V2KX-3GP
122
103
3D3V_S5_KBC 3D3V_S5_KBC
43
82
19
65
5
KBC24
54
VBAT
VTR
VTR
VTR
VTR
VTR
VTR
VTR_33_18
[65] KSO[0..16]
2
RN2412
1 8 KSO0 R2450 KSO0 2
KSO1 KSO1 GPIO027/KSO00/PVT_IO1 SMBDA1 3D3V_S0
2 7 100KR2J-1-GP 14 8 SMBDA1 [43,44]
KSO2 KSO2 GPIO015/KSO01/PVT_CS# GPIO007/SMB01_DATA/SMB01_DATA18 SMBCLK1 ECVBAT
3 6 15 9 SMBCLK1 [43,44]
KSO3 KSO3 GPIO016/KSO02/PVT_SCLK GPIO010/SMB01_CLK/SMB01_CLK18 SMBDA2
4 5 16 11
1
KSO4 GPIO017/KSO03/PVT_IO0 GPIO012/SMB02_DATA/SMB02_DATA18 SMBCLK2

37
GPIO045/BCM_INT1#/KSO04 GPIO013/SMB02_CLK/SMB02_CLK18
12 Change symbol part number, because origin symbol is DELL OBS part
2
KSO9 KSO5 38 89 SMBDA3
SRN100KJ-5-GP KSO6 GPIO046/BCM_DAT1/KSO05 GPIO130/SMB03_DATA/SMB03_DATA18 SMBCLK3 R2430 R2496
39
GPIO047/BCM_CLK1/KSO06 GPIO131/SMB03_CLK/SMB03_CLK18
91 For Typec SMBUS Q2415
RN2409 KSO7 50 96 SYS_PWROK [17] 10KR2J-3-GP D2403 100KR2J-1-GP
GPIO025/KSO07/PVT_IO2 GPIO141/SMB04_DATA/SMB04_DATA18
2
1 8 KSO4 KSO8 46 97 PBAT_PRES# [43] RB751V-40H-GP [70] KB_CLOSE#_2 S

KSO5 R2449 KSO9 GPIO055/PWM2/KSO08/PVT_IO3 GPIO142/SMB04_CLK/SMB04_CLK18
2 7 68
1
KSO6 KSO10 GPIO102/KSO09/CR_STRAP FAN1_TACH KB_CLOSE#_2_R
3 6
KSO7
DY 100KR2J-1-GP
KSO11
72
GPIO106/KSO10 GPIO050/TACH0
40 A K FAN_TACH1 [26] D
4 5 74 41 LID_CL_SIO# [70]
3D3V_S5_KBC KSO12 GPIO110/KSO11 GPIO051/TACH1 2N7002K-2-GP
75 3D3V_S5_KBC G
1
KSO13 GPIO111/KSO12
SRN100KJ-5-GP KSO14
76
GPIO112/PS2_CLK1A/KSO13 GPIO053/PWM0
44 BKLGT_PWM [65] 83.R2004.G8F 84.2N702.J31
77 45 BEEP [27] 2ND = 84.2N702.031
RN2403 KSO15 GPIO113/PS2_DAT1A/KSO14 GPIO054/PWM1
RN2410 86
KSO8 KSI0 KSO16 GPIO125/KSO15 3rd = 84.07002.I31
1 8 1 8 92 47 FAN1_PWM [26]
GPIO132/KSO16 GPIO056/PWM3
2 7 KSO10 2 7 KSI1 CAP_LED# 93
GPIO140/KSO17 GPIO030/BCM_INT0#/PWM4
34 L_BKLT_EN_EC 4th = 84.2N702.W31
3 6 KSO11 3 6 KSI2 35 EC_WAKE# [17]
[65] KSI[0..7] GPIO031/BCM_DAT0/PWM5
4 5 KSO12 4 5 KSI3 KSI0 98 36 PS_ID [43]
KSI1 GPIO143/KSI0/DTR# GPIO032/BCM_CLK0/PWM6
99 4 VOL_DOWN# [66]
KSI2 GPIO144/KSI1/DCD# GPIO002/PWM7
6
GPIO005/SMB00_DATA/SMB00_DATA18/KSI2 eDP backlight Control from PCH
SRN100KJ-5-GP SRN10KJ-6-GP KSI3 7 1 BAT1_LED#
RN2404 KSI4 GPIO006/SMB00_CLK/SMB00_CLK18/KSI3 GPIO157/LED0/TST_CLK_OUT BAT2_LED# R2435 3D3V_S5
RN2411 104 106
KSO13 KSI4 KSI5 GPIO147/KSI4/DSR# GPIO156/LED1 L_BKLT_EN_EC
1 8 1 8 105 70 SIO_SLP_S3# [17,27,40,51,54] 1 2 L_BKLT_EN [8]
KSO14 KSI5 KSI6 GPIO150/KSI5/RI# GPIO104/LED2 0R0402-PAD
2 7 2 7 107 RN2405
GPIO151/KSI6/RTS#
1
3 6 KSO15 3 6 KSI6 KSI7 108 80 ME_FWP_EC [19] 1 8
KSO16 KSI7 GPIO152/KSI7/CTS# GPIO116/TFDP_DATA/UART_RX HOST_DEBUG_TX R2436
4 5 4 5 81 2 7
GPIO117/TFDP_CLK/UART_TX 100KR2J-1-GP LID_CL_SIO#
[65] CLK_TP_SIO 78 3 6
GPIO114/PS2_CLK0
[65] DAT_TP_SIO 79 90 PTP_DIS# [65] Q2416 [65] TP_EN# 4 5
SRN100KJ-5-GP SRN10KJ-6-GP GPIO115/PS2_DAT0 GPIO035/SB-TSI_CLK PECI_EC
[17] SIO_PWRBTN# 52 94 1 2 H_PECI [4]
2
GPIO026/PS2_CLK1B GPIO033/PECI_DAT/SB_TSI_DAT 3D3V_AUX_S5
SC100P50V2JN-3GP
[17] PCH_RSMRST# 88 R2437 BAT1_LED# 1 6 BATT_WHITE_LED# [64]
GPIO127/PS2_DAT1B
C2405
[18,68] LPC_LAD[3..0] 95 EC_VTT 43R2J-GP SRN100KJ-5-GP
VREF_CPU
1
LPC_LAD0 59 3D3V_S5 2 5 3D3V_S5
GPIO040/LAD0
1
LPC_LAD1 60 101 ICSP_CLOCK DY
LPC_LAD2 GPIO041/LAD1 GPIO145/ICSP_CLOCK ICSP_DATA R2463 BAT2_LED#
61 102 [64] CHG_AMBER_LED# 3 4
2
EMI DVT1 0210 LPC_LAD3 GPIO042/LAD2 GPIO146/ICSP_DATA ICSP_CLR 1KR2J-1-GP R2419
62 87
C GPIO043/LAD3 ICSP_MCLR C
[18,68] LPC_LFRAME# 58
GPIO044/LFRAME# Need very close to EC, PDG: <0.5 inches. 1 2 LCD_TST [55] 2N7002KDW-GP
[17,66,68] PLT_RST# 56 119 EC_MUTE# [27] 0R0402-PAD
2
GPIO064/LRESET# BGPO/GPIO004
1
[18] CLK_PCI_LPC_MEC 57 120 +3VLP Q2412 and Q2413 merge 84.2N702.A3F

GPIO034/PCI_CLK SYSPWR_PRES/GPIO003 ALWON LCD_TST_EN
[18] CLKRUN# 63 121 ALWON [40] LCD_TST_EN [55] 2nd = 84.2N702.E3F
GPIO067/CLKRUN# VCI_OUT/GPIO036
1
C2402 [18] SERIRQ 55 126 KB_CLOSE#_2_R
GPIO063/SER_IRQ VCI_IN1#/GPIO162 3D3V_S5_KBC 3D3V_S5 3rd = 75.00601.07C
2015/09/22 modify
AZ5725-01FDR7G-GP
2 R2510 1 SIO_EXT_SMI# 10
GPIO011/SMI#/EMI_INT# VCI_IN0#/GPIO163
127 POWER_SW_IN# R2454 24014/12/23 modify
DY 10KR2F-2-GP TP_EN# 49
GPIO060/KBRST VCI_OVRD_IN/GPIO164
128 ACOK_IN [44] 100KR2J-1-GP 4th = 84.DMN66.03F
[18] SIO_RCIN# 53
2
GPIO061/LPCPD#
1
SIO_EXT_SCI# 66 23 USB_CHG_EN [34]
2
GPIO100/EC_SCI# GPIO160/DAC_0 DGPU_PWROK_KBC R2471 2
24 OPS 1 0R2J-2-GP R2424 R2434
Layout Note: EC_SPI_CLK 32
GPIO161/DAC_1
22 3D3V_S5_KBC
DGPU_PWROK [66]
20KR2F-L-GP 100KR2J-1-GP
10R2F-L-GP R2405 EC_SPI_MOSI GPIO126/SHD_SCLK DAC_VREF SCD1U16V2KX-3GP C2429 1
Need very close to EC [18,25] SPI_SI_ROM 1 2 28
GPIO133/SHD_IO0
2
RN2406 EC_SPI_MISO 29 85 CMP_VOUT0 CMP_VOUT0 [26]
2
EC_SPI_CLK GPIO134/SHD_IO1 GPIO124/CMP_VOUT0 CMP_VIN0 R2470 2 3D3V_S0
[18,25] SPI_CLK_ROM 1 4 [37] INT#_Typec 30 20 1 0R0402-PAD CMP_VIN0_R [26] USB_EN# USB_EN# [35,66]
EC_SPI_MISO GPIO135/SHD_IO2 GPIO020/CMP_VIN0 VCREF0 Vref = 1.117
[18,25] SPI_SO_ROM 2 3 [18] RTCRST_ON 31 25
GPIO136/SHD_IO3 GPIO165/CMP_VREF0 temp around 85
[18,25] SPI_CS_ROM_N0 27
GPIO123/SHD_CS#
2
SRN10J-8-GP 83 CMP_VOUT1
GPIO120/CMP_VOUT1 HW_ACAVIN_NB# R2489
[17,40,54] SIO_SLP_S4# 67 21
GPIO101/SPI_CLK GPIO021/CMP_VIN1
1
R2404,R2406 merge to RN2406 [43,64] SATA_LED# 69
GPIO103/SPI_IO0 GPIO166/CMP_VREF1/UART_CLK
26 LCD_TST_EN C2409 R2448 100KR2J-1-GP
1
[41] PCH_ALW_ON 71 HW_ACAVIN_NB# R2474 2 DY 1 0R2J-2-GP
2015/10/06 modify GPIO105/SPI_IO1 OVER_CURRENT_P8# [66]
SCD01U50V2KX-1GP
10KR2F-2-GP
[17,60] SIO_SLP_S0# 42 118 USBCHARGER_CB0 [34]
1
GPIO052/SPI_IO2 GPIO024/CMP_STRAP0 CAP_LED#
[4,65] INT_TP# 33 117 PANEL_BKEN_EC [55] S
2
GPIO062/SPI_IO3 GPIO023/ADC6/A20M R2475 2
[66] VOL_UP# 3 116 SIO_EXT_WAKE# [20] 1 0R0402-PAD DC_IN_OK [43]
2
GPIO001/SPI_CS#/32KHZ_OUT GPIO022/ADC5 MODEL_ID
109 D CAP_LED#_R [65]
USB_EN# GPIO153/ADC4 I_ADP
13 110
RESET_IN#/GPIO014 GPIO154/ADC3 BOARD_ID R2494 2
[17,40] ALL_SYS_PWRGD 48 111 DY 1 0R2J-2-GP CMP_VIN0_R [26] For Typec charge detect modfy 2016/01/04 3D3V_S0 G
GPIO057/VCC_PWRGD GPIO155/ADC2
VSS_VBAT
ALL_SYS_PWRGD assert, [17,26] RESET_OUT# 73 113 I_SYS 2N7002K-2-GP

GPIO107/RESET_OUT# VR_CAP GPIO122/ADC1 I_BATT Q2414
delay 10ms; PCH_PWROK assert. GPIO121/ADC0
114 84.2N702.J31
XTAL2
AVSS
125
XTAL2
115 Reserve resistor, 20141118 2ND = 84.2N702.031
VSS
VSS
VSS
VSS
VSS
XTAL1 ADC_VREF 3D3V_S5_KBC

123
XTAL1 3rd = 84.07002.I31
4th = 84.2N702.W31
MEC1404-NU-D0-1-GP-U
124
84
51
17
64
100
112
18
2 R2403 1 0R0402-PAD KB_DISABLE [20,69]

071.01404.0B0E C2422
1
3D3V_S5_KBC 3D3V_S5_PCH
SCD1U16V2KX-3GP
R2497
EC_AGND
2 DY 1
VR_CAP
PCH_DPWROK [17]
2
0R2J-2-GP 2015/09/15 modify
2
1
2015/09/22 modify RN2603
SRN2K2J-1-GP DS3
1
C2418
SC1U10V2KX-1GP
EC_AGND
R2422 I_ADP 2 1 AD_IA [44] 2N7002KDW-GP
2
3
4
X2401 I_SYS 2DY 1 P_SYS [44,46]
1 2 R2421 SMBDA2 6 1
SC2200P50V2KX-2GP
SML1_SMBDATA [18,26,66]
SC10P50V2JN-4GP
SC10P50V2JN-4GP
C2425
C2424
Dummy R2422 & C2427 330R2J-3-GP 330R2J-3-GP
SC2200P50V2KX-2GP
1
XTAL-32D768KHZ-83-GP
C2435
by EC control PCH_DPWROK 84.2N702.A3F 5 DS3 2
1
C2427
082.30003.0131 2nd = 84.2N702.E3F
2
20150416 DY 3rd = 75.00601.07C 4 3
2
R2445 4th = 84.DMN66.03F
2
1 2 Q2604
1
0R0402-PAD
EC_AGND SMBCLK2
EC_AGND
Layout Note: 2 R2407 1 0R0402-PAD HDMI_EC_DET# [57] Move schematic, 20141118 SML1_SMBCLK [18,26,66]
，C = 10p
B B
Microchip: Use CL=9p Xtal EC_AGND Connect GND and AGND planes via either
R2423
0R resistor or connect directly. I_BATT 2 1 BOOST_MON [44]
DY
330R2J-3-GP SMBDA2 R2447 0R2J-2-GP SML1_SMBDATA
1 NON DS3
2
SC2200P50V2KX-2GP
C2441
1
SMBCLK2 R2459 1 NON DS3
2 0R2J-2-GP SML1_SMBCLK
DY Layout Note: Reserve by NON DS3 function 20150413
2
3D3V_S5_KBC
EC_AGND
3D3V_S5_KBC
2
1
RN2604
SRN2K2J-1-GP
Touch Panel PH internally. 3D3V_S0
Q2605
3
4
3D3V_S5_KBC TOUCH_PANEL_INTR# R2429 1 2 10KR2J-3-GP
DY SMBDA3
[37] CCG2_I2C_SDA 3 4
R2418
0R2J-2-GP 3D3V_S5_KBC 84.2N702.A3F
3D3V_S5
2 TypeC5
1 DY 2 R2498,R2499 merge to RN2407 2nd = 84.2N702.E3F
3D3V_S5_KBC
2015/09/22 modify 2015/10/06 modify Just for Starload placement 3rd = 75.00601.07C
1 6
R2480
Q2408 100KR2J-1-GP RN2407 2015/09/23 modify 4th = 84.DMN66.03F
CMP_VOUT1 DB3 VOL_UP# 2N7002KDW-GP
G 4 1
2
7 VOL_DOWN# 3 2 [37] CCG2_I2C_SCL

2
D 1
4K7R2J-2-GP
H_PROCHOT# [4,44,46]
1
SRN10KJ-5-GP SMBCLK3
R2414
R2417 S DY ICSP_CLOCK 2
1
100KR2J-1-GP DY ICSP_DATA
C2403
3 LPC Change symbol part number, because origin symbol is DELL OBS part 20150116 2040
AZ5725-01FDR7G-GP
2N7002K-2-GP 4
1
84.2N702.J31 HOST_DEBUG_TX 5
2
2ND = 84.2N702.031 ICSP_CLR 6

3rd = 84.07002.I31 8
4th = 84.2N702.W31 D2402
2
20.K0691.006 RB751V-40H-GP
ACES-CON6-58-GP LID_CL_SIO# K A
TOUCH_PANEL_INTR# [4,55]
EMI DVT1 0210
83.R2004.G8F
3D3V_S5_KBC
RN2402
SMBCLK1 3 2
SMBDA1 4 1
SRN4K7J-8-GP
A A
Power Switch Logic(PSL)
USBCHARGER_CB0 R2473 1 2 10KR2J-3-GP
PCH_ALW_ON R2495 1 2 100KR2J-1-GP
DS3
ECVBAT
3D3V_S5_KBC
2
PBAT_PRES# R2415 1 2 10KR2J-3-GP

R2451
SIO_EXT_SCI# SIO_EXT_SCI# [16] 100KR2J-1-GP
R2432
SIO_EXT_SMI# SIO_EXT_SMI# [8]
1
[66] KBC_PWRBTN# 1 2 POWER_SW_IN# <Core Design>

C2426
1KR2J-1-GP
1
Just for Starload placement

SC1U10V2KX-1GP Wistron Corporation
2015/09/23 modify 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
2
X00_0804 Title
KBC Nuvoton NPCE285PA0DX
A1
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = SPI Flash

3D3V_S5_PCH
Source QUAD/DUAL fast read DUAL fast read SFDP
1
R2515
0R0402-PAD 72.25128.0B1 O O O
SPI Flash ROM(8M) for PCH 3D3V_S5_PCH 3D3V_SPIVCC1
2
O O O
1
D
3D3V_SPIVCC1 C2501 O O O D
SKT251
SC10U10V5KX-2GPDY DYC2502
2
SPI_CS_ROM_N0 1 8 SCD1U16V2KX-3GP
2
SPI_SO_ROM_R 2 7 SPI_HOLD_ROM_R R2501
SPI_W P_ROM_R 3 DY 6 SPI_CLK_ROM_R 4K7R2J-2-GP
4 5 SPI_SI_ROM_R
1
SKT-G6179HT0321-001-GP Change to Dummy 20150402
62.10089.011
SPI25 3D3V_SPIVCC1
[18,24] SPI_CS_ROM_N0 1 S# VCC 8

SPI_SO_ROM_R 2 7 SPI_HOLD_ROM_R R2503 1 2 10R2F-L-GP
DQ1 HOLD#/DQ3 SPI_HOLD_ROM [18]
SPI_W P_ROM_R 3 6 SPI_CLK_ROM_R
W#/DQ2 C SPI_SI_ROM_R RN2502
4 VSS DQ0 5
SPI_CLK_ROM_R 1 4 SPI_CLK_ROM [18,24]
SPI_SI_ROM_R 2 3 SPI_SI_ROM [18,24]
1
N25Q128A13ESEC0F-GP
EC2501
SC4D7P50V2BN-GP
72.25128.0B1 DY DY EC2503
1
SC10P50V2JN-4GP SRN10J-8-GP
2
EC2502 DY
SC4D7P50V2BN-GP
2

SRN10J-8-GP
2015/10/06 modify
[18,24] SPI_SO_ROM 2 3 SPI_SO_ROM_R
1 4 SPI_W P_ROM_R
C
[18] SPI_W P_ROM C
RN2503

2015/10/06 modify
B B
Main Func = RTC

+RTC_VCC 3D3V_AUX_S5 RTC_AUX_S5
D2501
1
2
1
C2503
BAS40C-2-GP
SCD47U10V2KX-GP
2
75.00040.07D
2nd = 75.00040.C7D
3rd = 75.00040.A7D
Q2505
G
A <Core Design> A
1
D RTC_DET# [20]
R2504
10MR2J-L-GP S
Wistron Corporation
2
2N7002K-2-GP Taipei Hsien 221, Taiwan, R.O.C.

84.2N702.J31
Title
2ND = 84.2N702.031
Flash/RTC
A3 A00
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
Main Func = Thermal Sensor

3D3V_S0 3D3V_S0
PWM FAN1
1
2
RN2602
SRN2K2J-1-GP Short pad change to 0 ohm , 20141118
7718 5V_S0 Layout Note:
3D3V_S0 2N7002KDW-GP Signal Routing Guideline:
4
3
1 R2612 2 FAN_VCC_1
THM_SML1_DATA
Trace width = 15mil
[18,24,66] SML1_SMBDATA 6 1
7718 0R0402-PAD
K
C2604
SC4D7U6D3V3KX-GP
C2605
SCD1U16V2KX-3GP
C2603
SC2200P50V2KX-2GP
C2601
84.2N702.A3F 5 2
SC10U6D3V3MX-GP
1
D2601
RB551V30-1-GP
2nd = 84.2N702.E3F
1
1
D 3rd = 75.00601.07C 4 3
DY DY D
DY 7718C2602 4th = 84.DMN66.03F
2
SCD1U16V2KX-3GP Q2601
2
A
THM_SML1_CLK
[18,24,66] SML1_SMBCLK
84.03904.P11
2nd = 84.03904.T11 FAN1
5
NCT7718_DXP FAN_VCC_1 1
THM261
2
C
Q2603 1 8 THM_SML1_CLK 0R0402-PAD 1 R2613 2 FAN_TACH1_C 3

VDD SCL [24] FAN_TACH1
CH3904PT-GP C2606 7718C2607 THM_SML1_DATA 0R0402-PAD 1 R2614 FAN_PWM1_C
D+ 7718 SDA
B 2 7 [24] FAN1_PWM 2 4
7718 DY SC470P50V3JN-2GP SC2200P50V2KX-2GP 3 6 ALERT# 6
2
T_CRIT# D- ALERT#
4 5
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
E
1
NCT7718_DXN T_CRIT# GND
C2608
C2609
AFTP2604 1 ACES-CON4-29-GP
DY DY 20.F1639.004
2.System Sensor, Put on palm rest NCT7718W-GP
2
74.07718.0B9
1
FAN_TACH1_C 1 AFTP2601
DY 0R2J-2-GP
R2601 Q2602
FAN_PWM1_C 1 AFTP2602
Layout Note: [17,24] RESET_OUT# G
2
C2607 close THM2601 FAN_VCC_1 1 AFTP2603

D
PURE_HW_SHUTDOWN# [40]
THERM_SYS_SHDN# S
SCD1U16V2KX-3GP
1
CMP_VOUT0
C2610
Layout Note: 2N7002K-2-GP
1
R2615
DY 2
0R2J-2-GP DVT1 0210, for T8 function
84.2N702.J31
DY
Both DXN and DXP routing 10 mil trace width and 10 mil spacing.
2
2ND = 84.2N702.031
3rd = 84.07002.I31
4th = 84.2N702.W31
C 3D3V_S0 C
R2603 2 7K5R2F-1-GP ALERT# 3D3V_S5

1 7718
R2604 1 7718 2 7K5R2F-1-GP T_CRIT#
KBC T8 R2607 1 2 10KR2J-3-GP
1 R2602 2 CMP_VOUT0 [24]

0R0402-PAD
Close to KBC
Close to Thermal sensor VD_IN1 for system thermal sensor
3D3V_S0 3D3V_S5_KBC
1
R2609 R2608
27KR2F-L-GP
DY 10R2F-L-GP
DVT1 0210, for T8 function
2
CMP_VIN0_R [24]
1
C2612
1
R2610 SCD1U16V2KX-3GP
NTC-100K-8-GP C2613
2
SC100P50V2JN-3GP
2
VD_IN1_C 1 R2611 2
0R0402-PAD
B B
A A
<Core Design>
Wistron Corporation
Title
THERMAL NCT7718W/Fan
A2
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = Audio
moat
+5V_AVDD 5V_S0
Width>40mil, to improve Headpohone Crosstalk noise R2703

3D3V_S0 +3V_AVDD 1 2
Change it to sharp will be better.
R2731 Add 2 vias (>0.5A) when trace layer change. C2710 0R0603-PAD
1
1 2 C2711
0R0805-PAD
Layout Note: Layout Note:
SCD1U16V2KX-3GP
D D
SC4D7U6D3V3KX-GP
1D8V_S0 CPVDD
2
Place close to Pin 40
1 R2724 2
[29] RING2
0R0402-PAD
[29] SLEEVE moat
AUD_AGND SC10U6D3V3MX-GP 2 1 C2713 MIC_CAP AUD_AGND
MIC2_VREFO_R [29]
EC2707 1 DY 2 SC1KP50V2KX-1GP
C2701 EC2706 1 DY 2 SC1KP50V2KX-1GP
1 MIC2_VREFO_L [29]
1
AUD_PC_BEEP_R 1 R2723 2 AUD_PC_BEEP EC2705 1 DY 2 SCD1U25V2KX-GP
SCD1U16V2KX-3GP C2724 EC2704 1 DY 2 SC1KP50V2KX-1GP
SC4D7U6D3V3KX-GP 0R0402-PAD AUD_HP1_JACK_L [29] EC2703 SCD1U25V2KX-GP
1 DY 2
2
2
[29] LINE1_R
AUD_HP1_JACK_R [29]
Close pin 21 [29] LINE1_L
AUD_AGND
1.5A
5V_S0 +5V_PVDD R2706
1 2
R2702 0R0805-PAD
1 2
0R0805-PAD
36
35
34
33
32
31
30
29
28
27
26
25
C2706 C2707 C2708 C2709 HDA27
1
1
R2704
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
LINE2-L/PORT-E-L
LINE1-L/PORT-C-L
PCBEEP
MIC2-CAP
MIC2-R/PORT-F-R/SLEEVE
MIC2-L/PORT-F-L/RING2
MIC2-VREFO-L
HPOUT-L/PORT-I-L
LINE2-R/PORT-E-R
LINE1-R/PORT-C-R
MIC2-VREFO-R
HPOUT-R/PORT-I-R
1 2
0R0805-PAD
2
AUD_AGND 37 24 CPVEE AUD_AGND Layout Note:

C2705 AVSS1 CPVEE
SC2D2U10V3KX-1GP 1 2 AUD_VREF 38 23 CBN C2703 2 1 SC1U10V3KX-3GP
VREF CBN
2
C2702 1 2 LDO1_CAP 39 22 CBP
AUD_AGND SC10U6D3V3MX-GP LDO1-CAP CBP C2704
40 21
Layout Note: Layout Note: +5V_AVDD CPVDD SC1U10V3KX-3GP
1
R2711 1 AVDD1 CPVDD
2100KR2J-1-GP
Close pin41 Close pin46 +5V_PVDD 41
PVDD1 HPOUT2-R/PORT-B-R
20
AUD_AGND
C
moat AUD_AGND AUD_SPK_L+ 42 19 C
[29] AUD_SPK_L+ SPK-OUT-L+ HPOUT2-L/PORT-B-L
1D8V_S0 AUD_SPK_L-
+3V_1D8V_AVDD Layout Note: [29] AUD_SPK_L-
43
SPK-OUT-L- AVSS2
18 AUD_AGND
SPDIF-OUT/GPIO2/DMIC-DATA34
Speaker trace width >40mil @ 2W4ohm speaker power AUD_SPK_R- 44 17 LDO2_CAP C2712 2 1 SC10U6D3V3MX-GP
[29] AUD_SPK_R- SPK-OUT-R- LDO2-CAP AUD_AGND
3D3V_S0 1D5V_S0 R2713 1 2 0R0402-PAD AUD_SPK_R+ 45 16
[29] AUD_SPK_R+ SPK-OUT-R+ AVDD2 +3V_1D8V_AVDD
R2705 1 DY 2 +5V_PVDD 46 15
5V_S5 PVDD2 LINE1-VREFO-R-E/MONO LINE1_VREFO_R [29]
GPIO0/DMIC-DATA12
0R2J-2-GP
1
R2710 1DY 2 0R2J-2-GP 1 R2725 2 5V_STB 47 14

5VSTB/AUXMODE LINE1-VREFO-L-E LINE1_VREFO_L [29]
GPIO1/DMIC-CLK
HP/LINE1-JD/JD1
C2715
DC-DET/EAPD
SC4D7U6D3V3KX-GP 0R0402-PAD 48 13
moat
2
HP2/LINE2-JD/JD2 LDO3-CAP
SDATA-OUT
LDO3_CAP
+3V_AVDD
SDATA-IN
Close pin16 49
DVDD-IO
GND
R2722
DVDD
SYNC
BCLK
AUD_AGND
AUD_SENSE_A
PD
2 1
C2718
1
ALC3253-CG-GP
10
11
12
100KR2J-1-GP
Azalia I/F EMI Layout Note: D2701
2
+3V_AVDD
SC10U6D3V3MX-GP
Place close to Pin 1 RN2701 HDA_SPKR_R 2
[19] SPKR 2 3 C2720
AUD_PC_BEEP_C 2AUD_PC_BEEP_R
C2719
[24] BEEP 1 4 3 1
HDA_CODEC_SDOUT R2709
HDA_CODEC_BITCLK 2 1 AUD_SENSE_A KBC_BEEP_R 1 SCD1U16V2KX-3GP
1
[29] AUD_SENSE 200KR2F-L-GP SRN1KJ-7-GP
1
EC2708 EC2709 +3V_AVDD
1
BAT54C-7-F-3-GP
SC33P50V2JN-3GP
TP2702 1COMBO-GPI R2717
2
R2728 2K2R2J-2-GP
DY DY
SCD1U16V2KX-3GP
SC33P50V2JN-3GP 2 DY 1
75.00054.E7D
2
+3V_AVDD EAPD#
2
100KR2J-1-GP
1 R2708 2 EAPD#
[24] EC_MUTE# 2nd = 83.R2003.W81
0R0402-PAD C2717
3rd = 75.00054.A7D
1
C2716
EMI suggest change to 33p SC4D7U6D3V3KX-GP SCD1U16V2KX-3GP 4th = 83.R2003.V81
2015/12/02
2
B B
DMIC_DATA_R 0R0402-PAD 1 R2714 2 DMIC_DATA_R

[55] DMIC_DATA CODEC_SDOUT_R R2719
2 1 0R0402-PAD
1 DVSS
EC2701 0R0402-PAD 1 R2716 DMIC_CLK_R HDA_CODEC_SDOUT [19]
2
0R2J-2-GP
1
[55] DMIC_CLK
SC33P50V2JN-3GP
HDA_CODEC_SDIN0 2 R2718 1 0R0402-PAD

HDA_SDIN0 [19]
DY
2
2
HDA_CODEC_SYNC
R2732
C2723 DY
SC33P50V2JN-3GP DY HDA_CODEC_SYNC [19]
1
CODEC_BITCLK_R 2 R2720 1 0R0402-PAD

HDA_CODEC_BITCLK [19]
Close pin6
2
+V1.8A 1D8V_S0
Q2702
DMP2130L-7-GP
150mA
S
D
D
1
G
1
C2722 R2726 C2721

G
SCD1U16V2KX-3GP
10KR2J-3-GP C2714 DY
SCD1U16V2KX-3GP
2
SC1U10V2KX-1GP
2
2
2
1 R2727 2 1D8V_EN_R#
84.02130.031
1D8V_EN#
Q2701 20KR2J-L2-GP
[17,24,40,51,54] SIO_SLP_S3# G 2nd = 84.00102.031

D 3rd = 84.03413.B31
S
2N7002K-2-GP
A A
<Core Design>
Wistron Corporation
Title
Audio Codec ALC3246

A2
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
<Core Design>
Wistron Corporation
Title
(Reserved)
A1
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = Audio
Layout Note: Speaker

Speaker trace width >40mil @ 2W4ohm speaker power
SPK1
( 7
EL2902 2 1 BLM15PD121SN1D-GP AUD_SPK_L+_C 1
D
[27] AUD_SPK_L+ ( CONN Pin Net name D
EL2901
(
1 BLM15PD121SN1D-GP AUD_SPK_L-_C
at high frequencies
2 Resistance element becomes dominant

2
[27] AUD_SPK_L- EL2903 2
( (
1 BLM15PD121SN1D-GP AUD_SPK_R-_C 3 Pin1 SPK_L+
[27] AUD_SPK_R- EL2904 2 ( at high frequencies
(
Resistance element becomes dominant
1 BLM15PD121SN1D-GP AUD_SPK_R+_C 4
[27] AUD_SPK_R+ ( at high frequencies
5 Pin2 SPK_L-
[20] SPK_DET#
at high frequencies
6
8 Pin3 SPK_R-
HR-CON6-1-GP-U Pin4 SPK_R+
20.F1804.006 Pin5 SPK_DET#
1
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
SC100P50V2JN-3GP
Pin6 GND
EC2901
EC2902
EC2903
EC2904
EC2910
EC2912
EC2909
EC2911
2
2
AUD_SPK_L-_C 1 AFTP2901
AUD_SPK_L+_C 1 AFTP2902
AUD_SPK_R-_C 1 AFTP2903
AUD_SPK_R+_C 1 AFTP2904
2015/11/26 modify by EMI suggest
C Universal Jack (Moved to I/O Board) C
RN2901
[27] MIC2_VREFO_R 1 4
[27] MIC2_VREFO_L 2 3
HPMIC1
SLEEVE_R 3
SRN2K2J-1-GP 0R0603-PAD 2 R2906 RING2_R AUD_PORTA_L_R_B
[27] RING2 1 1
R2907 2 1 0R0603-PAD AUD_HP1_JACK_L1 10R2F-L-GP 1 R2908 2 AUD_PORTA_L_R_B
[27] AUD_HP1_JACK_L C2907 1
[27] LINE1_L 2 LINE1-L_C R2922 1 2 0R0402-PAD JACK_PLUG 5
SC10U6D3V3MX-GP R2912 1 DY 2 2K2R2J-2-GP JACK_PLUG_DET 6
[27] LINE1_VREFO_L AUD_PORTA_R_R_B 2
R2909 2 1 0R0603-PAD AUD_HP1_JACK_R1 10R2F-L-GP 1 R2910 2 AUD_PORTA_R_R_B RING2_R 4
[27] AUD_HP1_JACK_R C2908 1
[27] LINE1_R 2 LINE1-L_R R2921 1 2 0R0402-PAD 0R0603-PAD 2 R2911 1 SLEEVE_R MS
SC10U6D3V3MX-GP R2913 1 DY 2 2K2R2J-2-GP Audio(IP/NK comb)
[27] LINE1_VREFO_R
SC100P50V2JN-3GP
EC2908
SC100P50V2JN-3GP
EC2907
SC100P50V2JN-3GP
EC2906
SC100P50V2JN-3GP
EC2905
AUDIO-JK522-GP
10KR2J-3-GP
1
R29191
[27] SLEEVE
1
10KR2J-3-GP
R2920
022.10002.00D1
DY
2 DY
2
DY DY DY DY AUD_AGND
2
2
Delay circuit
B B
(JACK_PLUG_DET: on IO Board)
AUD_AGND AUD_AGND
JACK_PLUG_DET JACK_PLUG 10 mils 1 R2923 2 0R0603-PAD 10 mils

10 mils AUD_SENSE [27]
CLOSS TO HPMIC1
1
1
R2905 DY C2902
0R0402-PAD SC10U6D3V3MX-GP
2
RING2_R
AUD_PORTA_L_R_B
2
JACK_PLUG AUD_AGND
JACK_PLUG_DET
AUD_PORTA_R_R_B
AUD_AGND SLEEVE_R
1
1
AZ2025-01H-R7G-GP
ED2901
AZ5725-01FDR7G-GP
ED2902
AZ5725-01FDR7G-GP
ED2903
AZ5725-01FDR7G-GP
ED2904
AZ5725-01FDR7G-GP
ED2905
AZ2025-01H-R7G-GP
ED2906
1
A <Core Design> A
Wistron Corporation
2

2
Title
Audio IO
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = Audio
D D
C C
(Blanking)
B B
<Core Design>
A
Title
(Reserved)
A4
Starload SKL-U Sheet A00
Date: Thursday, February 18, 2016 30 of 106
5 4 3 2 1
5 4 3 2 1
Main Func = LAN
D D
(Blanking)
C C
B B
A A
<Core Design>
Wistron Corporation
Title
LAN RTL8106
A2
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = LAN
D D
(Blanking)
C C
B B
A <Core Design> A
Wistron Corporation
Title
XFOM&RJ45
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = Card Reader
D D
C C
(Blanking)
B B
A A
<Core Design>
Wistron Corporation
Title
Size
Card Reader-RTS5170
Document Number Rev
A2
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = USB3.0 Port1
D D
USB Charger Port1

USB30_VCCA
5V_S5 USB_OC0# [16,35]
1
C3402 C3403 C3401 C3404 C3405
1
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SC1U10V2KX-1GP
2016/01/11 modify
2
13
12
1
9
U3401
C X02 0414 C
NC#9
FAULT#
IN
OUT
[24] USB_CHG_EN 5 EN DP_OUT 3 USB_CPU_PP0 [16]
DM_OUT 2 USB_CPU_PN0 [16]
5V_S5 R3405 1 2 0R0402-PAD ILIM_SEL 4
R3403 1 ILIM_SEL
DY 2 20KR2F-L-GP ILIM_LO 15 10 USB_PP0_R [36]
R3404 1 2 22K1R2F-L-GP ILIM_HI 16 ILIM_LO
ILIM_HI
DP_IN
DM_IN 11 USB_PN0_R [36]
Device Control Pins
CTL1
CTL2
CTL3
GND
GND
CTL1
CTL2 CTL3 ILIM_SEL
TPS2544RTER-GP (EC control)
6
7
8
14
17
X02 0414 74.02544.073
[24] USBCHARGER_CB0 R3401 1 2 0R0402-PAD CTL1 CDP 1 1 1 1

5V_S5 R3406 1 2 0R0402-PAD CTL2
R3402 1 2 0R0402-PAD CTL3
DCP Auto
0 1 1 X
B B
A <Core Design> A
Wistron Corporation
Title
(Reserved)
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
5V_S5 USB30_VCCB
U3501
5 IN OUT 1
GND 2
1
C3502 C3503 [24,66] USB_EN# 4 3 USB_OC0# [16,34]

EN# OC#
DY Active Low
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
2
SY6288DAAC-GP
074.06288.009B
C USB30_VCCB C
U3502
5 IN OUT 1
GND 2
[24,66] USB_EN# 4 EN#TypeCOC# 3 USB_OC0# [16,34]
SY6288DAAC-GP
074.06288.009B
B B
Layout Note: Close USB3

USB30_VCCB
USB3.0 Port2 2A
100KR2J-1-GP
1
R3501
C3507
C3508
1
C3513 C3514 TC3501

DY C3512 DY SC100U6D3V6MX-GP
SC22U6D3V5MX-2GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
78.10710.52L
2
2
SC1U10V2KX-1GP
SCD1U16V2KX-3GP
2
<Core Design>
A
for starlord placement modify
Title
USB switch
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1

USB2.0 Port2 and USB2.0 Port3 are on IOBD EU3601
USB30_RXDN1_C 1 9 USB30_RXDN1_C
USB3.0 Port1 USB30_RXDP1_C 2 8 USB30_RXDP1_C
3
USB30_TXDN1_C 4 7 USB30_TXDN1_C
USB30_TXDP1_C 5 6 USB30_TXDP1_C
R3605
1 2 USB30_TXDN1_R 1 2 USB30_TXDN1_C ESD3V3U4ULC-GP
[16] USB30_TX_CPU_N1 R3609
C3601 0R0402-PAD USB30_RXDN1_C
83.3V3U4.0A0
D [16] USB30_RX_CPU_N1 1 2 D
SCD1U16V2KX-3GP
0R0402-PAD USB30_VCCA
EU3602
USB20_DN0_C 1 6 USB20_DP0_C
I/O1 I/O4
2 GND VDD 5
3 I/O2 I/O3 4
R3606 R3610
1 2 USB30_TXDP1_R 1 2 USB30_TXDP1_C [16] USB30_RX_CPU_P1 1 2 USB30_RXDP1_C
[16] USB30_TX_CPU_P1 AZC099-04S-1-GP
C3602 0R0402-PAD 0R0402-PAD 75.09904.07C
SCD1U16V2KX-3GP
EMI for DVT1 0212
2nd = 75.02304.07C
USB30_VCCA
[34] USB_PP0_R USB20_DP0_C
USB2
USB 3.0 Connector
1 VBUS D- 2
3
USB20_DN0_C
USB20_DP0_C
Pin definition
DLP11SN900HL2L-GP D+
4 3 USB30_RXDN1_C 5 1 POWER
USB30_RXDP1_C STDA_SSRX-
6 STDA_SSRX+ GND_DRAIN 7
C 1 2 2 USB 2.0 D- C
USB30_TXDN1_C 8
TR3602 USB30_TXDP1_C STDA_SSTX-
9 STDA_SSTX+ GND 10 3 USB 2.0 D+
GND 11
12 CHASSIS#12 GND 4 4 GND
13 CHASSIS#13
5 StdA_SSRX- SuperSpeed RX
[34] USB_PN0_R USB20_DN0_C
SKT-USB13-221-GP 6 StdA_SSRX+
022.10005.01P1
7 GND
8 StdA_SSTX- SuperSpeed TX
9 StdA_SSTX+
USB3.0 Port2
ROR R3611 R3612
[16] USB30_TX_CPU_N2 1 2USB30_TXDN2_R 1 2 USB30_TXDN2_C [16] USB30_RX_CPU_N2 1 2 USB30_RXDN2_C EU3603
C3603 0R0402-PAD 0R0402-PAD USB30_RXDN2_C 1 9 USB30_RXDN2_C

SCD1U16V2KX-3GP USB30_RXDP2_C 2 8 USB30_RXDP2_C
3
USB30_TXDN2_C 4 7 USB30_TXDN2_C
USB30_TXDP2_C 5 6 USB30_TXDP2_C
B B
ESD3V3U4ULC-GP
83.3V3U4.0A0
USB30_VCCB
ROR EU3604
R3614 R3613
[16] USB30_TX_CPU_P2 1 2USB30_TXDP2_R 1 2 USB30_TXDP2_C [16] USB30_RX_CPU_P2 1 2 USB30_RXDP2_C USB20_DN1_C 1 I/O1 I/O4 6 USB20_DP1_C
C3604 0R0402-PAD 0R0402-PAD 2 5

SCD1U16V2KX-3GP GND VDD
3 I/O2 I/O3 4
USB30_VCCB
[16] USB_CPU_PP1 USB20_DP1_C AZC099-04S-1-GP
USB3 75.09904.07C
USB20_DN1_C EMI for DVT1 0212
1 VBUS D- 2
USB20_DP1_C
2nd = 75.02304.07C
D+ 3
DLP11SN900HL2L-GP
USB30_RXDN2_C
4 3
USB30_RXDP2_C
5 STDA_SSRX-ROR
6 STDA_SSRX+ GND_DRAIN 7
1 2
A USB30_TXDN2_C 8 <Core Design> A
TR3603 USB30_TXDP2_C STDA_SSTX-
9 STDA_SSTX+ GND 10
GND 11
12
13
CHASSIS#12
CHASSIS#13
GND 4
Wistron Corporation
USB20_DN1_C Taipei Hsien 221, Taiwan, R.O.C.
[16] USB_CPU_PN1
SKT-USB13-221-GP
Title
022.10005.01P1
USB30
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
VCC3PD VDDD VDDIO
VDDIO VDDD U3701

R3701 1 2 0R0402-PAD
6 VDDD GPIO/VBUS_P_CTRL1 13 I2C_DATA_PD [38]

R3702 1 2 0R0402-PAD
9 14 INT#_Typec_R R3705 1 2 0R0402-PAD VCCPD_VBUS
VDDD_2 GPIO/VBUS_P_CTRL2 INT#_Typec [24]
TypeC
8 17 PD_VBUS_R 100KR2J-1-GP 2 1 R3703
VDDIO GPIO/VBUS_C_CTRL1 R3711 10KR2F-2-GP TypeC R3704
2 1
VDDD PD_VCCD 7 21 PD_CC2_VCONN_CTRL_R 1TypeC 2 PD_CC2_VCONN_CTRL SCD1U16V2KX-3GP 2 1 C3705
VCCD GPIO/VBUS_C_CTRL2 200KR2J-L2-GP
D TypeC D
1
VDDD 24 PD_CC1_VCONN_CTRL_R 1TypeC 2 PD_CC1_VCONN_CTRL
C3704 GPIO/VBUS_DISCHARGE R3712 200KR2J-L2-GP
TypeC
SC1U10V2KX-1GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
3D3V_S5_KBC
SC1U10V2KX-1GP
TypeC
2
TypeC TypeC
1
R3719 1 DY 2 0R2J-2-GP
1
C3701 C3702 C3703
DY R3717 3 PD_RD1 R3718 1 2 0R0402-PAD
2
RD1
1
10KR2F-2-GP
2 PD_CC1 R3709 1 2 0R0402-PAD R3707
CC1 USBC1_CC1_CONN [38] 2K2R2J-2-GP
Typec
2 CC2 1 PD_CC2 R3710 1 2 0R0402-PAD USBC1_CC2_CONN [38]
2
1 R3706 2 CPU_DP_HPD_MUX 23
[8,38] CPU_DP_HPD_R GPIO/VBUS_VMON
0R0402-PAD
18 22 PD_VBUS_DISCHG [43] INT#_Typec_R
[43] PD_VBUS_C_CTRL1 GPIO GPIO/CC2_VCONN_CTRL
15 5V_S5
GPIO/CC1_VCONN_CTRL PD_VBUS_P_CTRL1 [43]
TypeC
20 D3704
[24] CCG2_I2C_SCL I2C_SCL
A K USBC1_CC1_CONN
U3703_OUT
[24] CCG2_I2C_SDA 19 I2C_SDA
VDDD RB551V30-GP
10 U3703
[38] I2C_CLK_PD GPIO/I2C_INT
2 6 83.R5003.H8H
VDDD IN OUT_0
5
SCD1U16V2KX-3GP
OUT_1
RN1814 TypeC TypeC TypeC
OC_1 4 FAULT#
1
I2C_CLK_PD 5V_S5
C3713
C 1 4 1 C
SC10U6D3V3MX-GP
GND
1
2 TypeC 3 I2C_DATA_PD C3714 3 7

R3708 EN PAD
2
4K7R2J-2-GP
VDDD SRN2K2J-1-GP PD_SW D_IO VCONN1 R3720
11 5 1 DY 2 0R2J-2-GP USBC1_CC1_CONN
RN1815
TypeC SWD_IO_HPD VCONN1
074.02141.0073
2
PD_SW D_CLK 12 4 VCONN2 R3721 1 DY 2 0R2J-2-GP

CCG2_I2C_SCL SWD_CLK_I2C_ADDR_SEL VCONN2
1 4
CCG2_I2C_SDA PD_XRES VDDIO TypeC
2 TypeC 3 16 XRES VSS 25 TypeC
D3703
SRN2K2J-1-GP CCG2 24-QFN A K USBC1_CC2_CONN
1
U3704_OUT
C3706 TypeC R3713
SCD1U16V2KX-3GP CYPD2122-24LQXIT-GP 1 2 PD_CC1_VCONN_CTRL RB551V30-GP
TypeC 909KR2F-GP
2
5V_S5 U3704
071.02122.0003 DY 83.R5003.H8H
USBC1_CC1_CONN R3722 1 2 10KR2F-2-GP 2 6
IN OUT_0
5
For Debug USBC1_CC2_CONN DY
OUT_1
R3723 1 2 10KR2F-2-GP OC_2
4
TP3701 FAULT#
1 TPAD14-OP-GP PD_SW D_IO TypeC R3714 1
SC390P50V2KX-GP
SC390P50V2KX-GP
PD_CC2_VCONN_CTRL GND
TypeC TypeC 1 2 3 EN PAD 7
TP3702 1 TPAD14-OP-GP PD_SW D_CLK 909KR2F-GP
1
TP3703 1 TPAD14-OP-GP PD_XRES C3711 C3712
074.02141.0073
2
TypeC
B
For Dead Battery modify 2016/01/08 B
From System
3D3V_S5 D3701 VCC3PD D3702
RB521CM-30T2R-GP-U RB521CM-30T2R-GP-U
A K K A
TypeC
TypeC
VCCPD_VBUS VBUS to 3.3V

U3702
6 1 VREG3PD
IN OUT
5 NC#5 NC#2 2
TPS70933_EN 4 3
EN GND
1
R3715 7 TypeC
909KR2F-GP GND
TypeC
TPS70933DRVR-GP-U C3709
SCD1U16V2KX-3GP
2
1
1
SC1U50V3KX-GP
C3707
074.70933.0033 C3710
SC2D2U10V3KX-1GP
2
RF
1
<Core Design>
301KR2F-1-GP
A TypeC A
1
TypeC R3716 TypeC TypeC

TypeC C3708
SCD1U25V2KX-GP Wistron Corporation
2

2
Title
(Reserved)
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
R3832
Main Func = TYPEC MUX 3D3V_MUX
1 2
0R0402-PAD
MUX_TYPEC_TXP1 C3864 2 SCD1U16V2KX-3GP

1TypeC MUX_TYPEC_TXP1_C TYPEC_CON_TXP1
C3820 TypeC
MUX_CEXT 1 2 MUX_TYPEC_TXN1 C3863 2 SCD1U16V2KX-3GP
1TypeC MUX_TYPEC_TXN1_C TYPEC_CON_TXN1
SC2D2U10V3KX-1GP
41
28
20
6
1
U3801 3D3V_S0 3D3V_MUX 3D3V_S5 R3833
DisplayPort Source DY 1 2
VDD33
VDD33
VDD33
GND
CEXT
R3847 1 2 0R2J-2-GP R3849 1 2 0R0402-PAD
[8] PCH_DPC_P0 C3812 1TypeC
2 SCD1U16V2KX-3GP PCH_DPC_P0_C 9 DY 0R0402-PAD
C3813 SCD1U16V2KX-3GP PCH_DPC_N0_C ML0P R3848 1
[8] PCH_DPC_N0 1TypeC
2 10 2 0R2J-2-GP R3850 1 2 0R0402-PAD
ML0N R3834
C3811 1TypeC
2 SCD1U16V2KX-3GP PCH_DPC_P3_C 18 1 2
[8] PCH_DPC_P3 ML3P
D C3810 1TypeC
2 SCD1U16V2KX-3GP PCH_DPC_N3_C 19 D
[8] PCH_DPC_N3 ML3N 0R0402-PAD
MUX_TYPEC_RXP1 TYPEC_CON_RXP1
Vendor request Tx to Tx ,Rx to RX 1 PORT USB + 4 LANES DP
30 MUX_TYPEC_RXP1 MUX_TYPEC_RXN1 TYPEC_CON_RXN1
USB HOST PS8740B RX1P
31 MUX_TYPEC_RXN1
C3805 SCD1U16V2KX-3GP USB30_RX_CPU_P4_C RX1N
[16] USB30_RX_CPU_P4 1TypeC
2 5
C3806 SCD1U16V2KX-3GP USB30_RX_CPU_N4_C SSRXP MUX_TYPEC_RXP2
[16] USB30_RX_CPU_N4 1TypeC
2 4 40
SSRXN RX2P MUX_TYPEC_RXN2 R3835
39
RX2N
1 2
33 MUX_TYPEC_TXP1
TX1P MUX_TYPEC_TXN1 0R0402-PAD
34
C3803 SCD1U16V2KX-3GP USB30_TX_CPU_P4_C TX1N
[16] USB30_TX_CPU_P4 1TypeC
2 8 TypeC:071.08740.0B03
C3804 SCD1U16V2KX-3GP USB30_TX_CPU_N4_C SSTXP MUX_TYPEC_TXP2 R3836
[16] USB30_TX_CPU_N4 1TypeC
2 7 37
SSTXN TX2P MUX_TYPEC_TXN2
36 1 2
TX2N Maybe connect to KBC
0R0402-PAD
3D3V_MUX
071.08740.0A03
TypeC
R3810 1 2 4K7R2J-2-GP MUX_TYPEC_RXP2 TYPEC_CON_RXP2
C3809 1TypeC
2 SCD1U16V2KX-3GP PCH_DPC_P2_C 15 TP2901
[8] PCH_DPC_P2 ML2P
[8] PCH_DPC_N2 C3808 1TypeC
2 SCD1U16V2KX-3GP PCH_DPC_N2_C 16 29 MUX_EN R3842 1 DY 2 0R2J-2-GP MUX_EN_R 1 TPAD14-OP-GP MUX_TYPEC_RXN2 TYPEC_CON_RXN2
ML2N EN
C3814 1TypeC
2 SCD1U16V2KX-3GP PCH_DPC_P1_C 12 TP2902
[8] PCH_DPC_P1 ML1P
C3807 1TypeC
2 SCD1U16V2KX-3GP PCH_DPC_N1_C 13 23 MUX_SW2_PD R3843 1 2 0R0402-PAD MUX_SW2_PD_R 1 TPAD14-OP-GP
[8] PCH_DPC_N1 ML1N SW2
22 MUX_SW1_PD R3844 1 0R2J-2-GP
TypeC2 0R2J-2-GP R3837
SW1/CSDA I2C_DATA_PD [37]
21 MUX_SW0_PD R3845 1 TypeC2 1 2
SW0/CSCL I2C_CLK_PD [37]
TypeC PS8740BQFN40GTR-A0-GP
C3801 1 2 SCD1U16V2KX-3GP DPB_AUXP_C 24 27 USBC_DPAUX1 0R0402-PAD
[8] DPB_AUXP
C3802 1TypeC
2 SCD1U16V2KX-3GP DPB_AUXN_C 25
AUXP SBU1
26 USBC_DPAUX2 From USB PD Controller
[8] DPB_AUXN AUXN SBU2
32 MUX_HPD_PD R3846 1 2 0R0402-PAD R3838
DPEQ/ADDR1
SSEQ/ADDR0
IN_HPD CPU_DP_HPD_R [8,37]
3D3V_MUX 1 2
3D3V_MUX
TypeC
I2C_EN
SSDE
REXT
R3801 1 2 100KR2J-1-GP DPB_AUXN_C 0R0402-PAD
CEQ
CDE
MUX_SW2_PD R3812 1 DY 210KR2J-3-GP
R3802 1 2 100KR2J-1-GP DPB_AUXP_C MUX_SW1_PD R3813 1 DY 210KR2J-3-GP
TypeC MUX_SW0_PD R3814 1 DY 210KR2J-3-GP MUX_TYPEC_TXP2 C3861 1TypeC
2 SCD1U16V2KX-3GP MUX_TYPEC_TXP2_C TYPEC_CON_TXP2
17
11
14
38
35
3
2
MUX_I2C_EN R3811 1 2 4K7R2J-2-GP
C MUX_TYPEC_TXN2 C3862 1TypeC
2 SCD1U16V2KX-3GP MUX_TYPEC_TXN2_C TYPEC_CON_TXN2 C
3D3V_MUX TypeC
MUX_REXT
3D3V_MUX
MUX_I2C_EN
MUX_DPEQ
MUX_SSEQ
MUX_SSDE
EN N/A Internal PD at ~150Kohm, 5V tolerent
MUX_CEQ
MUX_CDE
R3824 1 DY 2 4K7R2J-2-GP MUX_SSDE R3839
L: Chip Power Down (default)
TypeC TypeC TypeC TypeC TypeC 1 2
R3823 1DY 2 4K7R2J-2-GP H: Normal Operation
1
C3815 C3816 C3817 C3818 C3819 0R0402-PAD
1
R3803
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
4K99R2F-L-GP For Pin Control Mode (I2C_EN=L)

3D3V_MUX
TypeC
2
1 PORT USB + 4 LANES DP
2
R3822 1 DY 2 4K7R2J-2-GP MUX_SSEQ
PS8740B Normal Flipped
R3821 1 TypeC 2 4K7R2J-2-GP
SW2 H H
TR3805 068.24900.2001
SW1 L L 1 4 USBC_CON_PN3
[16] USB_CPU_PN3
3D3V_MUX SW0 L H 2 TypeC3 USBC_CON_PP3
[16] USB_CPU_PP3
USB Type-C connector facing TX channel De-emphasis setting; Internal tied to VDD33/2, 3.3V I/O.
R3820 1 DY 2 4K7R2J-2-GP MUX_CDE FILTER-4P-156-GP-U
CDE= VCCPD_VBUS
R3819 1 DY 2 4K7R2J-2-GP L: Programmable DE Level#1
H: Programmable DE Level#2
M: Programmable DE Level#3 (default)
EU3801
3D3V_MUX
TypeC
1
C3821 TYPEC_CON_TXP1 1 9 TYPEC_CON_TXP1
SCD1U25V2KX-GP
R3818 1 TypeC 2 4K7R2J-2-GP MUX_CEQ USB Type-C connector facing RX channel De-emphasis setting; Internal tied to VDD33/2, 3.3V I/O. TypeC TYPEC_CON_TXN1 2 8 TYPEC_CON_TXN1
CEQ= 3
2
R3817 1 DY 2 4K7R2J-2-GP TYPEC_CON_RXP1 4 7 TYPEC_CON_RXP1
L: Programmable EQ Level#1 USBC1_CC1_CONN TYPEC_CON_RXN1 5 6 TYPEC_CON_RXN1
H: Programmable EQ Level#2
USBC1_CC2_CONN
M: Programmable EQ Level#3 (default)
ESD3V3U4ULC-GP
3D3V_MUX
83.3V3U4.0A0
DP Receiver equalization setting; Internal tied to VDD33/2, 3.3V I/O. EU3802
R3816 DY 2 4K7R2J-2-GP MUX_DPEQ VCCPD_VBUS VCCPD_VBUS
1 DPEQ= TypeC
2
B TYPEC_CON_RXN2 1 9 TYPEC_CON_RXN2 B
R3815 1 DY 2 4K7R2J-2-GP L: Programmable EQ Level#1 ED3801 TYPEC_CON_RXP2 2 8 TYPEC_CON_RXP2
H: Programmable EQ Level#2 AZ5315-02F-GP 3
USB1 TYPEC_CON_TXN2 TYPEC_CON_TXN2
M: Programmable EQ Level#3 (default) TypeC TYPEC_CON_TXP2
4 7
TYPEC_CON_TXP2
A1 B1 5 6
TYPEC_CON_TXP1 GND GND TYPEC_CON_TXP2
A2 B2
3
TYPEC_CON_TXN1 SSTXP1 SSTXP2 TYPEC_CON_TXN2

A3 B3
SSTXN1 SSTXN2 ESD3V3U4ULC-GP
A4 B4
VBUS#A4 VBUS#B4
[37] USBC1_CC1_CONN USBC_CON_PP3
A5
CC1 CC2
B5
USBC_CON_PP3 USBC1_CC2_CONN [37] 83.3V3U4.0A0
A6 B6
USBC_CON_PN3 DP1 DP2 USBC_CON_PN3
A7 B7
USBC_DPAUX1 DN1 DN2 USBC_DPAUX2
A8 B8
RFU1 RFU2 EU3803
A9 B9
TYPEC_CON_RXN2 VBUS#A9 VBUS#B9 TYPEC_CON_RXN1
TYPEC_CON_RXP2
A10
SSRXN2 SSRXN1
B10
TYPEC_CON_RXP1 USBC_DPAUX1
TypeC USBC_DPAUX1
A11 B11 1 9
1
SSRXP2 SSRXP1 USBC_DPAUX2 USBC_DPAUX2
A12 B12 2 8
GND GND
1
R3831 3
R3830 NP1 TypeC 2MR2F-GP 4 7
2MR2F-GP NP1
NP2
NP2 TypeC 5 6
TypeC
2
13
2
CHASSIS#13 ESD3V3U4ULC-GP
16 14
GROUND CHASSIS#14
17
GROUND CHASSIS#15
15 83.3V3U4.0A0
18 20
GROUND CHASSIS#20
19 21
GROUND CHASSIS#21
22
CHASSIS#22 EU3804
SKT-USB36-9-GP-U 2 USBC_CON_PP3
022.10005.02U1
3
USBC_CON_PN3
TypeC 1
AZ5315-02F-GP
83.05315.0A0
A A
<Core Design>
Wistron Corporation
Title
(Reserved)
A2
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
<Core Design>
Wistron Corporation
Title
(Reserved)
A2
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = Power Plane & Sequence Power Good 3D3V_S0
1
R4005
R4011 1KR2J-1-GP
[51] 1D2V_VTT_PWRGD 1 2
0R0402-PAD
2
ROSA Run Power RSMRST_PWRGD#
D4002
3
1
83.00016.K11
ALL_SYS_PWRGD [17,24]
DY R4002 1 2 0R0402-PAD VR_EN [46]

2
BAS16-6-GP
3D3V_S5 3D3V_S5_KBC
Remove Q4001 & R4004 by Hsync 5V_S5
5V_S5 5V_S0 [#543016] Optional, Added for addition system robustness
D
20150417 U4001
5V_S0 D
1
R4031 R4032
4 13
VBIAS OUT1#13 100KR2J-1-GP 100KR2J-1-GP
14
1
OUT1#14 3V5V_CT1
CT1
12 3D3V_S0 5V_S0 Comsumption DY
C4005
SC10U10V5KX-2GP
1
R4010 2
IN1#1
8 Peak current 5A
2
IN1#2 OUT2#8
1 2 3V5V_S0_ON 3 9
[17,24,27,51,54] SIO_SLP_S3#
0R0402-PAD EN1 OUT2#9
CT2
10 3V5V_CT2
3D3V_S0 RSMRST_PWRGD#
C4002
SC470P50V2KX-3GP
C4001
SC470P50V2KX-3GP
3D3V_S5 6 [52] 1D0V_S5_PWRGD R4029 1 2 0R0402-PAD
IN2#6
1
7
IN2#7 GND
11 3D3V_S0 Comsumption
C4004
SC10U10V5KX-2GP
5 15 [54] 1D8V_S5_PWROK R4030 1 2 0R0402-PAD
EN2 GND Peak current 2.5A
2
[17,45,52,54] 3V_5V_POK R4033 1 DY 2
G5016KD1U-GP 0R2J-2-GP
074.05016.0093 NON DS3: PH 3V_5V_POK to 3D3V_AUX_S5 at page17
VCCIO and VCCSTG

Modify power switch IC and relate schematic
2016/01/07
+VCCIO_SIP +VCCIO
5V_S5
SC1U10V2KX-1GP
C4032
D4001
1
2 1 R4045 2
[45] 3V_5V_EN 1 3 PURE_HW_SHUTDOWN# [26]
2
0R1206-PAD
U4002 +VCCSTG
1
C
LBAS16LT1G-GP R4042 C
R4006 1 8 1 2
20KR2F-L-GP VIN VOUT#8 0R0402-PAD
2 7
83.00016.P11 VIN VOUT#7
C4008
R4017 3 6
SCD1U16V2KX-3GP
1
VCCSTG_EN_R VBIAS VOUT#6
1 2 4 5
2
[17,24,27,51,54] SIO_SLP_S3# 0R0402-PAD EN GND
C4007
DY
SCD1U16V2KX-3GP
1
R4009 1 2 10KR2J-3-GP ALWON [24] 9 1D0V_S5
2
VIN
C4033
SC1U10V2KX-1GP
2
1
1
C4009
APE8939GN3-GP C4006
SC10U6D3V3MX-GP
DY 074.08939.0093 SC10U6D3V3MX-GP
1
2
DVT1 0210
2
modify at DVT1 power sequence 20150203
20150116 2032
3D3V_S5 3D3V_S0
EOPIO and EDRAM 5V_S5 1D0V_S5

U4004
+V_EDRAM_VR
+V_EDRAM_VR
V1.8S
1
1 8 V_EDRAM_EOPIO_R 1 R4021 2 Voltage = 1.0 V ± 50 mV

1
VIN#1 VOUT#8
10KR2J-3-GP
10KR2J-3-GP
R4028 R4027 2 7
[#543977 Rev1.1] PDDG change to ALL_SYS_PWRGD VIN#2 VOUT#7 0R1206-PAD Imax = 6 A Imax = 3.2 A
DY 3
VBIAS VOUT#6
6
MS EN_EDRAM_VR 4
ON GND
5 Rds on = 4.65mohm TRISE = 240 us
+V1.8S_EDRAM
2016/02/24 modify +V1.8A
2
Q4009
23e 9 1D0V_S5
2
1D0V_S5 VIN#9 DMP2130L-7-GP
R4018 1 DY ALL_SYS_PWRGD_R R4019 1 TPS22961DNYT-GP V_EDRAM_EOPIO_R 100mA

2 2 S
B
[17,24,27,51,54] SIO_SLP_S3#
0R2J-2-GP 0R2J-2-GP NON MS/23e 074.22961.0093 1D0V_S5
+V_EOPIO_VR 23e D B
D
G
G
D4003
1
1
R4044 RB521CM-30T2R-GP-U Q4001 C4011 C4010 Voltage = 1.0 V ± 50 mV 23e C4029 R4046
SC10U10V5KX-2GP
1
SCD1U16V2KX-3GP
[17,24] ALL_SYS_PWRGD 1 2 K A SSM3K15AMFV-GP-U C4015 23e DY 23e10KR2J-3-GP 23e C4023 84.02130.031 C4028
Imax = 2.8 A
SCD1U16V2KX-3GP
2
1
SCD1U16V2KX-3GP
0R0402-PAD MS SC1U10V2KX-1GP
SC1U10V2KX-1GP
DY R4043 23e
2
2
[6] ZVM# S D EN_EDRAM_VR 23e TRISE = 240 us 2nd = 84.00102.031
2
1 23e 2 1D8S_EN_R#
2
V_EDRAM_EOPIO_R +V_EOPIO_VR
3rd = 84.03413.B31
1D8S_EN#
D4004 Q4008 20KR2J-L2-GP
RB521CM-30T2R-GP-U [17,24,27,51,54] SIO_SLP_S3# G
K A 2 R4022 1
DY 0R1206-PAD 23e D
MANAGEMENT RAIL POWER GENERATION VCCST, VCCSTG, and VCCPLL can remain powered during S4 and S5 power states for board VR optimization. 2N7002K-2-GP
+V1.00U_CPU
3D3V_S5 R4036 +VCCST_CPU
VCCST 1 2
SCD1U16V2KX-3GP
0R0402-PAD
C4014 R4038 +VCCSFR
3D3V_S5 1 2
1
0R0402-PAD 0.04 A
DY
Modify power switch IC and relate schematic ,DVT1 20150204
2
U4005 R4026 1D0V_S5

DY 10KR2J-3-GP
1 5
NC#1 VCC
2
C4013
SC10U10V5KX-2GP
[17,24,54] SIO_SLP_S4# 2
A
1
DY VCCSTU_EN
3 4
GND Y
2
EC4001 +V1.00U_CPU
1
74LVC1G07GW-GP DY U4006
A A
73.01G07.0HG
SCD1U16V2KX-3GP
1 8
2
R4024 VIN#1 VOUT#8

2 7
R4023 VCCSTU_EN VCCSTU_EN_R VIN#2 VOUT#7 U4006_CT
1 2 3 6
1
0R0402-PAD ON CT C4012
1 2 5V_S5 4 5
0R0402-PAD VBIAS GND SC10U6D3V3MX-GP
C4017
SCD1U16V2KX-3GP
9 <Core Design>
2
1
GND
1
DY
Wistron Corporation
1
SC1U10V2KX-1GP
C4034
DY TPS22965DSGR-GP-U
2
SC1U10V2KX-1GP
C4031
DY 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

2

2
Title
Power Plane Enable

A2
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = Power Plane & Sequence
3D3V_S5 3D3V_S5_PCH
R4101
D D
1NON DS3
2
0R5J-5-GP Reserve by NON DS3 function 20150413
3D3V_S5 Obs reason:

For new project,
pls help to use cost down version
SY6288C10CAC for instead.
C4102
1
U4101_OUT 3D3V_S5_PCH
SC1U10V2KX-1GP
2
DS3 U4101 R4103 Add 0603 0ohm

C 0R3J-0-U-GP C
U4101_OUT 1 20141114
1 GND OUT#8 8 2
2 IN#2 OUT#7 7
DS3 3 IN#3 OUT#6 6 DS3
[24] PCH_ALW_ON 1 2 DS3_PWRCTL 4 EN DS3 OC# 5
R4102 C4101
1
0R2J-2-GP
SC1U10V2KX-1GP
SY6288C10CAC-GP
074.06288.0079 (OBS)
2
DS3
RdsON: 100m ohm
DS3
B B
<Core Design>
A
Title
Connected_Standby(1/2)+DS3
A4
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = DIMM1

Main Func = DIMM2
D D
C C
B B
A <Core Design> A
Wistron Corporation
Title
Connected_Standby(2/2)
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = ADT Input 5V_S5
1
PR4302 3D3V_S5
84.03904.P11
15KR2F-GP PQ4302 PR4303
E
10KR2J-3-GP
1
PQ3802_1 B 3D3V_S5
1
CH3904PT-GP
2
2
PD4302
1
PR4309 PSID_DISABLE#_R_C LBAV99LT1G-1-GP
100KR2J-1-GP PR4304
75.00099.O7D 2K2R2J-2-GP
Layout Note: 2nd = 75.00099.K7D
G
1
3
PSID Layout width > 25mil
2
84.05067.031 3rd = 75.00099.Q7D
PR4317 PR4305
D
PS_ID_R 1 2 PS_ID_R2 D S PS_ID_R1 1 2
4th = 75.00099.D7D D
PS_ID [24]
0R0603-PAD
20140815 david 33R2J-2-GP
PQ4301
EL4304
1
DMN5L06K-7-GP
1 2 PD4303 PR4306
JGND L30ESD24VC3-2-GP 1 DY 2
0R5J-5-GP
Do Not Stuff
Pin Definition: TBD EL4303
3
1 2
DCIN1 0R5J-5-GP
9 60ohm@100MHz
+SDC_IN
1
DCR=0.02 ohm
Max current = 6000mA
2 1 AFTP4301
3 1 AFTP4302 +DC_IN AD+
4 PU4301 TypeC PU4302
5 EL4301 1 S D 8 8 D S 1
+DC_IN_C S D D S
PC4305
PC4303
PC4304
PC4306
240KR3-GP
6 1 2 2 7 7 2
SC10U25V3MX-GP
SCD01U50V2KX-1GP
1
Do Not Stuff
Do Not Stuff
7 0R5J-5-GP PC4302 3 S D 6 6 D S 3
K
1
1
SC1U50V3KX-GP
PC4301
PR4314 SCD1U50V3KX-GP G D D G
EC4302
PR4307
PR4316
PR4318
8 4 5 5 4
EC4301
SC10U25V3MX-GP
SCD1U25V2KX-GP
20KR2J-L2-GP
100KR2J-1-GP
1
PD4301 DY DY
10 DY 3K3R6J-GP SD103AWS-2-GP SI7121DN-T1-GE3-GP
1
PR4311 84.07121.037
2
2
1
SI7121DN-T1-GE3-GP 100KR2F-L1-GP
2
ACES-CON8-13-GP-U1 PR4312 NON_TypeC
470KR2F-GP PQ3809_D
20.F1295.008 TypeC
84.2N702.A3F PQ4305 NON_TypeC
47KR2F-GP
EL4302
2
1
R2
2nd = 84.2N702.E3F PQ4304 2 Id=-9.6A
2
JGND JGND 1 2 AD_OFF_L
PR4308
0R5J-5-GP 3rd = 75.00601.07C C 1 R1 Qg=-25nC PD4305
2016/01/07 mofiy 4th = 84.DMN66.03F B R1 3 AD_OFF_R DC_IN_OK A K
PQ4306
2
Rdson=18~30mohm ACOK_IN_M [17,44]
DY R2
E DY
LTA024EUB-FS8-GP
3 4 RB751V-40-2-GP
2
AC_IN#_G LMUN5212T1G-GP
If=0.3A
PR4315
18K7R2F-GP
DC_IN_OK 2 5
NON_TypeC +SDC_IN_SW_R1 1 2 +SDC_IN_SW
1
C 1 6 PD_VBUS_C_CTRL1_A PR4333 C
10KR2F-2-GP
1
2N7002KDW-GP
PR4313 20150520_ EC097
TypeC 71K5R2F-1-GP
AC_DIS
+SDC_IN
2
DY dischange schematic AC_DIS change to SATA LED function 2016/02/03 modify VCCPD_VBUS
USB_ADT
TypeC TypeC
PU4303 PU4304
R4302 2 DY 1 0R2J-2-GP 1 S D 8 8 D S 1 +SDC_IN
SC100P50V2JN-3GP
[24,64] SATA_LED# S D 7 D S
2 7 2 TypeC
680KR2J-GP
2
1
S D 6 D S
PD_VBUS_C_CTRL1 = 1 (Consumer Path OFF) 3 6 3
2
R4303 1 0R2J-2-GP G D 5 D G PR4320
PR4336
2
PD_VBUS_C_CTRL1 = 0/Z (Consumer Path ON) TypeC 4 5 4
PC4310
240KR2F-L-GP
TypeC SI7121DN-T1-GE3-GP SI7121DN-T1-GE3-GP
1
84.07121.037 84.07121.037
2
VCC3PD USB_ADT_SW
AFTP4303 1 +DC_IN_C USB_TYPEC_R USB_ADT
AFTP4304 1 PS_ID_R 3D3V_S5 VCCPD_VBUS
47KR2F-GP
240KR2F-L-GP
10KR2F-2-GP
2
1
AFTP4305 1 +DC_IN_C
1
PR4337
PR4321
TypeC TypeC
2
PR4322
TypeC PR4319
TypeC
1
PQ4311 100KR2F-L1-GP TypeC +SDC_IN_SW_R1

PR4335 4 3 TypeC TypeC 12K4R2F-GP
1
2
100KR2J-1-GP PQ4307 PQ4308 PR4327
2
VBUS_PRODECT# USB_TYPEC_SW PQ4310 USB_ADT_SW_R
TypeC 5 2 4 3 3 4
1
4 3
2
U4302 6 1 PD_VBUS_C_CTRL1_A 5 2 DC_IN_OK 2 5

DC_IN_OK 5 2
AC_IN#_G 5 1 DC_IN_OK 2N7002KDW-GP 6 1 1 6 USB_ADT_R1
SENSE OUT DC_IN_OK [24]
2 84.2N702.A3F VBUS_PRODECT USB_TYPEC_DIS 6 1
100KR2F-L1-GP
IC_DELAY VDD 2N7002KDW-GP 2N7002KDW-GP
CD TypeC
4 3
VSS
1
2N7002KDW-GP
PR4332
84.2N702.A3F 84.2N702.A3F PD4306
SC100P50V2JN-3GP
TypeC
PC4311
84.2N702.A3F TypeC A K
1
ACOK_IN_M [17,44]
074.01004.00BF
1
2
[37] PD_VBUS_C_CTRL1
TypeC RB751V-40-2-GP TypeC
2
PC4307 TypeC
2
SCD15U10V2KX-GP 100R2512J-1-GP
TypeC 2K2R2J-2-GP
2
1
B PR4338 PD_VBUS_DISCHG [37] PR4328 B
TypeC PR4323
If=0.3A
TypeC
1
100KR2F-L1-GP
1
VCCPD_VBUS
USB30_VCCB
2
PU4305 PU4306
8 D S 1 TYPEC_5V_SW 1 S D 8
7 D S 2 2 S D 7
6 D S 3 3 S D 6
5 D D 5
240KR2F-L-GP
G G
2
SI7625DN-T1-GE3-GP SI7625DN-T1-GE3-GP
Main Func = M-BAT Input
4
2
PR4330
TypeC TypeC
SCD1U25V2KX-GP
PC4312
TypeC
1
Placement: Close to Batt Connector
1
BT+
Batt Connecter TypeC
TYPEC_5V_SW_R
SMBCLK1
PR4339
PBAT_PRES#
SMBDA1
K
1
64K9R2F-1-GP
1
EC4308
DY DY EC4307 DY PD4304 TypeC
Do Not Stuff

2
PQ4309
A
2
PR4310 4 3 TYPEC_5V
3
BATT1 1KR2J-1-GP
1 NP1 D4304 D4305 D4306 1 2 PD_VBUS_P_CTRL1_R 5 2 VBUS_PRODECT
[37] PD_VBUS_P_CTRL1
RN4302
LBAV99LT1G-1-GP LBAV99LT1G-1-GP LBAV99LT1G-1-GP TypeC
2 75.00099.O7D 75.00099.O7D 75.00099.O7D 6 1
4 5 3
1
3 6 PBAT_SMBCLK1 4 2N7002KDW-GP
[24,44] SMBCLK1 PD_VBUS_P_CTRL1 = 1 (Provider Path ON) PD_VBUS_DISCHG = 1 (VBUS Discharging)
1
2 7 PBAT_SMBDAT1 5 PR4324 84.2N702.A3F

[24,44] SMBDA1 PD_VBUS_P_CTRL1 = 0/Z (Provider Path OFF) PD_VBUS_DISCHG = 0/Z (VBUS not discharging)
PBAT_PRES1# 100KR2F-L1-GP
[24] PBAT_PRES# 1 8
1 R4301 2 SYS_PRES1#
6 Id=115mA
SRN100J-4-GP 0R0402-PAD
7 TypeC TypeC
8
2
9 VCCPD_VBUS VCC3PD
3D3V_S5_KBC
10 NP2
2nd = 75.00099.K7D 2nd = 75.00099.K7D 2nd = 75.00099.K7D
240KR2F-L-GP
1
2
A ETY-CON10-28-GP A
PR4331
PR4334
3rd = 75.00099.Q7D 3rd = 75.00099.Q7D 3rd = 75.00099.Q7D 124KR2F-GP
EC4309 EC4310 EC4306 20.F2460.010 TypeC TypeC
4th = 75.00099.D7D 4th = 75.00099.D7D 4th = 75.00099.D7D
1
2
Do Not Stuff
Do Not Stuff
1 AFTP4306
2
1
Do Not Stuff
DY DY DY 1 AFTP4307 U4301
<Core Design>
1 AFTP4308
2
U4301_IN 5 1 VBUS_PRODECT
SENSE OUT
2
4
CD
VDD
VSS
3 Wistron Corporation
1
VCC3PD 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

PBAT_PRES1# AFTP4309 PR4329
TypeC
1 Taipei Hsien 221, Taiwan, R.O.C.
PBAT_SMBDAT1 1 AFTP4310 100KR2F-L1-GP
PBAT_SMBCLK1 1 AFTP4311 TypeC 074.01004.00BF Title
BT+ 1 AFTP4312
DCIN
2
BT+ 1 AFTP4313
BT+ 1 AFTP4314 TypeC Protect circuit Size Document Number Rev
SYS_PRES1# 1 AFTP4315 A2
2015/11/26 modify Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = Charger
+SDC_IN DCBATOUT
PR4402
D01R3721F-GP-U
1 2
D D
1
PG4402 PG4403
GAP-CLOSE-PWR-6-GP GAP-CLOSE-PWR-6-GP
2
2PG_1
1PG_2
PR4414
PR4444 2R2F-GP
0R0402-PAD DCBATOUT CHARGER_SRC
PG4404
PC4402 Do Not Stuff
2
SCD1U25V2KX-GP 2 1
1 2 USB_ADT
PG4405 TypeC
Do Not Stuff
2 1 PD4409 DCBATOUT
K A
PG4406
1
PC4403 PC4404 Do Not Stuff PWR_CHG_PHASE_1 DCBATOUT RB751V-40-2-GP
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
PWR_CHG_ACP
PWR_CHG_ACN
DY DY 2 1
PU4403 If=0.3A
2
PG4407 PD4411 EC4425
1
Do Not Stuff 8 D S 1 PC4434 K A AD+
SC2D2U10V2KX-GP
2 1 7 D S 2 SC2200P50V2KX-2GP DY
USB_ADT PD4407 6 D S RB751V-40-2-GP
3 1 DY2
If=0.3A
2
RB751VM-40TE-17-GP 5 D G 4 USB_ADT_D1
If=0.3A
A K
DCBATOUT SI7121DN-T1-GE3-GP
TypeC
1
CHARGER_SRC
USB_ADT_D
PR4442
Vf=0.25V @ 30mA 84.07121.037 470KR2J-L1-GP
PR4410 PR4403
PD4406 1KR2F-3-GP 100R5F-2-GP
RB751VM-40TE-17-GP 2 1 PWR_VBAT 1 2 BT+
2
Do Not Stuff
AD+ A K RF request 2016/01/12 modify
SC1KP50V2KX-1GP
SCD22U25V3KX-GP
Do Not Stuff
1
PC4405 PC4406 PC4407 PC4408 PC4409
Vf=0.25V @ 30mA
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U25V2KX-GP
PC4410
PC4411
SC1KP50V2KX-1GP
1
1 PC4426
PC4437
2
1
1
DY DY
1 PC4436
VAC DET
2
VDD PR4408
2
Greater than 2.633 V 300KR2F-GP BT+
100KR2F-L2-GP
Less than 3.5 V
2
1
PR4471
SCD1U50V3KX-GP
PWR_CHG_BATDRV
PWR_ASGATE 2
5
6
7
8
C PWR_CHG_ACDET PC4435 PC4415 PC4433 C
PWR_CHG_ACN
PWR_CHG_ACP
PWR_CMSRC
D
D
D
D
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
PU4404
PC4416
3D3V_S5_KBC AC_IN:3.35~3.75V VDD
PWR_OPCN
PWR_OPCP
SIS412DN-T1-GE3-GP
2
PQ4415
84.00412.037
1
ACOK#
4 3 PC4413 PWR_CHG_REGN
1
PR4409
SC2D2U10V2KX-GP
G
S
S
S
[24] ACOK_IN ACOK_IN 5 2 37K4R2F-1-GP
2
2
4
3
2
1
2
32
31
30
29
28
27
26
25
[17,43] ACOK_IN_M 6 1
1
1
PR4438 PR4439 PR4445 PR4443 PR4422 PU4401 PL4401 PR4415
2
10KR2F-2-GP
10KR2F-2-GP
100KR2F-L2-GP
300KR2F-L-GP
100KR2F-L2-GP
2N7002KDW-GP D01R3721F-GP-U BT+
VBAT
CSIN
CMSRC
QPCN
CSIP
ASGATE
QPCP
BGATE
DY DY DY 84.2N702.A3F PWR_CHG_PHASE 1 2 1 2
2nd = 84.DM601.03F COIL-4D7UH-33-GP
3rd = 84.2N702.E3F PR4447 PC4414 68.4R71A.20H
2
1
4th = 84.2N702.F3F 0R0603-PAD SCD22U25V3KX-GP PC4418 PC4419
PC4417
SC10U25V5KX-GP
SCD1U25V2KX-GP
Do Not Stuff 1 24 PWR_CHG_BTST 1 2PWR_CHG_BTST1 1 2
5
6
7
8
ACIN BOOT
SC10U25V3MX-2-GP
PG4412 PG4413
2
D
D
D
D
PG4408 PWR_CHG_ACOK PWR_CHG_HIDRV PU4405
GAP-CLOSE-PWR-6-GP
GAP-CLOSE-PWR-6-GP
2 1 2 23
ACOK UGATE
SIS412DN-T1-GE3-GP
2
PG4409 1 2 GAP-CLOSE-PWR-6-GP PWR_CHG_SDA 3 22 PWR_CHG_PHASE
[24,43] SMBDA1 SDA PHASE 84.00412.037
PG4410 1 2 GAP-CLOSE-PWR-6-GP PWR_CHG_SCL 4 21 PWR_CHG_LODRV
SCL LGATE
G
S
S
S
ISL95521AHRZ-T-GP
PWR_CHG_SRN_1
PWR_CHG_SRP_1
PG4419 2 1 Do Not Stuff PWR_CHG_PROCHOT# 5 20 PWR_CHG_REGN VDD PR4412
4
3
2
1
PROCHOT# VDDP 4D7R3F-L-GP
[24,43] SMBCLK1 Change MLCC size to release spacing to EE placement
[24] AD_IA PG4401 2 1 Do Not Stuff PWR_CHG_IADP 6 19 VDD 1 2
AMON VDD
PG4414
074.95521.0A73
[24] boost_mon 2 1 Do Not Stuff PWR_CHG_IDCHG 7 18 PWR_CHG_VCC
1
PG4415 BMON DCIN PC4428 PC4431
SC1U10V2KX-1GP
SC1U10V2KX-1GP
[4,24,46] H_PROCHOT# [24,46] P_SYS 2 1 PWR_CHG_PMON8 17 PWR_CHG_NTC
PSYS NTC
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
2
BATGONE
Do Not Stuff PR4411
PC4423
PC4424
PC4430
PR4401
SC2K2P50V2JX-GP
1
1
PR4437 2R2F-GP PR4448
1KR2F-3-GP
CCLIM
ACLIM
COMP
PROG
CSON
1
CSOP
49K9R2F-L-GP
FSET
33 0R0402-PAD
GND
2
PD4405 USB_ADT PC4420
1
PR4407 RB751VM-40TE-17-GP SCD1U25V2KX-GP
10
11
12
13
14
15
16
2
1 2 PWR_CHG_1 K TypeCA 1 2 DY
2
2D2R5J-1-GP If=0.3A PC4421
1
PC4412 PD4402 AD+ SC2200P50V2KX-2GP PC4422
PWR_CHG_BATPRES#
SC2200P50V2KX-2GP
SC1U50V5ZY-1-GP-U RB751VM-40TE-17-GP DY
K A
PWR_CHG_COMP
PWR_CHG_PROG
2
PWR_CHG_FSET
PWR_CHG_REGN If=0.3A
PD4401 BT+
PWR_CHG_ILIM
RB751VM-40TE-17-GP
K A
1
PR4420 PR4421 If=0.3A

10KR2F-2-GP
10KR2F-2-GP
PWR_CHG_SRP
B PWR_CHG_SRN B
2
ACLIM
100R2F-L1-GP-U
0R0402-PAD
1 PR4430
1
PR4416
1
PR4423 PR4424
SC560P50V2KX-2GP
100KR2F-L1-GP
100KR2F-L1-GP
150KR2F-L-GP
AD+
DY DY
1
1
PC4427
PR4433
1 PR_2 2
DY
2
SCD022U25V2KX-GP
100KR2J-1-GP
PR4431
2
1
PC4432
1
PR4449
2
1KR2F-3-GP
2
2
1
PR4436
Do Not Stuff
Switching frequency is 350KHz DY
E PQ4408_E
H_PROCHOT# [4,24,46]
2
PD4404
PR4455 84.2N702.A3F
L1SS355T1G-GP 0R0402-PAD 2nd = 84.DM601.03F
K APD4403_A B 3rd = 84.2N702.E3F
PQ4408 4th = 84.2N702.F3F
1
PQ4405
PD4403_K MMBT3906-4-GP
C
PQ4405_3 3 4
2
PR4458 84.T3906.A11 PR4462
2nd = 84.03906.P11 PQ4408_C 2 1 PQ4405_2 2 5 PQ4405_5
0R0402-PAD
PC4438
SC1U10V2KX-1GP
0R0402-PAD 1 6
1
2N7002KDW-GP
2
PR4451 PR4463
680KR2F-GP Do Not StuffDY
DCBATOUT
PQ4405_6
2
2 PWR_CHG_ACOK
2
1
PR4413
PR4450 100KR2F-L1-GP
10KR2F-2-GP
A CHECK EE 3D3V_S5 A
1
follow custormer circuits.
2
<Core Design>
Wistron Corporation
Title
Size Document Number

Charger Rev
D
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
3D3V_AUX_S5
SSID = PWR.Plane.Regulator_5V
1
PWR_5V 5V_S5
PR4503
PG4507
Do Not Stuff DY Do Not Stuff
1 2
3V_5V_POK
[17,40,52,54]
2
PR4530 PR4504
PG4508
2 DY 1 PWR_5V_EN1_R 1 2 PWR_5V_EN1
5V_AUX_S5 Do Not Stuff
Do Not Stuff 0R0402-PAD 1 2
2
PR4515
PG4509
2
0R0402-PAD PR4510 PG4529
DCBATOUT PWR_DCBATOUT_5V Do Not Stuff
1
100KR2J-1-GP
Do Not Stuff
PG4501 DY 1 2
Do Not Stuff PR4516
1
D 1 2 D
1 2 PWR_3D3V_EN1 PG4510
2
[40] 3V_5V_EN
0R0402-PAD Do Not Stuff
PG4502 1 2
Do Not Stuff
PWR_DCBATOUT_5V PU4502
1 2
2
IN#2
PG
9 PWR_5V_PG
PC4521 MagLayer. 6.86 x 6.47 x 3.0mm
Design Current=7A PG4511
Do Not Stuff
PR4502 SCD1U25V2KX-GP
PG4503 PWR_5V_BOOT1 PWR_5V_BOOT_A DCR: 14~15mOhm 10.5A<OCP>12.6A 1 2
1
Do Not Stuff PC4522 3 1 2 1 2
IN#3 BS
1
Idc : 9A , Isat : 18A
SCD1U25V2KX-GP
1 2 DY PC4523 PC4505 PC4519
4 0R0603-PAD
PG4512
IN#4
SC10U25V3MX-2-GP
SC10U25V3MX-2-GP
SC10U25V3MX-2-GP
2
Do Not Stuff
2
5 PWR_5V
PG4504 IN#5 PL4502 1 2
Do Not Stuff
6 PWR_5V_PH 2 1
1 2 LX#6
IND-1UH-94-GP-U PG4513
PWR_5V_PG 10 19
NC#10 LX#19 Do Not Stuff
PG4505
1
1 2
1
Do Not Stuff 20
16
LX#20
Trace used 10 mil DY PC4518 PC4514 PC4515 PC4516 PC4517 PC4527 PC4528 PC4529
SCD1U16V2KX-3GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SCD1U16V2KX-3GP
SC22U6D3V5MX-2GP
1 2 NC#16
SY8288CRAC-GP
PG4527 DY DY PG4514
2
Do Not Stuff
2
PWR_5V_VOUT Do Not Stuff
PG4506 14 1 2
PWR_5V_VCC OUT PC4526 PR4507 1 2
Do Not Stuff 17
VCC SC1KP50V2KX-1GP 1KR2F-3-GP
1 2 PWR_5V_FB 2 PWR_5V_FB_A
1
PC4524 13 1 1 2
FF
SC2D2U10V3KX-1GP
12 PG4528 5V_AUX_S5
EN1 Do Not Stuff
2
PWR_5V_EN1
11 15 PWR_5V_LDO 1 2
EN2 LDO
1
PR4513 PC4520
1
EN rating 25V PC4531 1MR2J-1-GP SC4D7U25V5KX-GP
GND
GND
GND
GND
Do Not Stuff
EN Rising Threshold : 0.8V
2
DY PWR_5V_FB
18
21
Ilimt : 8A
1
PR4551
348KR2F-GP
C C
PR4511
1KR2F-3-GP
2
1 2 PWR_5V_EN
DCBATOUT
DY DY
1
1
PR4512 PC4530
Do Not Stuff
Do Not Stuff
2
2
SSID = PWR.Plane.Regulator_3D3V
Design Current=5A PWR_3D3V 3D3V_S5

DCBATOUT PWR_DCBATOUT_3D3V
B
PG4515
PR4501 PC4506
SCD1U25V2KX-GP
7.5A<OCP>9A PG4519
Do Not Stuff
B
Do Not Stuff PWR_3D3V_BOOT 1 PWR_3D3V_BOOT_A 1

MagLayer. 6.86 x 6.47 x 3.0mm 1 2
2 2
1 2 DCR: 14~15mOhm
0R0603-PAD PL4501
PWR_DCBATOUT_3D3V PU4501 COIL-1D5UH-43-GP
Idc : 9A , Isat : 18A PWR_3D3V PG4520
Do Not Stuff
PG4516
Do Not Stuff PWR_3D3V_PH 1 2
2 6 1 2
IN#2 LX#6
1 2 3 19
IN#3 LX#19
4 20 DY PG4521
1
1
IN#4 LX#20 PC4513 PC4509 PC4510 PC4511 PC4525 PC4512
1
PC4501 PC4502 5
DY PC4503 PC4504 IN#5 Do Not Stuff
SCD1U16V2KX-3GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
Do Not Stuff
PG4517 10 PWR_3V_PG
SCD1U25V2KX-GP
NC#10 1 2
SC10U25V3MX-2-GP
SC10U25V3MX-2-GP
SC10U25V3MX-2-GP
Do Not Stuff 12 15
2
2
PWR_3D3V_EN EN1 NC#15 PWR_3D3V_LDO
2
1 2 11 16
EN2 NC#16
PG4522
PWR_3D3V_BOOT 1
BS Do Not Stuff
PG4518 PWR_3V_PG 9 7
Do Not Stuff PWR_3D3V_FB PG GND 1 2
13 8
FF GND
1 2 14 18
OUT GND
17 21 PG4523
LDO GND 3D3V_AUX_S5
Do Not Stuff
PG4532
PWR_3D3V_EN1 1 2
SY8286BRAC-GP Do Not Stuff
1
PR4514 PWR_3D3V_LDO 1 2
1MR2J-1-GP
PG4524
Do Not Stuff
1
PC4532 PC4507
1 2
Do Not Stuff
SC4D7U6D3V3KX-GP
2
DY PR4509 Trace used 10 mil

2
1KR2F-3-GP PG4530
DCBATOUT 1 2 Do Not Stuff
PWR_3D3V_VOUT 1 2
DY DY
1
PR4508 PC4508 PC4533 PR4506

Do Not Stuff
Do Not Stuff
EN rating 25V SC1KP50V2KX-1GP 1KR2F-3-GP

DCBATOUT 1 2 PWR_3D3V_FB2 2 1
2
EN Rising Threshold : 0.8V

PR4505
2
100KR2J-1-GP
Ilimt : 8A 3D3V_AUX_S5 1 2
A A
PG4531
EC4534
Do Not Stuff
1
1 2
SC2D2U10V2KX-GP
DY [17,40,52,54] 3V_5V_POK
2
<Core Design>
Wistron Corporation
RF request 2016/01/12 modify Title
(Reserved)
A2
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = CPU_CORE
PR4611
27K4R2F-GP
1 2
PC4632
1 2
SC1KP50V2KX-1GP
PR4602
D PC4602 81208_AGND D
1 2 PWR_VCCSA_COMP_R 1 2 PWR_VCCSA_CSN [50]
2
1K5R2F-2-GP SCD015U25V2KX-GP
PC4607 PC4606
SCD01U50V2KX-1GP
SCD01U50V2KX-1GP PR4606
1
PC4604 NTC-100K-1-GP-U
1
1 2 PR4609
PC4603 14K3R2F-GP 69.60028.011
2
SC1KP50V2KX-1GP SC15P50V2JN-2-GP
1
PWR_VCCSA_VSN_R 1 2 1 2 PWR_VCCSA_CSN_NTC
81208_AGND
PR4605 PR4612
[7] VSSSA_SENSE PR4604 1 2 0R0402-PAD 1 2 1 2 PWR_VCCSA_CSP [50]
8K06R3F-AS-GP 3D3V_S0
825R2F-GP
2
PC4605 PR4613 2 1 93K1R2F-L-GP
1
SC1KP50V2KX-1GP
PR4608 PR4614
1
2K61R2F-1-GP PC4609 1 2 SC220P50V2KX-3GP DY Do Not Stuff
[7] VCCSA_SENSE PR4607 1 2 0R0402-PAD 1 2
2
81208_AGND PR4670 1 2 0R0402-PAD VR_RDY 1 AFTP4601
PWR_VCCSA_VSP_R 1 2 1 2
PR4616 PR4630 1 2 0R0402-PAD
0R0402-PAD PC4608 VR_EN [40]
SC1KP50V2KX-1GP +VCCST_CPU
PWR_VCCSA_VSP_RC PR4671 1 2 0R0402-PAD PSYS
[24,44] P_SYS
PR4615 2 1 20KR2F-L-GP
Do Not Stuff
PR4622
100R2F-L1-GP-U
PR4623
1
PC4610
81208_AGND SCD1U25V2KX-GP +VCCST_CPU +VCCSTG Check +VCCST_CPU or +VCCSTG
2
[7] VCCGT_SENSE 0R0402-PAD 1 2 PR4617
1
45D3R2F-L-GP
PR4621
DY
1
PC4611 [#543016]
SC1KP50V2KX-1GP
1
C PR4619 C
[7] VSSGT_SENSE 0R0402-PAD 1 2 PR4618 2 1 1KR2F-3-GP PR4624 PR4669
Do Not Stuff
VR_SVID_CLK [7] DY DY Do Not Stuff
PWR_VCCGT_VSN_R 1 2 VR_SVID_ALERT# [7]
2
PC4612 SC2200P50V2KX-2GP PG4601 VR_SVID_DATA [7]
Do Not Stuff
[50]
[47,48,50]
PR4668
PWR_VCCSA_PWM
2 1
PWR_VCORE_DRVON
1
PR4665
PR4666
PR4667
1 2 H_PROCHOT# [4,24,44]
PR4625 100R2F-L1-GP-U
37D4R2F-GP
81208_AGND
PWR_VCORE_VR_RDY
1
PWR_VCCSA_CSP1B
PWR_VCCSA_COMP
2
PWR_VCCSA_IOUT
49D9R2F-GP
0R0402-PAD
10R2F-L-GP
PWR_VCCGT_VSN
PWR_VCCSA_VSN
PWR_VCCGT_VSP
PWR_VCCSA_VSP
PR4626 PC4613 2 SC470P50V2KX-3GP
PWR_VCCSA_ILIM
1
PWR_VCORE_EN
1
PWR_VCCGT_FB_R 1KR2F-3-GP PR4627
1 2 1 2 PWR_VCORE_CSP [47]
1
PR4628 8K06R3F-AS-GP
PR4632
2
PC4614 110KR2F-GP
SC470P50V2KX-3GP 1 2 81208_AGND
PR4629
2
2
81208_AGND
26K1R2F-2-GP 1 2 PWR_VCORE_CSNNTC
1
PWR_VCORE_VRHOT#
PWR_VCORE_ALERT#
2
PR4631 14KR2F-GP
49
48
47
46
45
44
43
42
41
40
39
38
37
PWR_VCORE_SCLK
PWR_VCORE_SDIO
PC4617 4K75R2F-1-GP 1 2 PU4601
1
1
SC10P50V2JN-4GP PC4634 PC4616 PR4633
PSYS
VSP_1B
VSN_1B
COMP_1B
ILIM_1B
CSN_1B
CSP_1B
IOUT_1B
VR_RDY
GND
VSN_2PH
VSP_2PH
EN
PWR_VCCGT_ILIM_R
PC4615 SCD022U25V2KX-GP SCD01U50V2KX-1GP NTC-100K-1-GP-U

2
SC470P50V2KX-3GP 69.60028.011
2
2
PWR_VCCGT_COMP_R
1
PR4634 81208_AGND PWR_VCORE_CSN [47]
1
1 2 PC4618 PWR_VCCGT_IOUT 1 36
PR4637 SC2200P50V2KX-2GP PWR_VCCGT_DIFFOUT IOUT_2PH PWM_1B
2 35 1 2
2
PR4638 NTC-220K-5-GP-U PWR_VCCGT_FB DIFFOUT_2PH DRVON PR4635

3 34
48K7R3F-1-GP 165KR2F-GP PWR_VCCGT_COMP FB_2PH SCLK
4 33
PWR_VCCGT_ILIM COMP_2PH ALERT# 59KR2F-GP
[48] PWR_VCCGT_CSPA 1 2 2 1 1 PR4639 2 2 1 5 32
PR4640 PWR_VCCGT_CSCOMP ILIM_2PH SDIO SC1500P50V2KX-2GP
22/23e 6 31
1
PC4620 PWR_VCCGT_CSSUM CSCOMP_2PH VR_HOT# PWR_VCORE_IOUT PC4633 81208_AGND

7 30
75KR2F-GP SC1KP50V2KX-1GP PC4621 12K4R2F-GP PWR_VCCGT_CSREF CSSUM_2PH IOUT_1A PWR_VCORE_CSP_1A PC4601 PWR_VCORE_COMP_R
8 29 1 2 1 2 1 2
PR4641 SC100P50V2JN-3GP CSREF_2PH CSP_1A SC1KP50V2KX-1GP PR4636
9 28
2
CSP2_2PH CSN_1A PWR_VCORE_ILIM 2K49R2F-GP

[48] PWR_VCCGT_CSPB 1 23e 2 10 27
73K2R3F-1-GP CSP1_2PH ILIM_1A PWR_VCORE_COMP PC4623 PC4619
11 26 1 2 SC15P50V2JN-2-GP
ROSC_COREGT
TSENSE_2PH COMP_1A
ADDR_VBOOT
B 12 25 PWR_VCORE_VSN 2 1PWR_VCORE_VSN_R 81208_AGND B
TSENSE_1PH
ICCMAX_2PH
VRMP VSN_1A
ROSC_SAUS
PR4643 2 1 10R2F-L-GP
ICCMAX_1A
ICCMAX_1B
23e
PWM1_2PH
PWM2_2PH
[48] PWR_VCCGT_CSNB
5V_S5 SC1KP50V2KX-1GP
PWR_VCORE_VRMP
PWM_1A
VSP_1A
1 2 PR4645 2 1 0R0402-PAD VSS_SENSE [7]
1
PR4644
VCC
1
1
[48] PWR_VCCGT_CSNA PR4646 2 1 10R2F-L-GP PC4624 PC4622 PR4642 422R2F-2-GP
SCD033U25V2KX-GP 1KR2F-3-GP
23eSCD033U25V2KX-GP 22 PC4625
SC1KP50V2KX-1GP
NCP81208MNTXG-4-GP PR4647
2
13
14
15
16
17
18
19
20
21
22
23
24
2
1 2 PR4648 2 1 0R0402-PAD VCC_SENSE [7]
2
PWR_VCCGT_CSP2 3K83R2F-GP
1
PWR_VCORE_VCC_R
PWR_VCORE_ROSC_SAUS
PC4626 PWR_VCCGT_CSP1 PWR_VCORE_VSP 2PWR_VCORE_VSP_RC PWR_VCORE_VSP_R

PWR_VCORE_ROSC_COREGT
1 1 2
SCD01U50V2KX-1GP PWR_VCCGT_TSENSE PR4649 PR4650
2
2K49R2F-GP PC4627 0R0402-PAD

DCBATOUT PWR_VCORE_TSENSE SC1KP50V2KX-1GP 2 1 PWR_VCORE_NTC
PR4651 81208_AGND PR4601 PWR_VCORE_PWM [47]
[48] PWR_VCCGT_CSPA 2 1 1KR2F-3-GP PWR_VCORE_ADDR_BOOT
2
1 2 PWR_VCCSA_ICCMAX
1
6K98R2F-GP PWR_VCORE_ICCMAX PR4652
PWR_VCCGT_ICCMAX PC4628 12K7R2F-GP PR4653
[48] PWR_VCCGT_CSPB 2 23e 1
1
SCD1U25V2KX-GP NTC-100K-1-GP-U
2
PR4654 PC4629 69.60028.011
2
6K98R2F-GP SCD01U50V2KX-1GP
2
1
PWR_VCCGT_NTC 1 2 PR4672 PR4658 PR4660 PR4663
U22 15W U23e 15W PR4655 22/23e
48K7R2F-2-GP
90K9R2F-GP
19K1R2F-GP
10KR2F-2-GP
0R0402-PAD 81208_AGND 81208_AGND
2
5V_S5
1
1
1
PR4662 48K (64.48725.55L) 73.2K (64.73225.55L) PR4656 PR4657

NTC-100K-1-GP-U PR4661 PC4630 2D2R2F-GP PR4664 PR4659
PR4641 Dummy 73.2K (64.73225.55L) 12K7R2F-GP SCD1U25V2KX-GP 1 2 24KR2F-GP 24KR2F-GP
2
PR4640 12.4K (64.12425.6DL) 16.9K (64.16925.6DL)

69.60028.011
2
2
1
1
PR4672 48.7K (064.48725.06DD) 100K (64.10035.6DL) PC4631

SC1U10V2KX-1GP 81208_AGND
2
PR4658 90.9K (64.90925.6DL) 100K (64.10035.6DL)

81208_AGND PWR_VCCGT_PWMB [48]
PR4635 59K (64.59025.6DL) 59K (64.59025.6DL) 81208_AGND 81208_AGND 81208_AGND
PWR_VCCGT_PWMA [48]
PR4628 110K (64.11035.6DL) 110K (64.11035.6DL)
A A
PR4643 Dummy 10R (64.10R05.6DL)
PR4654 Dummy 6.98K (64.69815.6DL)
PC4624 Dummy D33U (78.33322.2FL)

<Core Design>
PR4642 1K (64.10015.6DL) Dummy
PR4602 1.5K (64.15015.6DL) 1.5K (64.15015.6DL) Wistron Corporation

PC4602 15n (78.15322.2FL) 15n (78.15322.2FL)
Title
NCP81208MN_CPU_VCORE(1/3)
A2 Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1

DCBATOUT
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U25V2KX-GP
PC4710
1
D PC4702 PC4703 PC4701 PC4704 PC4705 D
2
PR4701
1 2 PW R_VCORE_BOOT_RC
PWR_VCORE_BOOT
3D9R3-GP
1
5V_S5 PC4706
SCD22U25V3KX-GP
PR4702
2
2D2R2F-GP
25
26
27
28
29
30
33
35
1
2 1 PW R_VCORE_VCC PU4701
THWN
VIN
VIN
VIN
VIN
VIN
VIN
GH
BOOT
1
PC4708 VCC_CORE
SC1U10V2KX-1GP 6
2
C VCC PW R_VCORE_PHASED C
PHASED 34 PL4701
7 VCCD PHASEF 32
1
PC4707 12 PW R_VCORE_SW 1 2
SC2D2U10V2KX-GP VSW#12
5 13
2
CGND VSW#13
VSW#14 14 COIL-D15UH-2-GP
VSW#15 15
[46] PW R_VCORE_PW M
4 PWM VSW#16 16 68.R1510.20A
PR4704 17 PT4701
PW R_VCORE_DISB# 2 VSW#17
1 2 DISB# VSW#18 18
1
[46,48,50] PW R_VCORE_DRVON
SE330U2VDM-L-GP
0R0402-PAD 36 ZCD_EN
1
5V_S5 PG4707 PG4708
DY
2
Do Not Stuff
Do Not Stuff
3 PR4703
1
SMOD# Do Not Stuff
DY
GL#10
GL#11
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
GL#8
GL#9
2
NCP81382MNTXG-3-GP PW R_VCORE_SNUB
8
9
10
11
19
20
21
22
23
24
31
37
1
PC4709
PW R_VCORE_GL Do Not Stuff
DY
2
Confirm with EE:
22uF/0603 total 35pcs (DY 5 pcs)
B B
[46] PW R_VCORE_CSP
[46] PW R_VCORE_CSN
A <Core Design> A
Wistron Corporation
Title
NCP81382MN_CPU_VCORE(2/3)
5 4 3 2 1
5 4 3 2 1
DCBATOUT
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U25V2KX-GP
PC4811 DCBATOUT
1
PC4802 PC4803 PC4804 PC4805 PC4806
D D
1
PT4805 PT4806
SE33U25VM-11-GP SE33U25VM-11-GP
2
PR4802
1 2
PWR_VCCGT_BOOTA
3D9R3-GP PWR_VCCGT_BOOTA_RC
For acoustic noice
5V_S5
1
PC4809
SCD22U25V3KX-GP
PR4803
2
2D2R2F-GP
25
26
27
28
29
30
33
35
1
2 1 PWR_VCCGT_VCCA PU4801
THWN
VIN
VIN
VIN
VIN
VIN
VIN
GH
BOOT
1
PC4808
SC1U10V2KX-1GP 6
2
VCC PWR_VCCGT_PHASEDA +VCCGT
34 PL4801
PHASED
1 7 32
VCCD PHASEF
PC4807 12 PWR_VCCGT_SWA 1 2
SC2D2U10V2KX-GP VSW#12
5 13 COIL-D15UH-2-GP Confirm with EE:
2
CGND VSW#13
VSW#14
14 68.R1510.20A 22uF/0603 total 35pcs (DY 5 pcs)
15
VSW#15
1 PT4801
4 16
[46] PWR_VCCGT_PWMA PR4808 PWM VSW#16
17
PWR_VCCGT_DISB#_A VSW#17
1 2 2 18
2
[46,47,50] PWR_VCORE_DRVON DISB# VSW#18
0R0402-PAD 36
1
5V_S5 ZCD_EN PG4808 PG4809
Do Not Stuff
Do Not Stuff
3 PR4804
2
SMOD# Do Not Stuff
C
DY C
GL#10
GL#11
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
GL#8
GL#9
79.33719.L01
SE330U2VDM-L-GP
2
NCP81382MNTXG-3-GP
8
9
10
11
19
20
21
22
23
24
31
37
PWR_VCCGT_SNUB_1
1
PWR_VCCGT_GL1
PC4810
Do Not Stuff
DY
2
[46] PWR_VCCGT_CSPA
[46] PWR_VCCGT_CSNA
DCBATOUT SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U25V2KX-GP
PC4812
1
1
PC4820 PC4829 PC4830 PC4828 PC4827
23e 23e 23e 23e 23e 23e
2
2
B PR4805 B
1 23e 2
PWR_VCCGT_BOOTB
3D9R3-GP PWR_VCCGT_BOOTB_RC
5V_S5
1
PC4845
23e SCD22U25V3KX-GP
PR4806
2
2D2R2F-GP
25
26
27
28
29
30
33
35
1
2 23e 1 PWR_VCCGT_VCCB PU4802

THWN
VIN
VIN
VIN
VIN
VIN
VIN
GH
BOOT
1
PC4847 23e
SC1U10V2KX-1GP 6
2
VCC PWR_VCCGT_PHASEDB +VCCGT

34 PL4802
PHASED
7 32
VCCD PHASEF
1
PWR_VCCGT_SWB
23e
PC4846 23e 12 1 2
SC2D2U10V2KX-GP VSW#12 COIL-D15UH-2-GP
5 13
2
CGND VSW#13
23e VSW#14
14 68.R1510.20A
15
VSW#15
4 16
[46] PWR_VCCGT_PWMB PWM VSW#16
1 PT4802
1 PT4803
PR4809 17
PWR_VCCGT_DISB#_B VSW#17
1 23e 2 2
DISB# VSW#18
18
2
2
[46,47,50] PWR_VCORE_DRVON
0R2J-2-GP 36
ZCD_EN
1
PG4815 PG4816
Do Not Stuff
Do Not Stuff
5V_S5 3 PR4807
1
1
SMOD# Do Not Stuff
DY DY 23e
2
GL#10
GL#11
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
GL#8
GL#9
SE330U2VDM-L-GP
2
Do Not Stuff
NCP81382MNTXG-3-GP
8
9
10
11
19
20
21
22
23
24
31
37
PWR_VCCGT_SNUB_2
1
A PWR_VCCGT_GL2 A
PC4814
Do Not Stuff
DY
2
<Core Design>
[46] PWR_VCCGT_CSPB
Wistron Corporation
[46] PWR_VCCGT_CSNB Title

NCP81382MN_CPU_VCCGT(3/3)
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
<Core Design>
Wistron Corporation
Title
NCP81210MN_CPU_VCCGTUS
5 4 3 2 1
5 4 3 2 1
DCBATOUT DCBATOUT_+VCCSA
PG5023
D 2 1 D
GAP-CLOSE-PW R
PG5024
2 1
GAP-CLOSE-PW R
DCBATOUT_+VCCSA
PC5029 PC5027 PC5002
1
SC10U25V5KX-GP
SC10U25V5KX-GP
SCD1U25V2KX-GP
5
6
7
8
PR5013
2
D
D
D
D
1 2 PW R_VCCSA_BST_RC PU5002
SIS412DN-T1-GE3-GP #544669 Intel CRB Rev0.53
2D2R3-1-U-GP +VCCSA(ICCMAX.=6A)
PWR_VCCSA_BST
G
S
S
S
PC5008
SCD22U25V3KX-GP PW R_+VCCSA +VCCSA
4
3
2
1
2
PW R_+VCCSA
C PU5001 PG5026 C
PL5001
2 1
1 8 PW R_VCCSA_DRVH
BST DRVH PW R_VCCSA_SW GAP-CLOSE-PW R
2 PWM SW 7 1 2
[46] PW R_VCCSA_PW M 3 6 PG5025
[46,47,48] PW R_VCORE_DRVON EN GND
5V_S5 4 VCC DRVL 5 COIL-D47UH-6-GP 2 1
1
9 GAP-CLOSE-PW R
GND
1
PR5014 PG5028
PC5001 2D2R5F-2-GP 2 1
DY
5
6
7
8
2
SC2D2U10V3KX-1GP NCP81253MNTBG-1-GP
2
D
D
D
D
074.81253.0AE3 PU5003 GAP-CLOSE-PW R
2
PG5021 PG5022
PWR_VCCSA_SNUB
SIS412DN-T1-GE3-GP PG5027
GAP-CLOSE-PWR-3-GP
GAP-CLOSE-PWR-3-GP
2 1
1
GAP-CLOSE-PW R
G
S
S
S
PG5030
2 1
4
3
2
1
PW R_VCCSA_DRVL GAP-CLOSE-PW R
PG5029
1
2 1
PC5031
DY SC2200P50V2KX-2GP GAP-CLOSE-PW R
2
PG5031
2 1
GAP-CLOSE-PW R
B B
Confirm with EE:

[46] PW R_VCCSA_CSP 22uF/0603 total 13pcs (DY 5 pcs)
[46] PW R_VCCSA_CSN
<Core Design>
A A
Wistron Corporation
Title
VCCSA
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1p2v
1D2V_PWR 1D2V_S3
PG5102
1 2
DCBATOUT Do Not Stuff

PWR_DCBATOUT_1D2V
PG5110 PG5111
1 2 1 2

PG5104
D Part Reference = PG5106 D
1 2
1 2
Do Not Stuff
PG5101 Do Not Stuff
1 2
PG5112
Do Not Stuff 1 2
PG5107
1 2 Do Not Stuff
Do Not Stuff PG5109

PG5103 1 2
1 2
Do Not Stuff
Do Not Stuff
PG5108 PG5114
1 2 1 2
Do Not Stuff
SY8288RAC for 1D2V Do Not Stuff
PWR_DCBATOUT_1D2V
PC5106 PC5108 PC5107
1
Do Not Stuff
SC10U25V5KX-GP
SCD01U50V2KX-1GP
DY Design Current=7A
2
10.5A<OCP>12.6A
1
PC5113
PWR_1D2V_LDO_P5
SC2D2U10V3KX-1GP
0R0603-PAD 1D2V_PWR
PC5117 PL5101
2
PR5101 SCD1U25V2KX-GP
PWR_1D2V_BOOT 1 2 PWR_1D2V_BOOT_R 1 2 1 2
PR5107 1 2 0R0402-PAD PWR_1D2V_PGOOD
[40] 1D2V_VTT_PWRGD COIL-1UH-73-GP
Do Not Stuff
PU5101
1
2 PWR_1D2V_EN
1
[54] PWR_2D5V_PG 1 PWR_1D2V_PHASE
PG5113
1
17 6
PR5105 VCC LX#6
Do Not Stuff
0R0402-PAD 19 PC5103 PC5105 PC5104 PC5101 PC5102

LX#19
SCD1U16V2KX-3GP
C 20 C
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
SC22U6D3V5MX-2GP
2
2
1
LX#20
SC22U6D3V5MX-2GP
PC5138
2
2
DY IN#2 PWR_1D2V_PGOOD
3 10
IN#3 NC#10
4 12
2
IN#4 NC#12 PWR_1D2V_LDO_P5

5 16 PWR_1D2V_VFB_R
IN#5 NC#16
1
PWR_1D2V_BOOT
1
1 PR5103
BS
9 10KR2F-2-GP PC5112
PG
11 7 SC330P50V2KX-3GP
EN GND
PR5106 1 2PWR_1D2V_IMAX
2
13 8
DYStuff
Do Not PWR_1D2V_VFB ILMT GND
R1
2
14 18
FB GND
OCP setting 15 21
BYP GND
High 12A SY8288RAC-GP Vo=0.6x(1+R1/R2)

Float 8A =0.6x(1+100/100)
Low 6A =1.2V
PWR_1D2V_BYP 1 2 3D3V_S0
PR5102
R2
1
0R0402-PAD
PR5104
1
10KR2F-2-GP
PC5110
SC1U10V2KX-1GP
2
2
DDR_VREF_S3
B B
1
PC5116
SCD1U16V2KX-3GP
2
1D2V_PWR
[17,24,27,40,54] SIO_SLP_S3# PR5126 1 DY 2 0R2J-2-GP PC5115
1
SC10U6D3V3MX-GP
PC5118 Peak Current = 1470mA
PR5125 1 2 0R0402-PAD PWR_0D6V_S3EN SCD1U16V2KX-3GP
[5] SM_PGCNTL_R
2
2
11
PU5102
PR5114 1 2 PWR_0D6V_S5EN 0D6V_PWR 0D6V_PWR 0D6V_S0
GND
[54] PWR_2D5V_PG
0R0402-PAD PG5121
6 5 1 2
VTTREF VTTSEN
7 4
S3 PGND
PR5118 8 3 Do Not Stuff
1
GND VTT PC5114
9 2
S5 VIN
SC22U6D3V5MX-2GP
5V_S5 2 1 PWR_0D6V_VCNTL 10 1 PG5120
VCNTL VREF
1 2
2
1
0R0402-PAD PC5111
1
PC5119 PC5120
SC1U10V2KX-1GP
APL5338XAI-TRG-GP
Do Not Stuff
Do Not Stuff
DY DY Do Not Stuff
74.05338.079
2
2nd source:
74.02997.B79
2014.03.28 EE modify
A A
<Core Design>
Wistron Corporation
Title
(Reserved)
A2
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
SSID = PWR.Plane.Regulator_1D0V
1D0V_PW R 1D0V_S5
PG5211
Do Not Stuff
1 2
PW R_DCBATOUT_1D0V PG5204
D DCBATOUT D
Do Not Stuff
1 2
PG5214
PG5216
Do Not Stuff
Do Not Stuff
1 2
1 2
PG5210
AOZ2262 for 1D0V

PG5201
Do Not Stuff
Do Not Stuff
1 2
1 2
PG5212
PG5208
Do Not Stuff
Do Not Stuff
1 2
1 2
PG5215
Do Not Stuff
1 2
5V_S5 PG5209
Do Not Stuff
1 2
Design Current : 9A PG5213

Do Not Stuff
1
MAG. 7*7*3 1 2
PC5202
SC1U10V2KX-1GP DCR: 9m~10mOhm 11.25A<OCP>13.5A PG5206
2
C Idc : 11 A , Isat : 22A Do Not Stuff C

1 2
PU5201 PL5201 1D0V_PW R
PG5207
IND-1UH-94-GP-U
PW R_DCBATOUT_1D0V Do Not Stuff
21 18 PW R_1D0V_PH 1 2 PC5203 PC5205 PC5201 PC5206 PC5208
VCC LX#18 1 2
LX#17 17
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SC22U6D3V3MX-1-GP
SCD1U25V2KX-GP
LX#16 16
LX#11 11
1
7 IN#7 LX#10 10
2
8 PC5204 SCD1U25V2KX-GP
IN#8
PC5214
PC5216
PC5209
PC5210
PC5211
9 20 PW R_1D0V_BT 1 2 PG5223
2
IN#9 BST GAP-CLOSE-PW R-6-GP
PR5201 88K7R2F-GP PW R_1D0V_FB
DY DY
5
1
FB
1
1 2 PW R_1D0V_TON 6 TON
DY DY PW R_1D0V_PG 1 4
2
PGOOD AGND
SCD1U50V3KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
SC10U25V5KX-GP
PW R_1D0V_FB_A
PW R_1D0V_EN 2 19
EN PGND
PGND 14
PW R_1D0V_PFM 3 13
PFM# PGND
PGND 12
1
PW R_1D0V_SS 22 15
SS PGND PR5202 PC5212
R1
1
SC220P50V2KX-3GP
PR5203 PC5213 2K55R2F-GP
2
AOZ2262QI-10-GP-U
1
100KR2F-L1-GP
SCD01U50V2KX-1GP
2
074.02262.0043
2
B B
1
3D3V_S5 PR5204
10KR2F-2-GP R2 Vo=0.8x(1+R1/R2)
=0.8x(1+2.55/10)
2
1
PR5208 =1.004V
100KR2J-1-GP
DY
PR5209
2
[40] 1D0V_S5_PW RGD 1 2 PW R_1D0V_PG

0R0402-PAD
PR5207
[17,54] SIO_SLP_SUS# 1 DS3 2 PW R_1D0V_EN
0R2J-2-GP
PC5215
1
SC1KP50V2KX-1GP
PR5210
[17,40,45,54] 3V_5V_POK 1 2
2
0R2J-2-GP
NON DS3
<Core Design>
A A
Wistron Corporation
Title
(Reserved)
A3
Starload SKL-U A00
5 4 3 2 1
A B C D E
4 4
3 3
2 2
<Core Design>
1 1
Wistron Corporation
Title
(Reserved)
A3
Starload SKL-U A00
A B C D E
5 4 3 2 1
Main Func = 1D5V
APL5930 for 2D5V PW R_2D5V 2D5V_S3
PG5408
3D3V_S5
S-1339D15-M5001 for 1D5V_S0
1 2
Do Not Stuff
PG5409
3D3V_S5
3D3V_S5
1
1 2
SC1U10V2KX-1GP
PC5408
D 5V_S5 D
Do Not Stuff
2
PC5414 Design Current = 16mA
PC5410
SC1U10V2KX-1GP
SC10U6D3V3MX-GP
1
1
Design current = 700mA PU5402 1D5V_PW R
PG5404 1D5V_S0
PR5410
10KR2F-2-GP 1 5 1 2
2
VIN VOUT
PW R_2D5V 2 VSS
PU5403 PR5405 1 2PW R_1D5V_EN 3 4 Do Not Stuff
[17,24,27,40,51] SIO_SLP_S3#
2
ON/OFF NC#4
0R0402-PAD
5 PC5407
VIN#5
PC5409
SC1U10V2KX-1GP
6 VCNTL VOUT#4 4 DY S-1339D15-M5001-GP
[51] PW R_2D5V_PG 7 POK VOUT#3 3 74.01339.B3F
Do Not Stuff
[17,24,40] SIO_SLP_S4# PR5417 1 2 0R0402-PADPW R_2D5V_EN 8 2 PW R_2D5V_FB
2
EN FB
9 VIN#9 GND 1
47KR2J-2-GP
SCD1U16V2KX-3GP
1
1
29K4R2F-GP
APL5930KAI-TRG-GP PC5411DY PC5413 DY PC5412
PR5409
PC5427
PR5419
SC68P50V2JN-1GP
74.05930.03D
SC10U6D3V5KX-1GP
SC22U6D3V5MX-2GP
2 2ND = 74.G9731.03D R1
2
2
2
1
C C
PR5420
R2 13K7R2F-GP
Vout=0.8V*(R1+R2)/R2
2
APL5930 for 1D8V_S5
5V_S5 3D3V_S5
1D8V_PW R +V1.8A
PG5405
SC1U10V2KX-1GP
B 3D3V_S5 B
PC5401
PC5403 1 2
SC10U6D3V3MX-GP
Design Current = 770mA
1
1
Do Not Stuff
1
PR5402
PG5406
Do Not Stuff 1D8V_PW R
2
2
PH at Page40
DY PU5401 1 2
Do Not Stuff
2
VIN#5 5 PG5407
PR5408
6 VCNTL VOUT#4 4
[40] 1D8V_S5_PW ROK 1 2 PW R_1D8V_POK 7 3 1 2
PW R_1D8V_EN POK VOUT#3
0R0402-PAD 8 EN FB 2
9 1 Do Not Stuff
PR5406 VIN#9 GND
[17,40,45,52] 3V_5V_POK 1 2 PR5403 PC5405

Do Not Stuff
1
1
NON DS3 APL5930KAI-TRG-GP PC5404 PC5402
PC5406
16K5R2F-2-GP
SC68P50V2JN-1GP
PR5401 DY DY 74.05930.03D DY DY
0R2J-2-GP R1
Do Not Stuff
SC10U6D3V5KX-1GP
Do Not Stuff
2ND = 74.G9731.03D
2
2
1.8V_RUN_FB
[#544669 Rev0.53]
2
PR5407
[17,52] SIO_SLP_SUS# 1 2
DS3
0R2J-2-GP
1
PR5404
A R2 13K3R2F-L1-GP <Core Design>
A
Vout=0.8V*(R1+R2)/R2 Wistron Corporation

2

Title
(Reserved)
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = LCD
CAMERA POWER
Hi:2.0V
Lo:0.8V
LCD1
Panel Conn. D5501 LCDVDD Layout 80 mil
3D3V_S0
3D3V_S0
Add 0603 0ohm , 20141118 3D3V_CAMERA_S0
43 [8] EDP_VDD_EN 1
U5501 R5513 20R3J-0-U-GP
41
Backup , 20141114 3
1 DY
D
DCBATOUT_LCD LVDS_VDD_EN_R 1 5 D
EN VIN#5
1 [24] LCD_TST_EN 2 2 F5502
LCDVDD GND
3 4 1 2
BAT54C-7-F-3-GP VOUT VIN#4
2
3 75.00054.E7D POLYSW-D5A6V-1-GP EC5502
1
SCD1U25V2KX-GP
4 RT9724GB-GP C5502 69.50007.921
5 74.09724.09F C5503
SC4D7U6D3V3KX-GP
6 2ND = 74.03514.07F SC4D7U6D3V3KX-GP
LCDVDD
2
1
1
7 C5507 C5508 C5505
SCD1U16V2KX-3GP
SC1U10V2KX-1GP
8 Add 0ohm , 20141118
SC4D7U6D3V3KX-GP
9
2
10
11
12 EDP_AUX C5510 1 2 SCD1U16V2KX-3GP EDP_AUX_DP [8]
13 EDP_AUX# C5511 1 2 SCD1U16V2KX-3GP EDP_AUX_DN [8]
14
15 EDP_TX3# C5532 1 2 SCD1U16V2KX-3GP EDP_TX3_DN [8] BBY
INVERTER POWER
EDP_TX3 C5531 1 2 SCD1U16V2KX-3GP
16 EDP_TX3_DP [8] BBY
17 Add 1206 0ohm , 20141118
EDP_TX2# C5533 1 2 SCD1U16V2KX-3GP R5502
18 EDP_TX2_DN [8] BBY DCBATOUT DCBATOUT_LCD
EDP_TX2 C5519 1 2 SCD1U16V2KX-3GP 0R2J-2-GP
19 EDP_TX2_DP [8] BBY R5514
20 1 DY 2
EDP_TX1# C5501 1 2 SCD1U16V2KX-3GP
21
EDP_TX1 C5504 1
EDP_TX1_DN [8] 2 DY 1
22 2 SCD1U16V2KX-3GP EDP_TX1_DP [8]
23 D5502 0R6J-L-GP
24 EDP_TX0# C5506 1 2 SCD1U16V2KX-3GP 1
EDP_TX0_DN [8] L_BKLT_CTRL [8]
25 EDP_TX0 C5509 1 2 SCD1U16V2KX-3GP F5503
EDP_TX0_DP [8]
26 BKLT_CTRL 3 2 1
27 EDP_HPD_CONN
28 2 LCD_TST POLYSW-1D1A24V-GP-U C5514 C5518
1
SC2D2U35V3KX-GP
SC2D2U35V3KX-GP
29 LCD_TST_C 69.50007.A31 C5512S C5513
SC1KP50V2KX-1GP
30 LCD_BRIGHTNESS BAT54C-7-F-3-GP 2nd = 69.50007.D31
CD1U50V3KX-GP
31 BLON_OUT_C 75.00054.E7D
2
32 DBC_EN_R 1 R5503 2
DBC_PANEL_EN [20]
33
34 0R0402-PAD RN5503
35 DMIC_CLK_C 1 4 DMIC_CLK [27]
36 DMIC_DATA_C 2 3 DMIC_DATA [27]
37
38 SRN33J-5-GP-U EC5503 EC5504
1
39 Starload height limite change to 0603 package
SC22P50V2JN-4GP
SC22P50V2JN-4GP
C 40 C
R5504,R5505 merge to RN5503 EMI DVT1 0210 2015/09/24 modify
2
42 2015/10/06 modify SENSOR POWER
44
3D3V_S0 3D3V_SEN_S0
IPEX-CON40-3-GP X02 0414
1 R5501 2 R5516 1 DY 20R3J-0-U-GP
20.F1407.040
0R0402-PAD
RN5501 Add 0603 0ohm , 20141118
LCD_TST_C 1 8 F5504
LCD_TST [24]
BLON_OUT_C 2 7 1 2
PANEL_BKEN_EC [24]
MIC_GND 3 6
LCD_BRIGHTNESS 4 5 BKLT_CTRL
1
POLYSW-1D1A6V-9-GP-U
SRN100J-4-GP EC5505 DY C5515
69.48001.081
SC33P50V2JN-3GP SC4D7U6D3V3KX-GP
Power Pin Count : 7
2
EDP_HPD_CONN 1 R5506 2 EDP_HPD [8]
100R2J-2-GP
GND Pin Count : 9
HSYNC TOUCH PANEL POWER

RN5502 LCD_BRIGHTNESS
1 8 LVDS_VDD_EN_R 5V_S0 TPAN_VDD
2 7 EDP_HPD
1
3 6 BLON_OUT_C EC5501 69.50007.A31
4 5 BKLT_CTRL DY SC6D8P50V2DN-GP
2nd = 69.50007.D31
2
SRN100KJ-5-GP 3rd = 69.50007.A41
Remove HSYNC schematic
F5501
201511276 POLYSW-1D1A24V-GP-U
1 2
B B
R5507 1 2
0R3J-0-U-GP
DY
1
C5516 C5517
SCD1U50V3KX-GP
SC4D7U6D3V3KX-GP
2
2
USB_CAMERA_N USB_CPU_PN4 [16]
DLP11SN900HL2L-GP
3 4
2 1
Starload height limite change to 0603 package
TCBD1 TR5501
33 2015/09/30 modify
DCBATOUT_CAMERA
NP1
1 IR CAMERA Power
2 DCBATOUT_CAMERA DCBATOUT
3 3D3V_SEN_S0 USB_CAMERA_P
USB_CPU_PP4 [16]
4
5 R5520
6 3D3V_CAMERA_S0 0R3J-0-U-GP
7 SENSOR_I2C_SDA [20,69,70] 1 2
8 SENSOR_I2C_SCL [20,69,70]
9 GSEN_INT1 [20,69]
2
10 GSEN_INT2 [20,69] C5534

11 GYRO_INT [70] C5542 SC1KP50V2KX-1GP
12 GYRO_DRDY [20,69] SCD1U50V3KX-GP
1
13 USB_PN6_TPNL R5510 1 2 0R0603-PAD USB_CPU_PN6 [16]

14 USB_CAMERA_P
15 USB_CAMERA_N
16
17 DMIC_CLK_C
18 DMIC_DATA_C
19 MIC_GND
20
A A
21
22 IR_CAMERA_DET#_R 1 R5540 2 IR_CAMERA_DET# [20]
23
24 0R0402-PAD USB_PP6_TPNL R5511 1 2 0R0603-PAD USB_CPU_PP6 [16]
25
26 TPAN_VDD
27 <Core Design>
28
29
30 USB_PP6_TPNL
USB_PN6_TPNL
Wistron Corporation
31 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
32 TOUCH_PANEL_INTR# [4,24] Taipei Hsien 221, Taiwan, R.O.C.
NP2
34 Title
DVT2 03/24
LCD&CAM&DMC&Touch
JAE-CON32-2-GP-U Size Document Number Rev
20.K0801.032 A2
A00
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
<Core Design>
Wistron Corporation
Title
CRT
A2
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
3D3V_S0
Main Func = HDMI
2
C5701
C5703
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
260mA
1
1D5V_S0 1D5V_VDD
C5714 1 2 SCD1U16V2KX-3GP HDMI_CLK#_R
[8] HDMI_CLK# C5709 SCD1U16V2KX-3GP HDMI_CLK_R R5701 1
[8] HDMI_CLK 1 2 2 0R0603-PAD
D C5707 1 2 SCD1U16V2KX-3GP HDMI_DATA2_R D

[8] HDMI_DATA2 C5710 SCD1U16V2KX-3GP HDMI_DATA2#_R
[8] HDMI_DATA2# 1 2
Exchange 0603 0ohm , 20141118 U5701
11 25 HDMI_DATA2#_R_C
1D5V_VDD VDD33 OUT_D0P HDMI_DATA2_R_C
37 VDD33 OUT_D0N 24
C5715 1 2 SCD1U16V2KX-3GP HDMI_DATA1#_R 27 HDMI_DATA1#_R_C
[8] HDMI_DATA1# C5712 SCD1U16V2KX-3GP HDMI_DATA1_R OUT_D1P HDMI_DATA1_R_C
[8] HDMI_DATA1 1 2 12 VDDRX OUT_D1N 26
2
40 30 HDMI_DATA0#_R_C
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
SCD1U16V2KX-3GP
C5711 SCD1U16V2KX-3GP HDMI_DATA0_R VDDRX OUT_D2P HDMI_DATA0_R_C
C5706
C5702
C5704
C5705
C5716
[8] HDMI_DATA0 1 2 OUT_D2N 29
C5708 1 2 SCD1U16V2KX-3GP HDMI_DATA0#_R 20
1
[8] HDMI_DATA0# VDDTX HDMI_CLK_R_C
31 VDDTX OUT_CKP 22
21 HDMI_CLK#_R_C
OUT_CKN
19 VDDTA
I2C_CTL_EN 8
HDMI_DATA2#_R 6 17 EQ
HDMI_CLK_R_C HDMI_DATA2#_R_C HDMI_DATA0#_R_C HDMI_DATA1_R_C HDMI_DATA2_R IN_D0P EQ/I2C_ADDR0 CFG
7 IN_D0N CFG/I2C_ADDR1 23
HDMI_DATA1#_R 4
HDMI_DATA1_R IN_D1P PRE
5 IN_D1N PRE 16
2
1
HDMI_DATA0#_R 1 34 ISET
R5704 HDMI_DATA0_R IN_D2P ISET
2 IN_D2N PD# 36
180R2J-1-GP 180R2J-1-GP 180R2J-1-GP 180R2J-1-GP
R5705 R5702 R5703 HDMI_CLK_R 9 13 DCIN_EN
HDMI_CLK#_R IN_CKP DCIN_EN/SCL_CTL DDCBUF
10 14
1
2
IN_CKN DDCBUF/SDA_CTL
HDMI_CLK#_R_C HDMI_DATA2_R_C HDMI_DATA0_R_C HDMI_DATA1#_R_C 38 32 DDC_CLK_HDMI
[8] CPU_DP1_CTRL_CLK SCL_SRC SCL_SNK DDC_DATA_HDMI
[8] CPU_DP1_CTRL_DATA 39 SDA_SRC SDA_SNK 33
C change to 180 for HDMI signal quality 2016/01/05 [8] CPU_DP1_HPD 3 HPD_SRC
C
HPD_HDMI_CON 28 15
HPD_SNK GND
GND 35
Change symbol part number, because origin symbol is DELL OBS part 18 REXT HDMMI GND 41
REXT HDMI CONN
1
20150116 2037 5V_S0 5V_S5 5V_HDMI_R_S5 5V_HDMI_S5 PS8407ATQFN40GTR2-A1-GP
F5701 R5710
5V_S0 POLYSW -1D1A6V-9-GP-U Change to 4.3k 20150402 4K3R2J-GP 071.08407.0003 HDMI1
R5715 1 2 0R0603-PAD 1 2 22
20
2
3
D5701 R5716
1 DY 2
0R3J-0-U-GP HDMI_DATA2_R_C
69.48001.081 1
BAW 56-9-GP X01 0227
2nd = 69.50011.081 2
75.00056.07D For DIODE in case of leakage from HDMI1 HDMI_DATA2#_R_C 3
HDMI_DATA1_R_C 4
2
DDC_DATA_PH2 1
5
HDMI_DATA1#_R_C 6
DDC_CLK_PH1
HDMI_DATA0_R_C 7
Vendor suggest, Dummy for floating 8
HDMI_DATA0#_R_C 9
3D3V_S0 20141117 HDMI_CLK_R_C 10
3D3V_S0 11
EQ 2 R5411 1 HDMI_CLK#_R_C 12
4K7R2J-2-GP PRE 2 R5415 1 13
DY 4K7R2J-2-GP 3D3V_S0 14
DY
1
1
2 R5412 1 R5419 5V_HDMI_S5 DDC_CLK_HDMI 15

R5707 R5706 4K7R2J-2-GP 2 R5416 1 DCIN_EN 2 DY 1 DDC_DATA_HDMI 16
B
2K2R2J-2-GP 2K2R2J-2-GP
DY 4K7R2J-2-GP 4K7R2J-2-GP 17
B
DY 18
HPD_HDMI_CON 19
2
2
3D3V_S0 3D3V_S0
1
3D3V_S0 C5713 21
DDC_DATA_HDMI ISET 2 R5413 1 CFG 2 R5420 1 23
SCD1U16V2KX-3GP
DDC_CLK_HDMI 4K7R2J-2-GP DDCBUF 2 R5417 1 4K7R2J-2-GP
DY
2
4K7R2J-2-GP
2 R5414 1 SKT-HDMI23-91-GP-U
4K7R2J-2-GP 2 R5418 1 22.10296.961
DY 4K7R2J-2-GP
DY
Remove DUMMY-HDMI , 20141118
X01 0214
3D3V_S5
4th = 84.2N702.W31
3rd = 84.07002.I31
1
R5721 2ND = 84.2N702.031

10KR2J-3-GP 84.2N702.J31
2N7002K-2-GP
2
A G HPD_HDMI_CON_C 1 R5722 2 HPD_HDMI_CON <Core Design> A
[24] HDMI_EC_DET# 1 R5723 2 HDMI_EC_DET#_C D 0R0402-PAD
0R0402-PAD S Wistron Corporation

Remove DUMMY-HDMI , 20141118 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Remove DUMMY-HDMI , 20141118 Q5704 Taipei Hsien 221, Taiwan, R.O.C.
Title
HDMI
A3 A00
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
D D
C
(Blanking) C
B B
A <Core Design> A
Wistron Corporation
Title
(Reserved)
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
C
(Blanking) C
B B
A <Core Design> A
Wistron Corporation
Title
(Reserved)
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = HDD
1 R6002 2 HDD_DEVSLP_R
[16] HDD_DEVSLP
SATA HDD Connector Reserved for M15 EE Implementation.

0R0402-PAD
HDD1
22 21
E [70] FFS_INT2_Q 1 R6001 2 FFS_INT2_Q_R 1 NP1 E
0R0402-PAD 2
3
5V_HDD_SIP
4 Layout Note:
5
6 Place near HDD1
7
1A
8 U6001
9 5V_HDD_SIP
10 SATA_TXP0_R 1 10 SATA_TXP0_R
SATA_TXN0_R LINE_1 NC#10 SATA_TXN0_R
11 2 9
LINE_2 NC#9
GND DY GND
12 3 8
HDD_DEVSLP_R 13 SATA_RXN0_R 4 7 SATA_RXN0_R
SATA_RXP0_R LINE_3 NC#7 SATA_RXP0_R
HDD C6001 14 5
LINE_4 NC#6
6
1
SCD01U50V2KX-1GP 1 2 SATA_TXP0_R 15 HDD C6004 HDD
[16] SATA_TX_CPU_P0
SCD01U50V2KX-1GP 2 C6003 SATA_TXN0_R SC2D2U10V2KX-GP C6002
[16] SATA_TX_CPU_N0 1 HDD 16 HDD
17 AZ1045-04F-R7G-GP
2
[16] SATA_RX_CPU_N0 SCD01U50V2KX-1GP 1HDD2 C6006 SATA_RXN0_R 18 SCD1U16V2KX-3GP
SCD01U50V2KX-1GP 1 2 C6005 SATA_RXP0_R 19
[16] SATA_RX_CPU_P0
HDD 20 NP2 75.01045.073
24 23 Swap based on the swap report.
FOX-CON20-1-GP-U1
20.F1546.020
Close to HDD1
Modify at 20150922
5V_S0 5V_HDD 5V_HDD_SIP

D D
R6006 1 2 0R0603-PAD R6003 1 2 0R0603-PAD
C6009
SC1U6D3V2KX-GP
R6007
1
0R2J-2-GP
DY U6002
1 DY 2
2
[18] HDD_EN_PCH
1 8
VIN#1 VOUT#8
2 7
HDD_EN VIN#2 VOUT#7 HDD_CT
[17,24] SIO_SLP_S0#
1 DY 2 3
ON CT
6
4 5
R6005 VBIAS GND
1
SCD1U16V2KX-3GP
C6007
SCD1U16V2KX-3GP
C6010
C6008
0R2J-2-GP DY 9
SCD1U16V2KX-3GP
GND
1
DY DY
DY
2
TPS22965DSGR-GP-U
2
74.22965.093
Add HDD power switch schematic(reserve) by Win10 feature ,DVT1 20150204
C C
Main Func = ODD

B B
A A
<Core Design>
Wistron Corporation
Title
SATA IF_HDD/ODD
A2
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = WLAN
D D
C C
B B
A <Core Design> A
Wistron Corporation
Title
NGFF_WLAN CONN
A3
Starload SKL-U A00
5 4 3 2 1
A B C D E
4 4
3
(Blanking) 3
2 2
<Core Design>
1
Wistron Corporation 1
Title
Reserved
A4
Starload SKL-U A00
A B C D E
5 4 3 2 1
SSD M.2
SSD M.2 CONN

3D3V_SSD SSD1
D NP2 NP2 NP1 NP1 D

76 76 77 77
74 3_3VAUX GND 75
72 3_3VAUX GND 73
70 3_3VAUX GND 71
68 69 SSD_PEDET 1 R6305 2
3D3V_S0 3D3V_SSD SUSCLK_32KHZ PEDET(OC_PCIE/GND_SATA)
58 NC#58 NC#67 67
56 57 0R0402-PAD
NC#56 GND
54 PEWAKE#/NC#54 REFCLKP 55
R6302 1 2 0R0603-PAD 52 53
CLKREQ#/NC#52 REFCLKN
R6307 1
50 PERST#/NC#50 GND 51 SSD
2 0R0603-PAD 48 NC#48 PERP0/SATA_A+ 49 SATA_TX_CPU_P1_C 1 2C6302 SCD22U10V2KX-1GP SATA_TX_CPU_P1 [16]
SC33P50V2JN-3GP
C6305
SC33P50V2JN-3GP
C6304
SCD047U25V2KX-GP C6307 46 47 SATA_TX_CPU_N1_C 1 2C6303 SCD22U10V2KX-1GP SSD

C6306
SCD047U25V2KX-GP
C6308
NC#46 PERN0/SATA_A- SATA_TX_CPU_N1 [16]
1
1
44 45
SCD1U16V2KX-3GP
NC#44 GND SATA_RX_CPU_N1_C
42 NC#42 PETP0/SATA_B- 43 1 2C6309 SCD22U10V2KX-1GP SSD SATA_RX_CPU_N1 [16]
40 41 SATA_RX_CPU_P1_C 1 2C6301 SCD22U10V2KX-1GP SSD SATA_RX_CPU_P1 [16]
2
2
NC#40 PETN0/SATA_B+
[16] MSATA_DEVSLP 1 R6301 2 MSATA_DEVSLP_R 38 DEVSLP GND 39
36 NC#36 PERP1 37
0R0402-PAD 34 35
NC#34 PERN1
32 NC#32 GND 33
30 NC#30 PETP1 31
28 NC#28 PETN1 29
SSD SSD SSD SSD SSD 3D3V_SSD
26 NC#26 GND 27
24 NC#24 PERP2 25
22 NC#22 PERN2 23
20 NC#20 GND 21
18 3_3VAUX PETN2 19
16 3_3VAUX PETP2 17
14 3_3VAUX GND 15
C 3D3V_SSD 12 13 C
3D3V_SSD 3_3VAUX PERP3
10 DAS/DSS# PERN3 11
8 NC#8 SSD GND 9
1
6 NC#6 PETN3 7
R6303 4 3_3VAUX PETP3 5
DY 10KR2J-3-GP
2 3_3VAUX GND 3
GND 1
NGFF_KEY_M 75P
2
SKT-MINI67P-15-GP
3D3V_SSD 1 AFTP6304 MSATA_DEVSLP 062.10003.0481
MSATA_DEVSLP_R
1
1 AFTP6301
R6304
SSD_PEDET 1 AFTP6303 DY 10KR2J-3-GP
2
ED6301
SATA_TX_CPU_P1_C 1 10 SATA_TX_CPU_P1_C
SATA_TX_CPU_N1_C 2 9 SATA_TX_CPU_N1_C
B B
3 SSD 8
SATA_RX_CPU_N1_C 4 7 SATA_RX_CPU_N1_C
SATA_RX_CPU_P1_C 5 6 SATA_RX_CPU_P1_C
L05ESDL5V0NA-4-GP
075.00550.0071
A <Core Design> A
Wistron Corporation
Title
(Reserved)
A3 A00
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
Main Func = Power BTN
D Battery LED1 (AMBER_LED) D
Low actived from KBC GPIO

5V_S5
Q6402
R2
E
[24] CHG_AMBER_LED# 1 R6403 2 CHG_AMBER_LED_R# B R1
R6401
C AMBER_LED_BAT 2 1
0R0402-PAD
BAT_AMBER [65] AMBER
RN2418-GP 499R2F-2-GP
1
084.02418.0011
1
ED6401
DYEC6401 PESD5V0S1BB-GP-U
SC220P50V2KX-3GP DY
2
5V_S5
Q6401
R2
C E C
[24] BATT_W HITE_LED# 1 R6404 2 BATT_W HITE_LED_R# B R1

R6402
C W HITE_LED_BAT 2 1 BAT_W HITE [65]
0R0402-PAD
RN2418-GP 330R2J-3-GP WHITE
1
084.02418.0011
1
ED6402
DYEC6402 PESD5V0S1BB-GP-U
SC220P50V2KX-3GP DY
2
Battery LED2 (WHITE_LED)
Low actived from KBC GPIO
B B
SATA LED
Q6105
[16] SATA_ACT# S
D BATT_W HITE_LED_R#
[24,43] SATA_LED# G HWHDLED

2N7002K-2-GP
84.2N702.J31
3D3V_S0 2ND = 084.27002.0A31
R6120 3rd = 84.07002.I31
1 2 SATA_LED#
HWHDLED
10KR2J-3-GP
Add SATA LED solution by customer request 2016/02/03

A <Core Design> A
Wistron Corporation
Title
LED Board&Power Button

A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = KB Main Func = TPAD
Keyboard
KBBD1
[24] KSI[0..7] 45
D 1 D
AFTP6538 1
[24] KSO[0..16] CAP_LED 2
CAP_LED
AFTP6523 1 KSO10 3
AFTP6522 1 KSO11 4
AFTP6504 1 KSO9 5
AFTP6521 1 KSO14 6
AFTP6520 1 KSO13 7
AFTP6524 1 KSO15 8
AFTP6539 1 KSO16 9
AFTP6519 1 KSO12 10 TP_VDD Discharge Circuit
AFTP6507 1 KSO0 11 3D3V_S5 3D3V_S0 TP_VDD
AFTP6513 KSO2
AFTP6511
1
KSO1
12 NON TP_WAKE TP_VDD
AFTP6518
1
KSO3
13 TP_WAKE R6502 1
1 14 2
AFTP6516 KSO8 Q6502 0R3J-0-U-GP
1 15
AFTP6517 1 KSO6 16 DMP2130L-7-GP Q6502_D
1
AFTP6515 1 KSO7 17
AFTP6514 1 KSO4 18 S R6514 TP_WAKE R6503
AFTP6510 KSO5 100R3J-4-GP
1 19 D 1 TP_WAKE
2 Q6503
D
AFTP6512 KSI0
1 20 TP_WAKE
G
AFTP6509 1 KSI3 21 0R3J-0-U-GP TP_ON#_GATE G
2
1
AFTP6501 1 KSI1 22 SCD1U16V2KX-3GP 84.02130.031
G
AFTP6506 1 KSI5 23 TP_WAKE C6502 2ND = 84.03413.A31 TP_WAKE D Q6205_Q
AFTP6508 1 KSI2 24 Add 0ohm , 20141118
2
AFTP6505 1 KSI4 25 1 2 TP_ON#_GATE S
[24] TP_EN#
AFTP6503 1 KSI6 26
AFTP6502 1 KSI7 27 R6504
20KR2F-L-GP 2N7002K-2-GP
[20] KB_DET# 28
29 84.2N702.J31
+5V_KB_BL 30 2ND = 84.2N702.031
KB_BL_CTRL# 31
KB_LED_DET_C 3rd = 84.07002.I31
32
33 4th = 84.2N702.W31
[64] BAT_AMBER
34
TP_VDD [64] BAT_WHITE
35
I2C0_SDA_R 36
I2C0_SCL_R 37
C6503
38
2 1 39
[4,24] INT_TP# 40
C SCD1U16V2KX-3GP 41 TP_VDD C
[24] PTP_DIS#
TPDATA_C 42
TPCLK_C 43
44 GPIO_TPAD: TBD
46
(Touch pad wake# for S3 wake up @ PCH GPIO??)
2
1
STAR-CON44-GP RN6501
20.K0809.044 SRN10KJ-5-GP
3
4
5V_S0 +5V_KB_BL RN6502
SRN33J-5-GP-U
F6501 2 3 TPCLK_C
1 2
69.50007.921 PS2 [24] CLK_TP_SIO
[24] DAT_TP_SIO 1 4 TPDATA_C
1
POLYSW-D5A6V-1-GP [20] I2C0_SCL_TCH_PAD 0R2J-2-GP 1 NON TP_WAKE

2 R6505 I2C0_SCL_R
KBBL C6501 KBBL 0R2J-2-GP 1 NON TP_WAKE
2 R6506 I2C0_SDA_R
1
DY 2 I2C [20] I2C0_SDA_TCH_PAD
2
R6501 0R3J-0-U-GP SCD1U16V2KX-3GP
EC6502
SC33P50V2JN-3GP
EC6503
SC33P50V2JN-3GP
EC6504
SC33P50V2JN-3GP
1
1
EC6501
KB Backlight Power Consumption: 285mA max. SC33P50V2JN-3GP DY DY DY DY
2
KB_BL_CTRL#
D
Q6501 R6507 Change pindefine DVT1 0210 1330

P8503BMG-GP KB_LED_DET_C
[19] KB_LED_BL_DET_R
1 KBBL 2
G 84.P8503.031 Pin number Pin name
1
B [24] BKLGT_PWM B
2nd = 84.03404.C31 51KR2J-1-GP Need to check if it is Active High or Active Low
1
and check if there is PH on TPAD side. 1 VDD

S
R6509 KBBL R6508 DY C6504

DY 100KR2J-1-GP
KBBL 100KR2J-1-GP 5V_S0 2 DAT(I2C)
SCD1U16V2KX-3GP
2
2
X02 0415 3 CLK(I2C)

2
A00 0609 TP_VDD TP_VDD 4 GND
1
5 ATTN
R6510
+5V_KB_BL 1 0R0402-PAD 6 GPIO
1
AFTP6529
1
2
KB_BL_CTRL# 1 R6511 7 DAT(PS2)
2
AFTP6530 RN6503 10KR2J-3-GP
TP_WAKE SRN2K2J-1-GP 8 CLK(PS2)
2
Q6204_G INT_TP#
4
3
Q6504
CAP LED Control 2N7002KDW-GP
I2C0_SCL_TCH_PAD 1 6 I2C0_SCL_R TP_VDD 1 AFTP6531
LOW actived from KBC GPIO TPCLK_C 1 AFTP6532
84.2N702.A3F 2TP_WAKE
5 TPDATA_C 1 AFTP6533
2nd = 84.2N702.E3F I2C0_SCL_R 1 AFTP6534
3rd = 75.00601.07C 3 4 I2C0_SDA_R I2C0_SDA_R 1 AFTP6535
4th = 84.DMN66.03F INT_TP# 1 AFTP6536
PTP_DIS# 1 AFTP6537
5V_S5 I2C0_SDA_TCH_PAD
X02 0414
Q6505 R2
E
1 R6512 2 CAP_LED_R# B
[24] CAP_LED#_R R1
CAP_LED_Q CAP_LED
C 1 2
0R0402-PAD R6513 1KR2J-1-GP
RN2418-GP
084.02418.0011
A A
<Core Design>
Wistron Corporation
Title
Key Board&Touch Pad

A2 A00
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
Main Func = IO Connector

IOBD1
51
53
1 Change choke Height just for Starload
Cutomer remove IO board USB3.0 2015/09/23 modify
2
3
4
D 5 D
6
7 PCIE_RX_CPU_P5 [16]
8 PCIE_RX_CPU_N5 [16] COIL-90OHM-100MHZ-5-GP
9 USB_CPU_PP2_C 4 3 USB_CPU_PP2 [16]
10 PCIE_TX_W LAN_N5 [16]
11 PCIE_TX_W LAN_P5 [16] WLAN USB_CPU_PN2_C 1 2 USB_CPU_PN2 [16]
12
13 TR6601
PEG_CLK1_CPU# [18]
14 PEG_CLK1_CPU [18]
15
16 USB_CPU_PN5_C
17 USB_CPU_PP5_C 68.00396.001
18
USB_CPU_PN2_C
2nd: = 68.01012.20B
19
20 USB_CPU_PP2_C USB3.0 port3
21
22 USB_CPU_PN7_C
23 USB_CPU_PP7_C Card Reader
24
25
26
27 COIL-90OHM-100MHZ-5-GP
28 5V_S5 USB_CPU_PP7_C 4 3 USB_CPU_PP7 [16]
29
30 USB_CPU_PN7_C 1 2 USB_CPU_PN7 [16]
31
32 TR6602
33
C 34 C
+RTC_VCC
35
36 3D3V_S0
37
38
39
40
41 VOL_UP# [24]
42 VOL_DOW N# [24] 1 R6605 2
43 PLT_RST# [17,24,68]
44 CLKREQ_PCIE#1 [18] 0R0603-PAD
45 KBC_PW RBTN# [24]
46 USB_CPU_PN5_C USB_CPU_PN5 [16]
W IFI_RF_EN [15]
47 BLUETOOTH_EN [20]
48 USB_OC1# [16] USB_CPU_PP5_C USB_CPU_PP5 [16]
49 USB_EN# [24,35]
50
54
52 1 R6606 2
0R0603-PAD
IPEX-CON50-1-GP
020.F0574.0050
EMI Reserve , 20141118
B GPU1 KBC_PW RBTN# PLT_RST# W IFI_RF_EN B
1
EC6601
EC6602
EC6603
A1 B1 DY DY DY
SC33P50V2JN-3GP
SC33P50V2JN-3GP
SC33P50V2JN-3GP
A1 B1
[18] CLKREQ_PEG#0 A2 B2 dGPU_RXP_C_CPU_TXP2 [16]
2
A2 B2
A3 A3 B3 B3 dGPU_RXN_C_CPU_TXN2 [16]
[16] dGPU_RXP_C_CPU_TXP0 A4 A4 B4 B4
[16] dGPU_RXN_C_CPU_TXN0 A5 A5 B5 B5 dGPU_RXP_C_CPU_TXP3 [16]
A6 A6 B6 B6 dGPU_RXN_C_CPU_TXN3 [16]
A7 B7 GPU2
[16] dGPU_RXP_C_CPU_TXP1 A7 B7
[16] dGPU_RXN_C_CPU_TXN1 A8 A8 B8 B8 CLK_PCIE_VGA [18]
A9 A9 B9 B9 CLK_PCIE_VGA# [18] DCBATOUT A1 A1 C1 C1
A10 A10 B10 B10 A2 A2 C2 C2
A3 A3 C3 C3
[20] GC6_FB_EN C1 C1 D1 D1 PLT_RST# [17,24,68] A4 A4 C4 C4
[24] OVER_CURRENT_P8# C2 C2 D2 D2 A5 A5 C5 C5
C9 C9 D9 D9 DGPU_PW ROK [24] A6 A6 C6 C6
[20] DGPU_PW R_EN C10 C10 D10 D10 DGPU_HOLD_RST# [20]
B1 B1 D1 D1
E1 E1 F1 F1 3D3V_AUX_S5 B2 B2 D2 D2
[16] CPU_RXP_C_dGPU_TXP0 E2 E2 F2 F2 B3 B3 D3 D3
[16] CPU_RXN_C_dGPU_TXN0 E3 E3 F3 F3 B4 B4 D4 D4
E4 E4 F4 F4 CPU_RXP_C_dGPU_TXP2 [16] B5 B5 D5 D5
[16] CPU_RXP_C_dGPU_TXP1 E5 E5 F5 F5 CPU_RXN_C_dGPU_TXN2 [16] B6 B6 OPS D6 D6
[16] CPU_RXN_C_dGPU_TXN1 E6 E6 OPS F6 F6
E7 E7 F7 F7 CPU_RXP_C_dGPU_TXP3 [16] 3D3V_S0 P1 P1 N1 N1
E8 F8 P2 Wistron Confidential document, Anyone can not
[18,24,26] SML1_SMBCLK E8 F8 CPU_RXN_C_dGPU_TXN3 [16] P2 Duplicate, Modify, Forward or any other purpose
[18,24,26] SML1_SMBDATA E9 E9 F9 F9 P3 P3 NP1 NP1
E10 F10 P4 NP2 application without get Wistron permission
E10 F10 GPU_EVENT# [20] 5V_S0 P4 NP2
A NP3 NP3 <Core Design> A
NP1 NP1 N1 N1
NP2 NP2 UNI-CONN28-6R-GP-U
NP3 NP3
020.F0588.0028 Wistron Corporation
UNI-CONN48-6R-GP-U1 Taipei Hsien 221, Taiwan, R.O.C.
020.F0581.0048 Title
IO Board Connector
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = Debug
D D
Debug Connector
Layout Note:
Place near trace separated point 3D3V_S0
DB1
11
LPC_LAD[3..0] RN6801 1
[18,24] LPC_LAD[3..0]
SRN0J-7-GP-U
LPC_LAD0 1 8 LPC_LAD0_C 2
LPC_LAD2 3 LPC 6 LPC_LAD2_C 4
LPC_FRAME#_DEBUG 6
LPC
1 2 PLT_RST#_DEBUG 7
[18,24] LPC_LFRAME#
[17,24,66] PLT_RST# R6801 LPC
1 2 0R2J-2-GP 8
R6802 0R2J-2-GP 9
[18] CLK_PCI_LPC
10
12
C C
PAD-10P-177042-GP
20.D0075.110: Dummy Pad with solder mask is ZZ.00PAD.Y41

DB1 Optional: New one smaller LPC connector is 20.F1180.010.
B B
<Core Design>
A
Title
Dubug connector
A4
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
R6902 3D3V_MCU From APU

100KR2J-1-GP
MCU_RST# 1 HUB 2
1
C6902
HUB SCD1U16V2KX-3GP
Sensor Hub
2
3D3V_S0 3D3V_MCU
R6901 150mA 3D3V_MCU
1 HUB 2
U6901
RN6901
C6901
SC1U10V2KX-1GP
C6903
SCD01U50V2KX-1GP
C6904
SCD01U50V2KX-1GP
C6905
SCD01U50V2KX-1GP
C6906
SCD1U16V2KX-3GP
C6907
SCD1U16V2KX-3GP
0R3J-0-U-GP SENSOR_I2C_SCL 4 1
1
1
1 18 GSEN_INT1_HUB SENSOR_I2C_SDA 3 DY 2
VLCD PB0 GSEN_INT2_HUB
PB1 19
change 0603 0ohm , 20141118 9 HUB 20 GYRO_INT_C_HUB
2
2
VDDA PB2 GYRO_DRDY_HUB SRN2K2J-1-GP
PB3 39
HUB HUB HUB HUB HUB HUB 24 VDD_1 PB4 40
36 VDD_2 PB5 41 X6901
48 42 SENSOR_I2C_SCL_HUB
VDD_3 PB6 SENSOR_I2C_SDA_HUB
PB7 43
45 MCU_OSCO 3 HUB 2
PB8
10 PA0_WKUP1 PB9 46
C HUB_PA1 11 21 C
HUB_PA2 PA1 PB10
12 PA2 PB11 22
1
HUB_PA3 13 25 C6908 4 1 MCU_OSCI
HUB_PA4 PA3 PB12
14 PA4 PB13 26 HUB
1
HUB_PA5 15 27 SC15P50V2JN-2-GP
2
HUB_PA6 PA5 PB14
GSEN2_INT1_C_HUB
16 PA6 PB15 28 XTAL-12MHZ-67-GP HUB C6909
17
2
PA7 MCU_OSCI SC15P50V2JN-2-GP
R6904
29 PA8 PH0_OSC_IN 5
MCU_OSCO
82.30006.641
1K5R2F-2-GP
HUB USBDISABLE
30 PA9 PH1_OSC_OUT 6
1 2 31 PA10
[16] USB_CPU_PN8 R6905 1 HUB 2 0R2J-2-GP USB_8- 32 7 MCU_RST#
R6906 PA11 RST#
[16] USB_CPU_PP8 1 HUB 2 0R2J-2-GP USB_8+ 33 PA12 BOOT0 44 MCU_BOOT0
SW DIO 34 GSEN_INT1_HUB R6921 1 HUB 2 0R2J-2-GP
PA13 GSEN_INT1 [20,55]
1
SW CLK 37 GSEN_INT2_HUB R6922 1 HUB 2 0R2J-2-GP
PA14 GSEN_INT2 [20,55]
GSEN2_INT2_C_HUB 38 8 HUB R6907 GYRO_INT_C_HUB R6923 1 HUB 2 0R2J-2-GP
PA15 VSSA GYRO_INT_C [20,70]
20KR2J-L2-GP GYRO_DRDY_HUB R6924 1 HUB 2 0R2J-2-GP
GYRO_DRDY [20,55]
R6920 1 HUB 2 KB_DISABLE_HUB 2 23 GSEN2_INT1_C_HUB R6925 1 HUB 2 0R2J-2-GP
[20,24] KB_DISABLE PC13_WKUP2 VSS_1 GSEN2_INT1_C [20,70]
0R2J-2-GP 3 35 GSEN2_INT2_C_HUB R6926 1 HUB 2 0R2J-2-GP
GSEN2_INT2_C [20,70]
2
PC14_OSC32_IN VSS_2
4 PC15_OSC32_OUT VSS_3 47
SENSOR_I2C_SCL_HUB R6928 1 DY 2 0R2J-2-GP SENSOR_I2C_SCL [20,55,70]
49 SENSOR_I2C_SDA_HUB R6929 1 DY 2 0R2J-2-GP
GND SENSOR_I2C_SDA [20,55,70]
STM32L151CBU6TR-GP
071.32151.000U
B
For Sensor Orientation Setting 3D3V_MCU B
R6908 1 DY 2 10KR2J-3-GP R6909 1 HUB 2 10KR2J-3-GP
R6914 1 HUB 2 10KR2J-3-GP R6915 1 DY 2 10KR2J-3-GP
R6916 1 HUB 2 10KR2J-3-GP R6917 1 DY 2 10KR2J-3-GP For MCU debug port

3D3V_MCU
HUB_PA1
HUB_PA2 SW DIO 1 TP6903 TPAD14-OP-GP
HUB_PA3 SW CLK 1 TP6904 TPAD14-OP-GP
HUB_PA4 1 TP6902 TPAD14-OP-GP
HUB_PA5 1 TP6901 TPAD14-OP-GP
HUB_PA6
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = Hall Sensor
LID sensoe combine G

3D3V_S5 3D3V_S5
2
R7001 R7011
100KR2J-1-GP 100KR2J-1-GP
DY DY 3D3V_S5 GYRO_INT_P11 1 DY 2 GYRO_INT [55]
D GMR1 0R2J-2-GP R7002 D
1
[24] KB_CLOSE#_2 1 4 [20,69] GYRO_INT_C 1 R7003 2
OUT2 OUT1 LID_CL_SIO# [24] C7002
2 3
1
GND VDD 0R0402-PAD
SCD1U16V2KX-3GP
1
HGDEDM013A-GP
2
C7001 074.00013.00BJ
DY
SCD047U16V2KX-1-GP
D7001
GYRO_INT_P11 1
DY 3
FFS_INT2 [20]
INT2_SELECT 2
BAT54A-7-F-2-GP
75.00054.R7D
1 2
R7008 0R0402-PAD
C C
Note:
- no via, trace, under the sensor (keep out area around 2mm)
- stay away from the screw hole or metal shield soldering joints
3D3V_S0 3D3V_GSEN2 - design PCB pad based on our sensor LGA pad size (add 0.1mm)
C7004 - solder stencil opening to 90% of the PCB pad size
R7004 11uA near pin9
1 2 Free Fall Sensor + G Sensor - mount the sensor near the center of mass of the NB as possible as you can
C7003
SCD1U16V2KX-3GP
0R0402-PAD
1
C7004
SC10U6D3V3MX-GP
2
3D3V_GSEN2
U7001 Please help to close with U6602

9 2 GSENSOR_CS 1 2
VDD CS R7006 10KR2J-3-GP 3D3V_S0
5
RES
10
VDD_IO GSEN2_INT1
12
1
INT1 GSEN2_INT2
11
INT2 R7018
SENSOR_I2C_SCL_2G 1 100KR2J-1-GP
SENSOR_I2C_SDA_2G SCL/SPC
4 6
R7005 1 SDA/SDI/SDO GND
3D3V_GSEN2 DY 2 10KR2J-3-GP 3 7
2
SDO/SA0 GND FALL_INT2
8
GND
1 2 GSENSOR_SDO
R7007 0R0402-PAD
LNG2DMTR-GP
Q7001
074.LNG2D.00BZ
1
B 2N7002KDW-GP B
84.2N702.A3F
2nd = 84.DM601.03F
3rd = 84.2N702.E3F
4th = 84.2N702.F3F
6
GSEN2_INT1_C R7009 1 2 0R0402-PAD GSEN2_INT1
[20,69] GSEN2_INT1_C
GSEN2_INT2_C R7010 1 2 0R0402-PAD GSEN2_INT2
[20,69] GSEN2_INT2_C
INT2_SELECT
FFS_INT2_Q [60]
R7012 1 2 0R0402-PAD
Note:
[18] HDD_FALL_INT
(1) Keep all signals are the same trace width. (included VDD, GND).
INT2_SELECT R7013 1 2 0R0402-PAD (2) No VIA under IC bottom.
RN7001
2 3 SENSOR_I2C_SCL_2G
[20,55,69] SENSOR_I2C_SCL
1 4 SENSOR_I2C_SDA_2G
[20,55,69] SENSOR_I2C_SDA
SRN0J-6-GP
A A
<Core Design>
Wistron Corporation
Title
(Reserved)
A2 A00
Starload SKL-U
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Size Document Number

RESERVED Rev
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A <Core Design> A
Wistron Corporation
Title
USB3.0 PORT
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
A A
<Core Design>
Wistron Corporation
Title
GPU(1/5)PEG
A2
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
A A
<Core Design>
Wistron Corporation
Title
GPU(2/5)DIGITALOUT
A2
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
A A
<Core Design>
Wistron Corporation
Title
GPU(3/5)VRAMI/F
A1
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
A A
<Core Design>
Wistron Corporation
Title
GPU(4/5)GPIO/STRAP
Custom
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
A A
<Core Design>
Wistron Corporation
Title
GPU(5/5)PWR/GND
Custom
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
<Core Design>
A A
Wistron Corporation
Title
GPU-VRAM1,2 (1/4)
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
<Core Design>
A A
Wistron Corporation
Title
GPU-VRAM3,4 (2/4)
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
A <Core Design> A
Wistron Corporation
Title
GPU-VRAM5,6 (3/4)
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
<Core Design>
A A
Wistron Corporation
Title
GPU-VRAM7,8 (4/4)
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = dGFX_CORE
D D
C C
B B
A A
<Core Design>
Wistron Corporation
Title
GPU CORE
A2
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = dGPU
D D
C C
B B
A A
<Core Design>
Wistron Corporation
Title
GPU Discrete Power

5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = UnusedParts
34.4YW18.001 ZZ.00PAD.7F1 ZZ.00PAD.7G1

D H2 H4 H3 H6 D
SPR3 SPR4 SPR2 HOLE335R178-GP HOLE335R178-GP H5 HOLE335R229-GP HOLE335R229-GP
SPRING-171-GP SPRING-15-GP SPRING-171-GP HOLE335R229-GP
1
1
1
SPR1
SPRING-171-GP
H7 H8 H9 H10 34.4Y802.011
1
HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP HOLE335R178-GP STFSR158R113H62-GP STFSR158R113H62-GP

HS1
STF217R115H101-GP HS2 HS3
OPS
OPS
434.07R01.0001 434.07R01.0001
NP1
1
NP1
1
SSID = EMI
Mind the voltage rating of the caps.

C C
AUD_AGND DCBATOUT 3D3V_S0 3D3V_S5 +DC_IN 5V_S5 5V_S0 1D2V_S3
EC8901 EC8902 EC8903 EC8904

1
EC8918
SC1KP50V2KX-1GP
EC8919
SCD1U25V2KX-GP
EC8906 EC8907 EC8908 EC8909 EC8910 EC8911 EC8912 EC8913 EC8914 EC8915 EC8916 EC8917
1
1
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SC1U50V3KX-GP
EC8905
SC2200P50V2KX-2GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
DY DY DY DY DY DY DY DY DY DY
SC1KP50V2KX-1GP
SC1KP50V2KX-1GP
DY DY
2
2
Change to 0.1uF at 20150427 for EMI
SSID = RF
1D2V_S3 DCBATOUT
DCBATOUT
B B
EC8920 EC8921 EC8922 EC8923 EC8924 EC8925

1
1
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SC1U50V3KX-GP
EC8927
SC1U50V3KX-GP
EC8928
SC1U50V3KX-GP
EC8929
EC8926
SC2D2U10V2KX-GP
DY
2
2
Remove EC8931,EC8932,EC8926,EC8930for placement
1D2V_S3
1
EC8933DY EC8934DY EC8935DY EC8936 EC8937 EC8938

SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
SC2200P50V2KX-2GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
SCD1U25V2KX-GP
2
A <Core Design> A
Wistron Corporation
Title
UNUSED PARTS/EMI Capacitors

A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
Reserved
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
SSID = TPM
D D
C C
B B
A <Core Design> A
Wistron Corporation
Title
TPM2.0
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
C (Blanking) C
B B
<Core Design>
A
Title
(Reserved)Finger Print
A4
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
(Reserved)
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
(Reserved)
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
(Reserved)
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
A <Core Design> A
Wistron Corporation
Title
(Reserved)
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
<Core Design>
A A
Wistron Corporation
Title
LVDS_Switch
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
D D
C C
(Blanking)
B B
<Core Design>
A A
Wistron Corporation
Title
CRT_Switch
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Main Func = Debug
D D
C C
B B
A A
<Core Design>
Wistron Corporation
Title
CPU_XDP;PCH_XDP
A2
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
CLK Block Diagram
Intel CPU
D
Haswell/Broadwell ULT D
M_A_DIMA_CLK_DDR0
CK0 SA_CLK0
M_A_DIMA_CLK_DDR#0
CK0# SA_CLK#0
DDR3L DIMM1
M_A_DIMA_CLK_DDR1
CK1 SA_CLK1
M_A_DIMA_CLK_DDR#1
CK1# SA_CLK#1 CLK_PCIE_WLAN_P3
CLKOUT_PCIE_P2 REFCLKP0
WLAN
CLK_PCIE_WLAN_N3
CLKOUT_PCIE_N2 REFCLKN0 NGFF
LAN
CLK_PCIE_LAN_P4
RTL8106E/RTL8111G
CLKOUT_PCIE_P3 REFCLK_P
FBA_CLK0P CLK_PCIE_LAN_N4
C CK CLKOUT_PCIE_N3 REFCLK_N
VRAM1 FBA_CLK0N
VGA C
CK#
N15V-GM-S-A2
LANXIN
GB2-64 (23x23)
‧‧
CKXTAL1
FBA_CLK0P
CLK_PCIE_VGA#
CK FBA_CLK0 PEX_REFCLK# CLKOUT_PCIE_N4
FBA_CLK0N
VRAM2 CK#
FBA_CLK0# X3001
25MHz
CLK_PCIE_VGA
PEX_REFCLK CLKOUT_PCIE_P4
LANXOUT
CKXTAL2
FBA_CLK1P
CK 27MHZ_IN
XTAL_IN
VRAM3 CK#
FBA_CLK1N
X7601
‧‧
27MHz
FBA_CLK1P
CK FBA_CLK1
VRAM4 FBA_CLK1N
FBA_CLK1# XTAL_OUT
27MHZ_OUT Audio
CK#
RN2102
Realtek
HDA_BITCLK HDA_CODEC_BITCLK
HDA_BCLK/I2S0_SCLK BITCLK ALC3223
B SRN33J-5-GP-U B
RTC_X1
RTCX1
X1901
R5815
0R2J-2-GP
SUSCLK_NGFF
SUS_CLK NGFF
32.768KHz
RTC_X2
RTCX2
XTAL24_IN KBC
XTAL24_IN
NPCE285P
X1801
24MHz
SUSCLK/GPIO62
CLKOUT_LPC_1
SUS_CLK_PCH R1710 SUS_CLK
0R2J-2-GP
CLK_PCI_KBC_R R1805
‧ R2441
0R2J-2-GP
CLK_PCI_KBC
SUS_CLK_KBC
GPIO0/EXTCLK/F_SDIO3
LCLK/GPIOF5
0R2J-2-GP
XTAL24_OUT CLKOUT_LPC_0 CLK_PCI_LPC_R R1804 CLK_PCI_LPC
XTAL24_OUT 0R2J-2-GP
LPC
CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P
Test Point
A A
<Core Design>
Wistron Corporation
Title
CLK Block Diagram
A2
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
Change notes -
DATE VERSON DATE Page Modify List OWNER
D D
C C
B B
<Core Design>
A A
Wistron Corporation
Title
Change History
A3
Starload SKL-U A00
5 4 3 2 1
5 4 3 2 1
SKL-U/Y Timing Diagram for G3 to S0/M0 [Non Deep Sx Platform] Tulip Skylake POWER UP SEQUENCE DIAGRAM (Deep Sx Platform)
3D3V_S5 5V_S5 1D05V_S5
For DDR4 power sequence
Red: Power Rail IN IN
Orange: Output from KBC 74LVC1G07GW VCCSTU_EN SLG59M1470VTR +V1.00U_CPU

A Out EN Out
Light Blue: Output from CPU
2D5V_S3 Page40 Page40
PWR_DCBATOUT_1D35V
1D2V_S3 DC SI7121DN-T1-GE3-GP
BT+ Page44 Vin
a Battery EN 1D35_S3 4
DCBATOUT OUT
Page43
CH035H-40PT0-GP SY8206DQNC
0D6V_S0 Page44 1D35V_VTT_PWRGD
Power Good
AC +DC_IN
SI7121DN-T1-GE3-GP VIN
a Adapter in
Page43 3D3V_S5 5V_S5
Page43
EN1 5V_S5
IN 5V_S0
AD+ EN Out
TPS51225RUKR
DC/DC G5016KD1U 3D3V_S0
EN2 (3.3V/5V) 3D3V_S5 Page40
D Charger D
3D3V_S5
BQ24770RUYR Page45 PGOOD
3V_5V_POK IN 1D5V_S0
EN Out
ACOK Page44 3D3V_AUX_KBC
d TLV70215DBVR
Page40
SIO_SLP_S4#
SIO_SLP_S3#
b PWR_CHG_ACOK
PM_SLP_S4# S5
3V_5V_EN
e 3 1D35V_S3
R2446 4
SWITCH
PR4475 Page24 APL5338XAI
Page40 S3 0D675V_S0
Page45 3 4
Page51
SLP_S4# SLP_S3#
c
ALWON
GPIO71
DPWROK
KBC_PWRBTN#
PSL_IN2#
The DSW rails must be stable for at least
1 10 ms before DSW_PWROK is asserted to PCH. H_VR_ENABLE
GPIO66
VR_EN 7
DSW_PWROK
KBC_DPWROK 3D3V_S5
ACAV_IN b PM_PWRBTN# Skylake-U MCP

VCI_OVRD_IN GPIO20 PWRBTN#
4 PM_SLP_S3#
RSMRST_PWRGD#
TBD KBC 2 Vcc
j ALL_SYS_PWRGD and VR_RDY assert,
PM_SLP_S0# AND Gate
Delay 10ms
delay 10ms; PCH_PWROK assert.
MEC1404 U74LVC1G08G-AL5 Y
RSMRST#_KBC: Delay 10 ms after receive 8 PCH_PWROK

5
RSMRST_PWRGD# and PM_SLP_SUS#. APWROK 6
AND
VCCSTG_EN
RSMRST#_KBC k
GPIO36 GPIO93 PCH_PWROK SLP_S0#
PCH_PWROK 1D0V_S5 5V_S5
PM_SUSWARN#
GPIO02 SUSWARN# PROCPWRGD VIN VDD
ALL_SYS_PWRGD l EN +VCCIO
6 GPIO26 9 VOUT
PM_SUSACK#
GPIO81 SUSACK#
SLG59M1470VTR
m AND
It is recommended that SYS_PWROK be asserted after RSMRST#_KBC Page40
RSMRST#
both PWROK assertion and processor core VR PWRGD assertion. 11 PCI_PLTRST#
k PLTRST#
PM_SLP_S4#
GPIO44
3
Delay 100ms
PM_SLP_S3#
4 GPIO01 H_VCCST_PWRGD ALL_SYS_PWRGD
6 Level Shifter
10 74LVC1G07GW Page17
C SYS_PWROK C
GPIO77 SYS_PWROK
EXT_PWR_GATE#
i GPIO05 SIO_SLP_SUS# 1D35V_VTT_PWRGD
SLP_SUS# EXT_PWR_GATE#
g 5
g 1D0V_S5_PWRGD ALL_SYS_PWRGD
Page24 5
3D3V_S5
ALL_SYS_PWRGD assert, SVID Transanctions g 1D8V_S5_PWROK 6
delay 100ms; SYS_PWROK assert. f
VIN
PCH_ALW_ON 3D3V_S5_PCH 6 ALL_SYS_PWRGD

VR_ON IMVP8
EN SW PWR_VCORE_VR_RDY
VR_READY CPU SVID Rails
SY6288C10CAC 7 SA/Core/GT
Page41
1D8V_S5_PWROK
g
SIO_SLP_SUS#
0R 0402
3V_5V_POK RSMRST_PWRGD#
PWR_DCBATOUT_1D0V e 0R 0402 j
1D0V_S5_PWRGD
i 0R 0402
Page40
VIN
EN
LX
1D0V_S5 h
SY8208DQNC 1D0V_S5_PWRGD 3D3V_S5 5V_S5
PGOOD
i
Page52
Vin VCNTL
Vout
1D8V_S5 f
1D0V_S5
3V_5V_POK
e EN APL5930KAI 1D8V_S5_PWROK
PGOOD
R1103 VCCPRIM_CORE
Page54
Page11
R1734 +VCCMPHYGTAON_1P0_LS_SIP
Page17
[dGPU] N16x Power-Up/Down Sequence

B B
[DG-07158-001_v03]
a b c d e f g h i j k l m
1 2 3a 4 4a 4b 5 6 7 8 9 10 11 12
A A
<Core Des ign>
Wistron Corporation
21F, 88, Sec.1, Hs in Tai Wu Rd., Hs ichih,
Taipei Hs ien 221, Taiwan, R.O.C.
Title
Size
Power Sequence
Docum ent Num ber Rev
A0
Starload SKL-U A00
Date: Thurs day, February 18, 2016 Sheet 102 of 106
5 4 3 2 1
5 4 3 2 1
DCBATOUT
Adapter TBD VR_EN VR_EN VR_EN 3D3V_VGA_S0 1D35V_VGA_EN
EN EN PWR_2D5V_PG EN
AOZ1268QI SY8288RAC-GP NCP81208MNTXG NCP81210MNTWG
EN
NCP81382MNTXG
EN EN
TypeC Adapter RT8812AGQW SY8288RAC
Charger NCP81382MNTXG NCP81382MNTXG
BQ24780SRUYR 1D0V_S5
D D
Battery BT+ 1D2V_S3 1D2V_S3 VCC_CORE +VCCGT

+V_VCCGTUS_VR +VCCSA_VR VGA_CORE 1D35V_VGA_S0
VCCPRIM_CORE
EN(S5) PWR_2D5V_PG
APL5338XAI-TRG EN(S3) SM_PGCNTL
0D6V_S0
PWR_3D3V_EN1
PWR_5V_EN1
EN
SY8286BRAC
EN
SY8288CRAC
3D3V_AUX_S5
5V_S5 3D3V_S5
5V_AUX_S5 5V_PWR_2
USB_PWR_EN# PM_SLP_S3# PM_SLP_S3# 1D05V_VGA_EN 3V_5V_POK SIO_SLP_S4# PM_SLP_S3# SIO_SLP_S3#
USB_CHG_EN
C EN EN EN C
EN EN EN
SY6288DAAC x 2 G5016KD1U RT8068AZQWID EN EN
M5938ARD1U
USB30_VCCA APL5930KAI APL5930KAI S-1339D15-M5001
3D3V_S0
USB30_VCCB 5V_S0
USB20_VCCC +V1.8A 2D5V_S3 1D5V_S0
SIO_SLP_S0#
1D05V_VGA_S0 VCCIO
EN
TPS22965DSGR
DGPU_PWR_EN
EN
5V_HDD
RT9724GB G5016KD1U
Power Shape
LCDVDD 3D3V_VGA_S0 Regulator LDO Switch
B B
A A
<Core Design>
Wistron Corporation
Title
Power Block Diagram
A2
Starload SKL-U A00
5 4 3 2 1
A B C D E
PCH SMBus Block Diagram 3D3V_S0

KBC SMBus Block Diagram
‧
3D3V_S5_PCH
‧ TP_VDD
3D3V_S0 SRN10KJ-5-GP
‧
‧
SRN2K2J-1-GP SMBus Address:0xA0/0xA1
DIMM 1
‧ ‧
SRN10KJ-5-GP
‧ ‧
SMBCLK MEM_SMBCLK PCH_SMBCLK
1
TouchPad Conn. 1
‧
SCL
SMBDATA MEM_SMBDATA PCH_SMBDATA
‧
SDA PS2_DAT0 DAT_TP_SIO DAT_TP_SIO TPDATA
PS2_CLK0 CLK_TP_SIO CLK_TP_SIO TPCLK

2N7002SPT SMBus Address:0xA0/0xA1
3D3V_AUX_KBC
DIMM 2
PCH_SMBCLK
PCH_SMBDATA
SCL
SDA
‧
3D3V_S5_PCH
3D3V_S5_PCH
‧
SRN4K7J-8-GP
‧ ‧‧ SRN33J-7-GP Battery Conn.

‧ ‧
SMB01_CLK18 SMBCLK1 PBAT_SMBCLK1 CLK_SMB
3D3V_S0 SMBus address:16
‧
SRN2K2J-1-GP SMB01_DATA18 SMBDA1 PBAT_SMBDAT1 DAT_SMB
SRN2K2J-1-GP
SML0CLK SML0_CLK
CYPD2122 ‧ HPA02224RGRR
‧
MEM_SMBCLK
SML0DATA SML0_DATA
MEM_SMBDATA
SMSC SCL
SDA SMBus address:0X13H/0X12H

SMBus Address:0x08 2N7002SPT MEC1404
2 2
GPIO73/SCL2
GPIO74/SDA2
PCH 3D3V_S0 SMBus Address:
‧
3D3V_S5_PCH 0x94/0x95/0x96/0x97
SRN2K2J-8-GP
3D3V_S0
‧
SRN2K2J-8-GP
‧ ‧ ‧ Thermal
‧ ‧ ‧
SML1_SMBCLK THM_SML1_CLK
SCL
SML1CLK
SML1_SMBDATA THM_SML1_DATA
SML1DATA SDL
NCT7718W
SMBus Address:0x82/0x83 SMBus Address:0x98/0x99
2N7002SPT
3D3V_VGA_S0
‧ SRN4K7J-8-GP
3D3V_VGA_S0
‧ dGPU
3 3
‧
‧ SMBus Address:0x9E/0x9C
SMB_CLK_VGA I2CS_SCL
SMB_DATA_VGA I2CS_SDA
5V_S0
‧ 0R2J-2-GP
DY
‧
‧ ‧
SRN2K2J-1-GP CMP_VOUT1 CMP_VOUT1
H_PROCHOT_EC
HDMI Level Shifter GPIO166/CMP_VREF1/UART_CLK LCD_TST_EN LCD_TST_EN
‧ 0R2J-2-GP
‧
DDPB_CTRLCLK CPU_DP1_CTRL_CLK DDC_CLK_HDMI
LCD_TST
DDPB_CTRLDATA CPU_DP1_CTRL_DATA DDC_DATA_HDMI
HDMI CONN
SMBus Address:0x80h/0x81h
4 4
<Core Design>
Wistron Corporation
Title
SMBUS Block Diagram

A B C D E
A B C D E
Thermal Block Diagram Audio Block Diagram

1 1
3D3V_S5_PCH 3D3V_S0 SPKR_L+

PAGE28 D+ NCT7718_DXP SPKR_L-
PCH MMBT3904-3-GP
SPKR_R-
SPKR_R+ SPEAKER
SC2200P50V2KX-2GP
D-
Thermal NCT7718_DXN Place near CPU
NCT7718 Codec
‧ ‧‧ ‧
PWM CORE
GPP_C6/SMML1DATA SDA
ALC3253
‧‧ ‧ ‧
2N7002
THM_SML1_DATA
GPP_C7/SML1CLK SCL
THM_SML1_CLK MMBT3904-3-GP AUD_HP1_JACK_L HP MIC
SML1_SMBDATA
SML1_SMBCLK
T8 Put under CPU(T8 HW shutdown) AUD_HP1_JACK_R
THERM_SYS_SHDN# 2N7002 D
PURE_HW_SHUTDOWN# SLEEVE COMBO
T_CRIT# EN
3V/5V RING2
2 PAGE18 S G RESET_OUT# 2
3D3V_S5_KBC
PAGE24
GPIO012 R2714
Digital
KBC GPIO013 GPIO0/DMIC_DATA
DMIC_DATA_R
0R2J-2-GP
DMIC_DATA
MIC
R2716
SMSC1404 CMP_VOUT0
KBC T8 HW shutdown GPIO1/DMIC_CLK
DMIC_CLK_R
0R2J-2-GP
DMIC_CLK
GPIO124 27K
CMP_VIN0_R
GPIO020
SCD1U16V2KX-3GP
SC100P50V2JN-3GP
GPIO56 GPIO050
NTC100K
FAN1_PWM
FAN_TACH1
GND GND GND
3 3
TACH
FAN
FAN_VCC1
VIN
5V
4 4
<Core Design>
Wistron Corporation
Title
Size
Thermal/Audio Block Diagram
Document Number Rev
Custom
Starload SKL-U A00
A B C D E
5 4 3 2 1
D D
C C
B B
<Core Design>
Wistron Corporation
A Taipei Hsien 221, Taiwan, R.O.C. A
Title
SIP connector
A
Starload SKL-U A00
5 4 3 2 1

5368 (Diagramas - Com.br)

Uploaded by

Copyright:

Available Formats

You might also like

5368 (Diagramas - Com.br)

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

5368 (Diagramas - Com.br)

Uploaded by

Copyright:

Available Formats

5 4 3 2 1

A DY : None Installed <Variant Name> A

UMA: UMA only installed Wistron Corporation

OPS: DISCRTE OPTIMUS installed Title

Free fall LDO-V1D8V

Thermal KBC INPUTS OUTPUTS

Fan Control Flash ROM MIC_IN/GND

Main Func = CPU

Main Func = CPU #544669 CRB Rev0.52

83.R2004.G8F Add resistor by NON DS3 function

(#543016) PROCHOT# Routing Guidelines

M1,2,3,4,5: <3 inches

Main Func = CPU

SKYLAKE_ULT M_A_DQ32 AY39 SKYLAKE_ULT AN45

M_A_DQS_DN[7:0] [12] M_B_DQS_DN[7:0] [13]

Main Func = CPU

PCH strap pin: 071.SKYLA.000U 2016/01/11 modify

[BDW Only]PHYSICAL_DEBUG_ENABLED (DFX PRIVACY)

DISPLAY PORT PRESENCE STRAP

Main Func = CPU

VCCSENSE_EOPIO_VR VCCGT VCCGTX_AK56 +VCCSFR

23e 23e R724

100R2F-L1-GP-U 1. Place close to CPU

SVID CLOCK #544669

H_CPU_SVIDCLK 1 R732 2 VR_SVID_CLK [46]

Main Func = CPU

E55 SKYLAKE_ULT C47

[38] PCH_DPC_N0 C50 DDI2_TXN[0] DDI EDP_AUXN E45 EDP_AUX_DN [55]

(#543016) eDP_RCOMP Guideline CPU_DP2_HPD R804 1 2 0R2J-2-GP CPU_DP_HPD_R [37,38]

(#543016) DDI Disabling and Termination Guidelines 3D3V_S0

PU to 3.3 V with 2.2-k

Main Func = CPU

2015/10/16 modify (Power team request)

Remove PC1033 and PC1035 (power team request)

IccMax current-10ms max[A] = 67 A

22U 0603 x35 (5 DY)

22U 0603 x13 (5 DY)

U-line 23e 28W

Main Func = CPU

PCH DERIVED RAILS UNSLICED GT VCCIO

Dummy : 20150123 Dummy : 20150123

C1175 near AB19

C1124 C1125 C1126 C1101 C1127

21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,

C1229 1D2V_S3 C1223 C1230 C1224 C1227

RF request 2016/01/12 modify

2 R1212 1 M_A_DQS_DN[7:0] [5]

By layou modify 20150916 3D3V_S0

Layout note: closed to Dimm 3D3V_S0

2 R1306 1 10KR2F-2-GP SA1_CHB_DIM0 EC1303

RN1301 R1305 2 R1311 1 M_B_DQS_DP[7:0] [5]

RF request 2016/01/12 modify

Main Func = PCH

CSI-2 SKYLAKE_ULT 10KR2J-3-GP

A36 CSI2_DN0 CSI2_CLKN0 C37

C31 E13 CSI2_COMP 1 R1501 2 100R2F-L1-GP-U

Main Func = PCH