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Diab Computer 3
Diab Computer 3
Diab Computer 3
Introduction to Computing
Week 5 – Virtual Class
Eighth Edition
By William Stallings
I/O
Processor Modules
Main System
Memory Bus
Processor
Referred to as
the Central
Processing Unit
(CPU)
Main Memory
n Volatile
nProvides for
communication among
processors, main memory,
and I/O modules
CPU Main Memory
0
System 1
PC MAR Bus 2
Instruction
Instruction
Instruction
IR MBR
I/O AR
Data
Execution
unit Data
I/O BR
Data
Data
I/O Module n -2
n -1
PC = Program counter
IR = Instruction register
Buffers MAR = Memory address register
MBR = Memory buffer register
I/O AR = Input/output address register
I/O BR = Input/output buffer register
processor reads
processor executes
(fetches) instructions
each instruction
from memory
Two steps
Fetch Stage Execute Stage
Interrupts
Disabled
Check for
Fetch next Execute interrupt;
START instruction instruction initiate interrupt
Interrupts
handler
Enabled
HALT
An interrupt occurs
while another interrupt Two approaches:
is being processed
• e.g. receiving data from • disable interrupts while
a communications line an interrupt is being
and printing results at processed
the same time • use a priority scheme
Memory Hierarchy
Greater capacity
Faster = smaller cost per
access time bit
= greater Greater
cost per bit capacity =
slower access
speed
The Memory Hierarchy
§ Going down the Inb
g-
Re rs
iste
k
Ou Dis
t
Sto board netic M
Ø increasing capacity
B
Of e
Ø decreasing frequency of
access to the memory by
the processor
Figure 1.4 The Memory Hierarchy
n Memory references by the processor tend to
cluster
n Datais organized so that the percentage of
accesses to each successively lower level is
substantially less than that of the level above
n Can
be applied across more than two levels of
memory
Secondary
Memory
Also referred to
as auxiliary
memory
• external
• nonvolatile
• used to store
program and data
files
n Invisible to the OS
n Interacts with other memory management hardware
n Processor must access memory at least once per instruction
cycle
n Processor execution is limited by memory cycle time
n Exploit the principle of locality with a small, fast memory
cache size
number of
cache block size
levels
Main
categories
are:
write mapping
policy function
replacement
algorithm
Cache and Block Size
n Multiple interrupts
multiprocessors
n Multicore computers
n The memory hierarchy