BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI - K. K.

BIRLA GOA CAMPUS

FIRST SEMESTER, 2019-2020
QUIZ I, ANALOG & DIGITAL VLSI DESIGN (EEE F313/INSTR F313)

Open Book Maximum Marks: 25 Date 11.09.2019

Name: ID. No.:

Q1. In NMOS, one terminal is connected to 1 V while other to -1 V. If threshold voltage is 0.5 V then, what is the maximum
voltage at the gate that can cause device to be in saturation? (Marks:2)
Ans: Maximum voltage at gate=
Q2. In PMOS, one terminal is connected to 1 V while other to -1 V. If threshold voltage is -0.5 V then, what is the minimum
voltage at the gate that can cause device to be in saturation? (Marks:2)
Ans: Minimum voltage at gate=  
W
Q3. If transconductance of NMOS with aspect ratio is gm and intrinsic impedance is ro for certain bias conditions,
  L
3W
then if aspect ratio is changed to keeping bias conditions constant, write down values of new transconductance,
3L
intrinsic impedance and intrinsic gain in terms of gm and ro . (Marks:6)
Ans: New transconductance= New intrinsic impedance=

New intrinsic gain=

W 10
Q4. For the circuit given below, if RS =10 kΩ, Io =0.2 mA, µnCox = 287 µA/V 2 , λn = 0.1V −1 , = , find Gm , Rout and gain
L 0.5
Av of the circuit. What is total resistance looking through source terminal of NMOS including RS ? Current source Io is ideal.

Ans: Gm = Rout = Av =

Total resistance looking through source terminal of NMOS including RS = (Marks:9)

W 10
Q5. For the circuit given below, if IREF =0.2 mA, µnCox = 287 µA/V 2 , Vtn =0.41 V, λn = 0.1V −1 ,
= for all transistors,
L 0.5
find minimum voltage required at P so that M3 and M2 remain in saturation. If voltage at P changes by ∆V =0.1 V, what will
be change in voltage at Y if all NMOS are in saturation? (Marks:6)

Ans: Minimum voltage at P= Change in voltage at Y=