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Testing Advanced Photovoltaic Inverters
Conforming to IEEE Standard 1547 – Amendment 1
Anderson Hoke, Student Member, IEEE, Sudipta Chakraborty, Senior Member, IEEE, and Thomas
Basso, Senior Member, IEEE
Abstract—This paper introduces a new test plan and provides
results for testing photovoltaic inverters with advanced grid
support features including voltage regulation, wider voltage and
frequency operating ranges, and voltage and frequency ride-
through, as allowed by IEEE Standard 1547-Amendment 1. The
test plan emphasizes testing for interactions between and among
advanced inverter features and conventional features (e.g.,
unintentional islanding), and it includes testing of inverter
dynamic response when regulating voltage. Results are included
from testing of a single-phase inverter and a three-phase inverter.
Index Terms—Inverters, photovoltaic, electric power systems,
reactive power control, voltage control, IEEE 1547, IEEE 1547.1.
I. INTRODUCTION
W ith large amounts of distributed energy resources
(DERs) such as photovoltaic (PV) systems being
deployed, newer DER interconnection functions are required
for reliable and efficient operation of electric power systems
(EPSs). The IEEE Standards Association has published an
amendment to IEEE Standard 1547-2003 (IEEE 1547) [1].
The amendment, IEEE Standard 1547a – Amendment 1 (IEEE
1547a), updates the 2003 published requirements for voltage
regulation and response to area EPS abnormal voltage and
frequency conditions, and considers whether other changes to
IEEE 1547 are necessary in response to these updates [2].
IEEE Standard 1547.1-2005 (IEEE 1547.1) specifies test
procedures to confirm whether DERs conform to the original
IEEE 1547 [3]. New test procedures are needed to verify the
conformance of advanced interconnection systems to the new
requirements of IEEE 1547a. The advanced grid-support
features can interact with each other and with conventional
inverter features. For example, the wider voltage and
frequency trip settings in IEEE 1547a could adversely impact
the effectiveness of the islanding detection algorithms.
Therefore, the new test procedures should verify that
interactions between features do not negatively affect grid
safety, stability, or power quality. Also, advanced grid-support
features operate on a range of time scales—from milliseconds
This work was supported by the U.S. Department of Energy under
Contract No. DE-AC36-08-GO28308 with the National Renewable Energy
Laboratory.
A. Hoke, S. Chakraborty, and T. Basso are with the National Renewable
Energy Laboratory, Golden, CO 80401 USA (email: andy.hoke@nrel.gov,
sudipta.chakraborty@nrel.gov, thomas.basso@nrel.gov).
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to many minutes—so the new test procedures should also test
DER dynamic responses.
Several efforts are under way related to advanced inverter
test plan development. The SunSpec Alliance is developing
standardized communications specifications for smart
inverters [3], which are based on work by the Electric Power
Research Institute (EPRI), International Electrotechnical
Commission (IEC), and others [4]–[7]. Sandia National
Laboratory is developing a test plan based on the SunSpec
specifications [8]. Some utilities have conducted their own
testing using internally developed procedures [9]. The
California Energy Commission (CEC), U.S. Federal Energy
Regulatory Commission (FERC), U.S. National Institute of
Standards (NIST), Underwriters Laboratories (UL), and other
organizations are also seeking to standardize advanced
inverter functions and test procedures [10]–[12]. Much of this
work is in response to the experience of German utilities with
high PV penetrations, where inverters have been retrofitted
extensively to mitigate high-penetration issues [13]–[14].
Successful deployment and standardization of inverters with
advanced grid-support features may allow the U.S. to avoid
such retrofitting.
The National Renewable Energy Laboratory (NREL)
developed a preliminary (beta) test plan for grid
interconnection systems of advanced inverter-based DERs.
This paper is a synopsis of the recently published NREL
technical report [15] that provides the beta test procedures for
advanced PV inverters. Two advanced PV inverters, one
single-phase and one three-phase, were tested under that beta
test plan and test results were included in the NREL report
[15]. In addition to the test results presented in [15], this paper
includes the results of additional tests investigating the impact
of advanced grid-support functions on unintentional island
detection.
The beta test plan was written before the first IEEE working
group meeting to develop IEEE Standard 1547.1-Amendment
1 (IEEE 1547.1a). The beta test plan is intended to support the
IEEE working group standard-development process and
provides additional experience beyond standards conformance
testing, such as inverter characterization testing.
Section II of this paper discusses the NREL-developed beta
test plan, including some representative figures showing
characteristics of the advanced functions. Sections III and IV
give sample test results for the single-phase and three-phase
inverters, respectively, tested at NREL. Section V discusses
the plan for the future work that includes testing using power
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hardware-in-the-loop (PHIL). Finally, Section VI provides combinations of operating conditions are tested, as under the
conclusions. magnitude tests.
Both the magnitude test and time test include procedures to
II. TEST PLAN test that any adjustable ride-through settings cannot be set in a
NREL’s beta test plan follows the format and methodology manner that interferes with trip settings.
established by IEEE 1547.1, while incorporating (1) upgraded
tests for response to abnormal voltage and frequency including
ride-through, (2) a newly developed test for voltage
regulation, and (3) modified tests for unintentional islanding,
open phase, and harmonics. Although IEEE 1547a does not
mandate ride-through requirements, its language does allow
such functionality, and future revisions may require it. Hence,
test procedures for ride-through are included in NREL’s test
plan. The details of the following test procedures are in [15].
A. Test for Response to Abnormal Voltage Conditions
The purpose of this test is to verify that the PV inverter
interconnection component or system ceases to energize the
area EPS as specified in IEEE 1547a with respect to Fig. 1. Widest allowable voltage trip magnitudes and maximum clearing
overvoltage and undervoltage conditions. In contrast to the times from IEEE 1547a. (Not to scale)
original IEEE 1547.1, the NREL test plan provides a single
test procedure to cover both overvoltage and undervoltage. tC5 EUT must disconnect
The test procedure consists of two parts: magnitude testing VT5
and time testing. tC4 VT4
tR4 VR4
Under the magnitude testing, test procedures for three tR3
VR3
different inverter behaviors are developed to validate that (1) EUT must remain connected VR2
clearing voltage levels are in compliance with IEEE 1547a, (2) tR2 VT3
adjustable clearing voltage levels and associated times behave tR1 VR1
tC3

as expected (for inverters that implement adjustable clearing

voltages), and (3) adjustable “must remain connected” voltage
ride-through magnitude settings behave as expected (if voltage
ride-through settings are implemented in the inverter).
Voltage ride-through behavior is defined by specifying a range
of voltage disturbances and disturbance times for which the
inverter must remain connected to the EPS (i.e., must not trip).
Voltage trip and ride-through magnitudes are tested by slowly
ramping the EPS voltage up (or down) at a rate designed to
allow determination of the exact voltage magnitude that
causes the inverter to trip. Multiple combinations of operating
conditions are tested including tests for various trip settings,
phases, ride-through settings, and voltage regulation settings.
The allowable voltage trip magnitudes and associated
maximum clearing times from IEEE 1547a are shown in Fig.
1. Fig. 2 shows an example inverter configuration with both
voltage trip settings and voltage ride-through settings.
Similarly to the magnitude tests, the voltage time test
procedures verify three different inverter behaviors: (1)
clearing times at various voltage levels are in compliance with
IEEE 1547a, (2) adjustable clearing times at various voltage
levels behave as expected (for inverters with adjustable
clearing times), and (3) adjustable “must remain connected”
voltage ride-through time settings behave as specified by the
manufacturer (if voltage ride-through settings are
implemented in the inverter). Voltage ride-through and trip
times are measured using prescribed voltage steps designed to
determine the time between the start of an over/undervoltage
and the disconnection of the inverter from the EPS. Multiple
tC2 VT2
VT1
EUT must disconnect
tC1
Time
Fig. 2. An example of voltage trip and ride-through boundaries. EUT =
equipment (inverter) under test.
B. Test for Response to Abnormal Frequency Conditions
The test procedures for abnormal frequency conditions are
similar to those for abnormal voltage. They verify that the
inverter’s response to over- and underfrequency conditions is
compliant with IEEE 1547a, and that voltage ride-through
performs as expected, if implemented.
Similarly to the abnormal voltage test, the frequency test
includes procedures to verify the frequency magnitudes at
which the inverter trips and the time to trip for each frequency
level. The description of each test is similar to those for the
voltage tests described in the previous section. Fig. 3 shows
the default trip frequencies given in IEEE 1547a and the
associated maximum clearing times for each frequency level.
Both the magnitude test and the time test include procedures
to test that any adjustable ride-through settings cannot be set
in a manner that interferes with trip settings.

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Fig. 3. Default trip frequencies and maximum clearing times from IEEE
1547a.
C. Test for Voltage Regulation through Volt-VAR Control
The purpose of this test is to verify that the PV inverter
provides voltage support by producing or absorbing reactive
power as specified by the manufacturer. If the inverter is not
capable of modifying its power factor or reactive power
output, this test shall not be performed. Multiple methods of
reactive power support are possible. The NREL beta test plan
currently covers provision of reactive power as a function of
voltage based on a Q(V) characteristic [15].
In the test procedure, maximum available reactive power is
defined according to the inverter manufacturer’s
documentation. Test procedures are provided for testing
various Q(V) characteristics including those that include
deadband and/or hysteresis. An example Q(V) characteristic
with hysteresis and deadband is shown in Fig. 4. The test plan
specifies voltage profiles to test each of these Q(V)
characteristics. An example test voltage profile is shown in
Fig. 5. The voltage ramp rate is specified based on the settling
time of the inverter’s Q(V) response to be slow enough that
the inverter’s reactive power is in quasi-steady-state during the
ramp; hence, we refer to this test as the quasistatic volt-VAR
test. Fig. 6 shows the pass/fail criteria for measured reactive
power during the test. In addition to testing the steady-state
Q(V) characteristic, the test plan also verifies that the
inverter’s dynamic response to voltage steps while in volt-
VAR mode is in line with the manufacturer’s stated rise time,
settling time, and overshoot value.
Fig. 4. Q(V) characteristic including hysteresis and deadband.
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Fig. 5. Sample test voltage profile.
Fig. 6. Acceptable range of measured reactive power relative to the
commanded characteristic, where b = a1 + n, n is the maximum amplitude of
noise in the RMS voltage measurement, a1 is the manufacturer’s stated
accuracy of voltage, and a2 is the manufacturer’s stated accuracy of reactive
power.
D. Unintentional Islanding Test
Two steps are added to the original IEEE 1547.1 test
procedure to ensure that the inverter’s island detection system
continues to function appropriately in the presence of four
advanced grid-support features: (1) wider voltage operating
range, (2) wider frequency operating range, (3) voltage
regulation, and (4) frequency response/regulation. The
standard islanding test is repeated in the presence of selected
combinations of these four advanced features.
E. Other Modified Tests
The NREL beta test plan also includes modified tests for
open phase and harmonics. The open-phase test from IEEE
1547.1 is repeated while performing each of the four advanced
grid-support features listed above individually, and while
performing all four simultaneously. The harmonics test from
IEEE 1547.1 is repeated with voltage regulation running and
again with grid-frequency response/regulation running.
III. SINGLE-PHASE INVERTER TEST RESULTS
Two inverters were tested at NREL to evaluate the beta test
plan. One was a commercially available single-phase 3-kW
advanced PV inverter. The other was a prototype three-phase
50-kW inverter developed at NREL. Although the NREL test
plan calls for repetition of various tests, most tests were run
only one or two times per inverter for evaluation purposes.
Selected results from the testing of both inverters are
discussed in this section and the next. For complete results,
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see [15]. 1.5

A simple diagram of the test setup is shown in Fig. 7. It

voltage / current, p.u.

includes a controllable DC supply, a resistive-inductive- 1
Trip time = 12.96 s
capacitive (RLC) load bank, and a controllable AC power
supply (grid simulator). For the single-phase tests, the nominal 0.5 Vrms
grid voltage was 240 V AC, and the nominal DC voltage was Irms
250 V DC. As in IEEE 1547.1 testing, it is assumed that PV
0
variability will not impact the inverter’s interconnection 15 20 25 30 35
time,
time,seconds
seconds
system, so the PV array (or other energy source) is represented
Fig. 8. Inverter RMS voltage and current during a voltage time test with
by a DC supply for testing purposes. Communication with the volt-VAR control running.
inverter was established through RS-485 using the 1.5
manufacturer’s proprietary protocol. Features tested were

voltage / current, p.u.

multi-level voltage trip settings, multi-level frequency trip 1
settings, unintentional islanding, volt-VAR control (voltage
regulation), and high-frequency power curtailment. 0.5
Vrms
Irms
0
30 35 40 45 50 55
time, seconds
Fig. 9. Inverter RMS voltage and current during a voltage time test without
volt-VAR control running.

Table II shows abnormal voltage trip magnitudes. Again,

the inverter passed all tests both with and without volt-VAR
Fig. 7. Advanced inverter test setup single-line diagram. running. Fig. 10 shows the results of an undervoltage
magnitude test at the 60% voltage level with volt-VAR control
Table 1 shows abnormal voltage trip times for each of the running. Note that the steep voltage ramp serves to reach the
settings tested. The inverter passed all voltage trip time tests, holding voltage prior to the test; the actual test ramp is nearly
both with and without volt-VAR running. No evidence was imperceptible. The same test without volt-VAR control
found that volt-VAR control impacts the trip time or running was nearly identical.
magnitude. In all tests, the inverter tripped within 0.03 to 0.06
second of the designated time. The trip magnitude tests were TABLE II
similar in that performing volt-VAR control did not VOLTAGE TRIP MAGNITUDE TESTS FOR SINGLE-PHASE INVERTER
Volt-VAR Voltage Trip Trip Time Measured Trip Result
significantly impact the test results and in that the inverter
Setting Setting (%) Setting (s) Voltage (%)
consistently tripped very close to the designated voltage Off 60 0.16 60.32 Pass
magnitude. 60 0.16 60.2 Pass
88 10 88.27 Pass
TABLE I 110 13 109.56 Pass
VOLTAGE TRIP TIME TESTS FOR SINGLE-PHASE INVERTER 120 0.16 119.35 Pass
Volt-VAR Voltage Trip Trip Time Measured Result On (with 45 0.16 47.1 Pass
Settings Setting (%) Setting (s) Trip Time (s) deadband) 60 0.16 60.2 Pass
Off 60 0.16 0.13 Pass 60 0.16 60.2 Pass
88 10 9.96 Pass 88 10 88.2 Pass
110 13 12.94 Pass 110 13 109.6 Pass
120 0.16 0.13 Pass 120 0.16 119.6 Pass
On 60 0.16 0.13 Pass
(with 88 10 9.96 Pass 1.5
deadband) 110 13 12.96 Pass Vrms
voltage / current, p.u.

120 0.16 0.13 Pass Irms

1

Fig. 8 shows plots of RMS inverter voltage and current

during typical trip time tests at the 110% voltage level with 0.5

volt-VAR control running, and Fig. 9 shows the same test

without volt-VAR control running. No significant difference is 0
evident. 8 9 10 11 12 13 14 15 16
time, seconds
Fig. 10. Inverter RMS voltage and current during a voltage magnitude test
without volt-VAR control running.

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The inverter also passed all frequency tests for both 65 2

magnitude and time. Table III shows the trip times and Table
IV shows the trip frequencies. No evidence was found that frequency

frequency, Hz

current, p.u.
high-frequency power curtailment interferes with the Irms
inverter’s ability to respond correctly to abnormal frequencies. 60 1
In all frequency magnitude tests, the inverter tripped within
0.02 Hz of the commanded frequency. In all frequency time
tests, the inverter tripped when 90% of the clearing time had
passed (minus a few AC line cycles). 55 0
5 10 15 20 25 30 35
time, seconds
TABLE III
Fig. 12. Inverter RMS current and grid frequency during a frequency
FREQUENCY TRIP TIME TESTS FOR SINGLE-PHASE INVERTER
magnitude test with high-frequency power curtailment running.
Frequency Volt- Frequency Trip Time Measured Result
Response VAR Trip Setting Setting (s) Trip
Setting Setting (Hz) Time (s) Although this inverter does not claim voltage or frequency
Off On (with 56 10 8.99 Pass ride-through capability, its responses to abnormal voltage and
deadband) 58 300 269.91 Pass frequency are very consistent. Therefore, by setting the trip
62 90 80.96 Pass magnitudes and times slightly outside any desired ride-through
64 10 8.98 Pass
boundaries, the inverter could be configured to remain
Off Off 57 0.16 0.12 Pass
60.5 0.16 0.11 Pass connected during a given set of voltage and frequency
64 2 1.77 Pass deviations. For example, a frequency trip setting of 62 Hz and
20% Slope Off 64 0.16 0.10 Pass 10 s could be interpreted to imply that the inverter will ride
40% Slope 56 0.16 0.12 Pass through any frequency disturbance up to 61.98 Hz and 8.94
40% Slope 64 0.16 0.13 Pass
seconds.
The inverter is capable of adjusting its reactive power
TABLE IV
FREQUENCY TRIP MAGNITUDE TESTS output as a function of voltage (volt-VAR control). It can do
Frequency Volt- Frequency Trip Time Measured Result so following a Q(V) characteristic with or without deadband
Response VAR Trip Setting Setting (s) Trip Freq. or hysteresis. Various tests were completed with different
Setting Setting (Hz) (Hz) Q(V) characteristics chosen to thoroughly verify the inverter’s
Off Off 56 0.16 56.01 Pass
range of volt-VAR settings. Fig. 13 shows sample results from
58 10 58.00 Pass
62 10 62.02 Pass one volt-VAR test in which the inverter Q(V) characteristic
64 0.16 64.00 Pass was set with deadband. Note that the measured Q(V)
P(f) 20% Slope Off 64 0.16 64.01 Pass characteristic follows discrete steps. The measured results
P(f) 40% Slope 64 0.16 64.00 Pass follow the Q(V) characteristic well in the deadband regions
and near nominal voltage but deviate slightly when voltage
Figs. 11 and 12 show the inverter RMS current and AC goes away from nominal.
frequency during frequency magnitude tests at the 64 Hz level
without and with high-frequency power curtailment running, 2000
re a c tiv e p o w e r, V A r

respectively. Measured trip frequencies were identical. Q

In Fig. 11, note that as the frequency ramps up steeply, the Qcmd
inverter current increases. This is unexpected behavior. During 0
this time, the inverter is importing reactive power, apparently
due to its grid synchronization controls falling slightly out of
-2000
sync with the increasing grid frequency, causing the inverter 210 220 230 240 250 260 270
current to lag the voltage. After the steep ramp ends, the RMS voltage, V
inverter recovers synchronization in about 2 s. Fig. 13. Inverter reactive power vs. voltage during a test of volt-VAR control
with deadband.
65 2
Fig. 14 shows an enlarged plot of measured and
commanded reactive power during a similar test with a
frequency, Hz

different Q(V) command. Note that in this test, the measured

current, p.u.

60 1 reactive power exceeds the commanded reactive power for

high voltages, whereas in Fig. 13 the measured reactive power
frequency is below the command for high voltages. Fig. 14 demonstrates
Irms the method used to determine whether the measured reactive
55 0
5 10 15 20 25 30 35 power is close enough to the commanded reactive power to
time, seconds
pass the test (see Fig. 6). The manufacturer’s specified
Fig. 11. Inverter RMS current and grid frequency during a frequency
magnitude test without high-frequency power curtailment running. accuracy of reactive power (a2) is not known, but would need
to be at least 200 VAR to pass the test.

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TABLE VI
Q ISLAND TRIP TIMES FOR SINGLE-PHASE INVERTER
-800 Frequency Volt- Trip Load Quality Measured Trip Result
Qcmd
reactive power, VAr

Response VAR Settings Factor Time (s)

-1000 Off Off 1547 1.0 0.259 Pass
Off Off 1547 1.0 0.277 Pass
-1200 Off Off 1547a2 1.0 0.626 Pass
Off Off 1547a 1.0 0.655 Pass
-1400 Off Off 1547a 1.0 0.661 Pass
Off Off 1547a 1.0 0.600 Pass
-1600 Off Off 1547a 1.0 0.626 Pass
247 248 249 250 251 252 253 254 255 256 Off On 1547a 1.0 0.661 Pass
L-L voltage, Vrms Off On 1547a 1.0 0.618 Pass
Fig. 14. Close-up of inverter reactive power vs. voltage during a volt-VAR On On 1547a 1.0 0.339 Pass
test, illustrating how the worst-case deviation between commanded and On On 1547a 1.0 0.259 Pass
measured Q(V) can be used to evaluate whether the inverter meets the test Off Off 1547 2.5 0.285 Pass
criteria. Off Off 1547 2.5 0.306 Pass
On On 1547a 2.5 0.272 Pass
On On 1547a 2.5 0.277 Pass
Fig. 15 shows a sample test of the inverter’s dynamic On On 1547a 2.5 0.335 Pass
response to voltage steps while in volt-VAR mode. The
reactive power response is nearly critically damped, with no In all cases, the inverter passes the test by disconnecting in
overshoot or ringing, thus passing the test. less than 2 seconds. However, note that although the
4000 disconnection times are ≤ 0.34 s without advanced grid-
support running, they are ≥ 0.6 s in the tests with advanced
voltage, p.u

2000
1 0
grid-support features running. It was generally found to be the
VA

case that wide voltage and frequency operating regions extend

0.8
0 5 10 15 20 25
time, seconds
Fig. 15. Inverter reactive power and voltage during a volt-VAR dynamic test.
The original unintentional islanding tests shown in [15]
were performed using a PHIL-based method [16]. However,
for this paper, additional islanding tests were performed using
the standard RLC load method from IEEE 1547.1, and those
tests were repeated with advanced grid-support features
running. Table V defines three configurations of abnormal
voltage and frequency trip settings: 1547 uses the original trip
settings from IEEE 1547; 1547a uses the widest trip settings
-2000
V the island disconnection time to between 0.6 and 0.7 seconds,
Q
30 35 although high-frequency power curtailment actually negates
P
that effect, bringing disconnection time down to between 0.25
and 0.35 seconds even with wide voltage and frequency
operation ranges. It is not known what type of island detection
scheme this inverter uses. Fig. 16 shows an unintentional
islanding test without any advanced grid-support features
running. Fig. 17 shows the same test with voltage and
frequency trip levels and times set to their widest settings, and
with volt-VAR control running.
Vrms
Irms
voltage, current, p.u.

1
from IEEE 1547a; and 1547a2 uses the widest voltage trip Grid on
settings from IEEE 1547a, along with the original IEEE 1547
frequency trip settings. Table VI shows the trip times for the 0.5
unintentional islanding tests.
Trip time = 0.259 s
0
TABLE V
DISCONNECTION SETTING CONFIGURATIONS FOR ISLANDING TESTS 1.6 1.8 2 2.2 2.4 2.6 2.8 3
Name Fast Slow Slow Fast Overfreq. Underfreq. time, seconds
Overvolt. Overvolt. Undervolt. Undervolt.
Fig. 16. Unintentional islanding test without advanced grid support on.
1547 120% 110% 88% 50% 60.5 Hz 59.3 Hz,
0.16 s 1s 2s 0.16 s 0.16 s 0.16 s
1547a 120% 110% 60% 45% 64 Hz 56 Hz
0.16 s 13 s 10 s 0.16 s 10 s 10s Vrms
voltage, current, p.u.

1547a2 120% 110% 60% 45% 60.5 Hz 59.3 Hz, 1 Irms

0.16 s 13 s 10 s 0.16 s 0.16 s 0.16 s Grid on

0.5

1.6 1.8 2 2.2 2.4 2.6 2.8 3

time, seconds
Fig. 17. Unintentional islanding test with advanced grid support running.

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or 110 2 109.61 Pass

hysteresis 120 0.16 111.56 Pass

Five islanding tests were performed with the quality factor 1.5

voltage and current, p.u.

(QF) of the resonant load tuned to 2.5 as suggested in IEEE
Standard 929-2000 [17] (rather than 1.0 as prescribed in IEEE 1 Trip voltage =
1547.1 and in [15]) to investigate whether a less-damped 109.61%
resonance would lead to longer disconnection times. These
0.5 Vrms
tests were performed both with and without advanced grid-
Irms
support functions running. Disconnection times in these five
tests were similar to the corresponding tests with a QF of 1.0; 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
no evidence was found that a QF of 2.5 extends islanded time, seconds
disconnection time. Fig. 18. An overvoltage magnitude test with advanced grid support running.

IV. THREE-PHASE INVERTER TEST RESULTS Tables IX and X show frequency trip times and magnitudes,
The test setup for the three-phase prototype inverter was respectively. Fig. 19 shows an overfrequency time test at the
similar to the single-phase setup (Fig. 7). The nominal DC 64 Hz level with a 6 s disconnection time, without advanced
voltage was 450 V and the nominal AC line-to-line voltage grid support running. The inverter passes the test, but note that
was 208 V RMS in a three-wire delta configuration. the frequency step induces significant ringing in the current
Responses to abnormal voltage and frequency were waveform, which should be addressed as the prototype is
generally similar to those for the single-phase inverter. Tables refined.
VII and VIII show voltage trip times and magnitudes,
TABLE IX
respectively. Both disconnection magnitudes and
THREE-PHASE INVERTER FREQUENCY TRIP TIME TESTS
disconnection times were very close to the commanded Trip Magnitude Trip Time Measured Trip Result
magnitudes and times, though disconnection times were Setting (Hz) Setting (s) Time (s)
typically one to four cycles longer than commanded because 56 0.16 0.18 Pass*
this prototype inverter does not account for fixed delays in the 56 6 6.021 Pass*
59.5 300 299.98 Pass
disconnection process. Volt-VAR control did not impact
64 6 6.02 Pass*
disconnection times. Fig. 18 shows a voltage magnitude test at 64 0.16 0.183 Pass*
the 110% voltage level. *Trip timer needs adjustment for fixed delays

TABLE VII TABLE X

THREE-PHASE INVERTER VOLTAGE TRIP TIME TESTS THREE-PHASE INVERTER FREQUENCY TRIP MAGNITUDE TESTS
Volt-VAR Voltage Trip Trip Time Measured Trip Result Trip Magnitude Trip Time Measured Trip Result
Setting Setting (%) Setting (s) Time (s) Setting (Hz) Setting (s) Freq. (Hz)
Off 45 0.16 0.234 Pass* 56 0.16 55.99 Pass
60 11 11.028 Pass* 59.5 6 59.49 Pass
88 21 21.03 Pass* 60.5 6 60.51 Pass
110 2 2.043 Pass* 64 0.16 63.99 Pass
110 13 13.043 Pass*
110 13 13.047 Pass* 80 2
112 0.16 0.187 Pass*
On, without 45 0.16 0.194 Pass* 60 1.5
deadband or
frequency, Hz

60 11 11.024 Pass*
current, p.u.

hysteresis 88 21 21.03 Pass*

40 1
110 13 13.048 Pass* frequency
120 0.16 0.19 Pass* Irms
20 0.5
*Trip timer needs adjustment for fixed delays

0 0
TABLE VIII 0 1 2 3 4 5 6 7 8 9
THREE-PHASE INVERTER VOLTAGE TRIP MAGNITUDE TESTS time, seconds
Volt-VAR Voltage Trip Trip Time Measured Result Fig. 19. An overfrequency time test without advanced grid support running.
Setting Setting (%) Setting (s) Trip Time (s)
Off 45 0.16 45.19 Pass
Fig. 20 shows the measured and commanded Q(V)
60 2 60.14 Pass
88 2 88.06 Pass
characteristic for a quasistatic volt-VAR test. The measured
110 2 109.82 Pass reactive power matches the command very well.
112 0.16 111.72 Pass
On, 45 0.16 45.10 Pass
without 60 2 60.001 Pass
deadband 88 2 88.13 Pass

978-1-4799-4398-2/14/$31.00 ©2014 IEEE 1020

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) <
reactive power, VAr
5000
0 inverter dynamic response for functions such as volt-VAR
-5000
100 110
120 130
L-N voltage, Vrms
Fig. 20. A three-phase quasistatic volt-VAR test.
Fig. 21 shows a dynamic volt-VAR test. The reactive power
resonates significantly following each voltage step, causing
corresponding ringing in the point of common coupling (PCC)
voltage. Again, this ringing should be addressed by modifying
the inverter controls.
1.2
voltage, p.u
1 0
0.8
0 5 10 15 20
time, seconds
Fig. 21. A three-phase dynamic voltage step response test of volt-VAR.
V. FUTURE WORK
Future work will investigate other emerging inverter
features, including ceasing to export power without
disconnecting during transient undervoltage events, returning
to service after those events, other methods of voltage support,
and methods of frequency support.
Inverter test procedures have historically focused on testing
a single inverter at a single PCC. However, some advanced
inverter functions (such as volt-VAR) will impact the EPS in
which the inverter is connected, requiring dynamic feedback
between the inverter test article and the EPS. Significant
future work using PHIL is planned for testing the advanced
grid-support features under conditions that simulate EPS
dynamics for realistic testing of one or more inverters.
VI. CONCLUSIONS
Due to the emerging nature of interconnection standards,
test procedures for the new interconnection functions—such as
voltage regulation and wider voltage and frequency operating
ranges—are not yet fully harmonized. This paper covers the
important topic of advanced inverter testing based on a
recently published NREL report. The test plan summarized
here follows the framework established by IEEE 1547.1 while
establishing new and modified tests for the advanced grid-
support features. These test procedures consider not only the
individual interconnection functions but also the interactions
among various new and existing features.
The preliminary test plan was applied to two inverters and
worked well for both. Some interesting observations were
made from initial testing such as (1) separate voltage and
frequency ride-through settings may not be necessary if the
trip test results adhere closely to commanded values, and (2)
performing voltage or frequency ride-through (or having a
978-1-4799-4398-2/14/$31.00 ©2014 IEEE
8
wide band of operating voltages and frequencies) may prolong
Q the trip time during unintentional-islanding tests. Test results
Qcmd presented here also emphasize the importance of testing
control.
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1
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1021