IEEE TRANSACTIONS

ELECTRON
ON DEVICES, VOL. ED-33, NO. 4, APRIL 1986 477

Polycrystalline-Silicon Device Technologyfor

Large-Area Electronics
WILLIAM G. HAWKINS

Abstract-The process sequence used to fabricate post-hydrogenated steps involved is a novel feature of polycrystalline-silicon
polycrystalline silicon thin-film devices has a dramatic impact on per- thin-film MOS devices. In addition to fundamental inter-
formance. A near-optimal process for devices that have hole mobilities
of up to 50 cmZ/V . s and electron mobilities of 70 cmZ/V s is dem-
est, knowledge of the performance achievable as a func-
onstrated. These observed mobilities are substantially higher than pre- tion of process temperature allows for assessment of trade-
vious literature reports. Implantation of boron or phosphorus into the offs between substrate cost and performance. In previous
polycrystalline-silicon device channel after the gate-oxidation step al- work, p-channel devices were fabricated anddegenerately
lows threshold-voltage tailoring for achievement of either enhance- doped polysilicon under the device was used as a gate.
ment- or depletion-mode operation of n- and p-channel devices. These
results indicate that CMOS or NMOS logic could be fabricated using
The present study explores fabrication routes to top-
polycrystalline-silicon devices. Devices with steam-grown gate oxides gated self-aligned structures that are suitable for large-
have reduced channel mobility in comparison with devices oxidized in areaelectronicsapplications.It was previously demon-
dry 0, at the same temperature. Possible mechanisms for the variation strated that polycrystalline-silicon thin-film devices can
in performance with oxidation conditions are discussed. be fabricated to achieve high channel mobility and low
leakage [6]. Here, deposition of the channel as an amor-
I. INTRODUCTION phous or polycrystalline layer,the effect of oxidation tem-
perature (900 to 1100°C) and ambient (steam or dry O,),
A MORPHOUS-SILICON device technology has
played adominant role inlarge-areaelectronics.
Amorphous silicon has advantages in large-area applica-
the effect of gate material, and the impact of hydrogena-
tion timeondevice performance areexplored. Device
performance was characterized by measurement of chan-
tions because devices can be fabricated on low-cost glass
nel mobility, device leakage, and threshold voltage for
substrates. Two undesirableconsequences of low-temper-
both n- and p-channel devices.
ature plasma-deposited devices are low channel mobility
(typically below 1 cm2/V s) [l] and electron traps in the 11. DEVICEFABRICATION
plasma-deposited insulator used as the gate dielectric [2].
The substrates used for fabrication of the devices were
The low carrier mobility of amorphous silicon results in
(100) 10-s2 cm p-type 75-mm wafers. After a cleaning
modest maximum operating frequencies [ l ] of logic cir-
procedure, 660 nm of Si02 was grown on the wafers in
cuits, while insulator carrier traps are responsible for noise
640 torr of pyrogenic steam. The silicon channel layer
inanalog circuitry [3], [4]. An alternativematerialfor
was then deposited in a commercial low-pressure chemi-
large-area electronics is polycrystalline silicon. Polycrys-
cal-vapor deposition (LPCVD) system. The temperature
talline-silicon deviceshave previously been fabricated
of the deposition tube was selected to produce either
with a channel mobility of 7 cm2/V * s [51 and are there-
amorphous or polycrystalline channel layers [7]. The de-
fore capable of higher frequency operation. Additionally,
vice channels were doped either priorto or after oxidation
it would be anticipated that a gate dielectric formed by
using ion implantation. Following patterning of the de-
themal oxidation of silicon would be largely devoid of
vice body, a gate oxide was grown to a thickness of 105
theinsulator trapping sites that areadisadvantagein
nm in either steam or dry oxygen at several temperatures.
amorphous-silicon device technology in analog applica-
The channel was then masked from the source-drain im-
tions [2].
plant using photoresist for Al-gate technology or 600 nm
To date, there has been no systematic published study
of LPCVD polysilicon for self-aligned polysilicon-gate
of how polycrystalline-silicon MOSFET device process-
technology. In most cases, the polysilicon was doped nf
ingimpactsonperformance. The study presented here
by solid-source diffusion at 880°C for 45 min. Following
demonstrates that mobility and threshold voltage can be
implantation of the source and drain with phosphorus or
varied by over a factor of twenty with changes in oxida-
boron,the wafers were cleaned and then annealed at
tion,channel-depositionconditions, and hydrogenation
1000°C for 30 min inN2. Vias were opened in the oxide
conditions. The sensitivity of performance to the process
over the source and drain. The wafers were cleaned and
1-pm Al/1-percent Si was deposited and delineated. The
Manuscript received July 3, 1985; revised December 4, 1985.
The author is with the Webster Research Center, Xerox Corporation,
wafers were then sintered at 400°C for 15 min in N2. Fol-
Webster, NY 14580. lowingsintering,
devices
were post-hydrogenated at
IEEE Log Number 8607548. 300°C for various times. Hydrogenation was carried out
0018-9383/86/0400-0477$01.00 O 1986 IEEE
478
-25 pm-
6 6 0 nm S i 0 2
Fig. 1. Schematic cross-sectional view of the experimental device stmc -
tures studied (W/L = 1.0).
in a commercial parallel-plate plasma-deposition system.
The plasma was excited at 300 kHz. The hydrogenation
conditions were 300"C, 350 W, and 400 mtorr in 50-per-
cent €3,
in N,. A diagram of itypical completed devics:
is shown in Fig. 1.
111. CHANNEL MOBILITY EXPERIMENTS
Polycrystalline-deposited silicon was compared wit I
amorphous-deposited silicon channels in the first experi-
ment. The devices were fabricated with aluminum gates
and were post-hydrogenated for 30 min. Oxidation was
carried out following ion implantation of the channel with
3 X 1012 cmP2boron. Fig. 2 illustrates that the mobility
of amorphous-deposited silicon p-channel devices is twice
the mobility of devices that have polycrystalline-depm .-
ited channels. Comparison of channel mobilities in satu-
ration and at small source-drain voltage indicated a di-'-
ference of lessthan 10 percent, so both methods o f
channel mobility measurement yield equivalent results
A recent study of LPCVD silicon deposited as an amo7-
phous layer and allowed to crystallize by solid-phase nu-
cleation reveals that grain size is largein comparison wilh
LPCVD silicon deposited as a polycrystalline film [71.
The crystallization of the deposited amorphous films is
complete upon annealing at 900°C for 30 min in N2 with
0.5-percent 0,. The preferred orientation of amorphouj-
deposited films after crystallization is (111>, while
polycrystalline-deposited films have a predominately
( 110) orientation under usual deposition conditions [E].
Consequently, large grain size and/orpredominant ( 11:. )
film orientation may play a role in the high channel mo-
bility observed foramorphous-deposited channels. A fin a1
factor that may improve channel mobility of channels that
were deposited as amorphous material is the smoothness
of oxides that can be formed on thesefilms. Oxidation of
polycrystalline-deposited silicon leads to a rough surface
texture [7]. The smoothness of the silicon-SiO, interface
affects channel mobility since rough surface texture i n -
creases carrier scattering from the interface. The results
do not clearly indicate whether surface texture, grainshe,
or preferred film crystalline orientation is responsible for
the mobility improvement. Experiments that will provide
more understanding are currently underway.
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-33, NO. 4, APRIL 1986
lor
Tax= 1050°C
.
-
N
-
.-.
4
8-
-
fox = 105 nrn
FY
0 6-
0~"'"'""
0 -10 -20
vg (volts)
Fig. 2. Plot used toderive channel mobility and threshold voltage for
polycrystalline- and amorphous-deposited p-channel devices with A1
gates.
The level of boron channel doping did not affect the
device threshold voltage over theimplant range of lot2to
l O I 3 cm-, when implantation occurred prior to oxidation.
Since control of threshold is important for many applica-
tions, this problem will be addressed later in this paper.
IV. OXIDATION AND HYDROGENATION
A set of experiments was conducted toexamine a
broader range of oxidation and hydrogenation conditions.
Both n- and p-channel devices with channel inplants of 3
X 10" boron for p-channel and 3 X loi2cm-2 phospho-
rus for n-channel devices were fabricated. In this case,
amorphous-deposited channels were oxidized at 1000,
1050 and 1100°C in dry O2 and 900 and 1000°C in pyr-
ogenic steam. Gates were fabricated from degenerately
doped (30 WCI) n+ polysilicon. Mobility and threshold
were measured as a function of hydrogen-plasma expo-
sure time.
Dry O2 and pyrogenic-steam-oxidized devices behave
very differently as shown in Fig. 3. Hydrogenation of dry-
oxidized devices improves mobility initially and then re-
duces the channel mobility, while hydrogenation of steam-
oxidized devices results in monotonic improvement with
time. Notice also in Fig. 3(a) that steam-oxidized devices
have substantially lower mobility for all hydrogenation,
improves "over-hydrogenated'' dry-oxidized devices,
while steam-oxidized devicesare degraded by the an-
nealing. The results presented in Fig. 3(a) demonstrate
that hydrogenation of dry-oxidized polysilicon devices
occurs rapidly. Steam-oxidized polysilicon devices have
low mobility and annealing at 400°C causes the mobility
to revert toward unhydrogenated performance.
In order to achieve the highest frequency operation, a
hydrogenation time is selected that yields the maximum
channel mobility. Fig. 3(a) indicates that control of mo-
bility over large areas for the dry-oxide case should be
achievable at the maximum mobility point since channel
mobility is a weak function of exposure time. However,
Fig. 3(b) illustrates that threshold voltage changes more
significantly with exposure time where devices oxidized
in dry 0, have maximum channel mobility. The results in
Fig. 3(b) suggest that careful attention needs to be paid
tothe hydrogenation stepfor applications where close
HAWKINS: POLYCRYSTALLINE-SILICON DEVICE TECHNOLOGY
70r
H y d r o g e n a t iT
o inm
l me i n )
(a)
0- 0 -
Dry O2 m o b i l i t y mox
-8
I
-10
0 15 30 45
Hydroqsnailon
Time
(b)
Fig. 3 . Effect of hydrogen-plasma exposure on (a) mobility and (b) thresh-
old voltage for n-channel devices oxidized at a variety of temperatures
and ambients.
control of threshold voltage is important, such as forlogic
gates.
Previous work demonstrated that high-temperature in-
ert annealing of oxidized devices had little impact on mo-
bility or threshold voltage [6]. For example, inert anneal-
ingdid not improveperformance when oxidation was
conducted at 1000°C and inert annealing took place at
1100°C.Deviceperformancebehavior differences be-
tween inert and oxidizing ambients are a key to undar-
standing the role high-temperature processes play in chan-
nel-mobility improvement.
A qualitativeunderstanding can beextracted by ap-
pealing to the abundance of data available for the single-
crystal silicon case. A major difference in the behavior of
point defects in single-crystal silicon occurs with inert an-
nealing or oxidation at high temperature. Oxidizing am-
bients generateexcess silicon self-interstitials[9].Self-
interstitials originate at the silicon-silicon dioxide inter-
face and diffuse rapidly into the bulk of the wafer. The
interstitials have a diffusion length that is dependent on
crystal perfection and is about 100 p m under the best con-
ditions [ 101. Crystal-quality-dependent excess self-inter-
stitial diffusion length is a consequence of recombination
by multiple mechanisms.The mechanisms include va- threshold, voltages by using ion implantation into the
cancy-interstitial annihilation, addition to stacking faults, channel. For the case where the boron channel implanta-
and surface recombination at nonoxidizing Si-Si02 inter- tion was performed prior to channel oxidation, p-channel
faces. The longest diffusion length occurs when vacancy- threshold voltage could not be controlled. However, the
interstitial annihilation is the predominant mechanism.
479
It is well known that excess silicon self-interstitials are
also generated from high-concentration phosphorus dif-
fusion [ l l ] . When polysilicon is heavily diffused with
phosphorus, grain growth at high temperature occurs rap-
idly in comparison with undoped or lightly doped poly-
silicon [12]. It hasbeen proposed that excess silicon self-
interstitials are generated during high-concentration dif-
fusion of phosphorus through polysilicon [ 121, in analogy
with single-crystalsilicon.Silicon self-interstitials are
known to have avery short diffusion length in polysilicon,
presumably because they are captured at grain boundaries
and defects. The above-mentioned facts suggest that the
rapid rate of grain growth in heavily phosphorus-doped
polysilicon is caused by the large excess of phosphorus-
diffusion-generated silicon self-interstitials.The self-in-
terstitials impart a high mobility to the silicon lattice,
which catalyzes the conversion of energetically unfavor-
able crystallites into grains with low-surface-energy ori-
entations. It is believed that self-interstitials generated
during oxidation play the same role as those generated as
a consequence of phosphorus diffusion. The use of oxi-
dationtoaccelerategrain growth is technically useful
since undoped films are produced.
The wet-oxidation case would appear to contradict the
60 40O0C/3Omin ' self-interstitial model because the generation of self-in-
(min) terstitials increases with the oxide growth rate [9], while
low mobility is seen for wet-oxidized devices in Fig. 3.
The hydrogen that is liberated during oxide growth in
steam might be expected to interact with grain boundaries
to impede bonding of self-interstitials onto unsatisfied
bonds in the boundary, either by tying up the bonds, or
by someother mechanism. Retardation of polysilicon
grain growth under wet-oxidation conditions has been
previously observed 11 31.
The behavior of device performancewith varied hydro-
genation time provides data on how atomic hydrogen is
shielded from thechannellayer by various gatestruc-
tures. The optimum hydrogenation time for dry-oxidized
p-channel devices increases by a factor of three, if the
boron implant used to degenerately dope the source and
drain is used as the sole dopant of the polysilicon gate
instead of phosphorus diffusion. The difference in hydro-
genation time can be seenby comparison of Fig. 3(a) with
[6, Fig. 21. Therefore, highly degenerate n+ polysilicon
gates allow hydrogen passivation of the channel layer to
occur rapidly, as was previously observed for aluminum-
gate material [6]. However, theuse of p+ polysilicon gates
reduces penetration of hydrogen. Consequently, 3 0 4 1 U
phosphorus-doped polysilicon 600 nm thick was used as
a gate material for subsequent work.
V. THRESHOLD VOLTAGES
A final set of experiments demonstrated control of
threshold voltage of n-channel devices could be con-
480
-20 -10 0 IO
G a tVeo l t a g e
Fig. 4. Variation in threshold voltage caused by channel implantation of
boron and phosphorus following gate oxidation. Depletion-and enhance-
ment-mode behavior was obtainable for both n- and p-channel devices.
trolled by phosphorus doping above 3 X When
channel implantation occurs before gateoxidation, the
high diffusion rate exhibited by dopants in polysilicon [14)
and preferential segregation of boron into oxide, or phos-
phorus into silicon gives rise to acomplex time-dependent
segregation of dopant at the moving silicon-silicon diox-
ide interface, which cannot be numerically simulated re-
liably.
An alternative process is to carry out channel doping,
after oxidation. The final lot of devices was fabricate<[
with dry oxidation at 1050°C to 105 nm followed by iort
implantation of phosphorus or boron through the gate ox.
ide. Theprojected range of ions was selected to match thc
distance to the center of the channel. Degenerately phos-
phoms-doped polysilicon gates were used and hydrogen-
ation time was 30 min, based on results presented in Fig.
3(a). Fig. 4 shows a plot of IsD(sat)1'2 versus V, for both
p-channel and n-channel devices. Comparison of Fig. : 1
with Fig. 4 demonstrates that pre-oxidation implantatio.1
of boron reduces p-channel mobility from 49 cm2/V s
to 34 crn2/V * s, while the observed threshold voltage c f
undoped channels is comparable to threshold voltage c f
channels doped with boron prior to oxidation. These ob-
servations support the contention that essentially all the
boron placed in the channel prior to oxidation segregate 5
into the oxide during growth. The reduced p-channel mo-
bility of pre-implanted devices indicates that boron inte --
feres with grain growth or affects some other film properly
that lowers mobility. In the case of phosphorus-doped 11-
channel devices, no change in threshold voltage is 011-
served until channel doping exceeds 3 X 1012cm-2. The
preferential segregation of phosphorus to grain bound,r-
ries is well-known [15], and is a possible cause for the
insensitivity of threshold to implant dose at low conce-t-
tration. Fig. 4 demonstrates that it is possible to achieve
depletion- and enhancement-mode behavior from both p-
channel and n-channel devices. The high resistivity of un-
doped and lightly doped polysilicon is a consequence of
trapping of carriers by deep levels. Implantation of dop-
ants into the film allows partial filling to complete filling
of deep levels, depending on the dose, Therefore, the gcte
1EEE 'J'RANSACTIONSON ELECTRON DEVICES, VOL. ED-33, NO. 4, APRIL 1986
20 -12
IO 0 -10
G a tV
eoltage
Fig. 5. Subthreshold and leakage behsvior ofn-channeldevices from
Fig. 4.
r 7pd p-Channel
I-
Gale Voltage
Fig. 6. Subthresholdandleakagebehaviorofp-channeldevicesfrom
Fig. 4.
voItage at which the carrierconcentration exceeds the trap
- density (and the channel becomes conductive due to mo-
bile carriers) and can be varied by doping the device chan-
nel. These results indicate that it should be possible to
fabricate either CMOS or NMOS logic circuitry using the
fabrication sequence devised here.
The leakage currents that are achieved from thedevices
described above are shown in Fig. 5 for n-channel and
Fig. 6 for p-channel devices. The source-drain voltage
was 10 V. The currents observed under reverse gate bias
are relatively free of anomalous leakage [ 161. The hys-
teresis observed in the subthreshold region of the p-chan-
ne1 devices (Fig. 6) is absent for n-channel devices (Fig.
5 ) . The p-channel hysteresis is most likely associated with
a fairly high density of defect states below rnidgap in
polysilicon [17]. Figs. 4, 5 , and 6 demonstrate that the
threshold voltage of n- and p-channel devices can be ad-
justed without increasing device leakage.
VI. CONCLUSION
Under optimal process conditions, polycrystalline-sili-
con thin-film deviceshavehole mobilities of 50 cm2/
VICE
POLYCRYSTALLINE-SILICON
HAWKINS: 48 1

V s or electron mobilities of 70 cm2/V . s. The thresh-
old voltage can be tailored to achieve either depletion- or
enhancement-mode operation of both n- and p-channel
devices. Substantial threshold voltage adjustment can be
achieved without an increase in device leakage. Heavy
phosphorus doping of the gate-level polysilicon decreases
the time necessary for plasma hydrogenation from 90 to
30 min. The time for hydrogenation of the aluminum gate
(1 pm) and the degenerate phosphorus-doped polysilicon
gate (600 nm) devices is approximately equal, while [IO] D. A. Antoniadis and I. Moskowitz, “Diffusion of substitutional im-
highly boron-doped polysilicon impedes the channel hy-
drogenation time by a factor of three. Therefore, a self-
aligned gate technology can be applied to large-area logic
without any penalty in fabricationtime or complexity
while retaining all the attendantbenefits that accrue to the
self-aligned gate process. Thesebenefits include gettering
of mobile ions in the gate insulator and achievement of [13] D. Pawlik, H. Oppolzer, and T. Hillmer, “Characterization of ther-
accurate gate dimensions without concern for stray gate-
source capacitance.
ACKNOWLEDGMENT
The author is indebted to P. J . Hartman and C . Burke
for help in device fabrication and to S. Pond and other
management of Xerox Webster Research Center for sup-
port in carrying out this investigation. Critical comments
from F. Jansen, T. Orlowski, and N. Goodman were also
appreciated.
[6] W. G . Hawkins, “High performance polycrystalline silicon thin film
devices,” in Muter. Res. SOC. Symp. Proc., vol. 49, pp. 443-448,
1985.
[7] G . Harbeke, L. Krausbauer, E. F. Steigmeier, A. E. Widmer, H. F.
Kappert, and G. Neugelbauer,“High quality polysilicon by amor-
hous low pressure chemical vapor deposition,” Appl. Phys. L e t f . ,vol.
42, pp. 249-251, 1983.
[8] M. Kimura and K. Egami, “Influence of as-deposited film structure
on ( 100) texture in laser-recrystallized silicon on fused quartz,” Appl.
Phys. Lett., vol. 44, pp. 420-422, 1984.
191 D. A. Antoniadis, “Oxidation-induced point defects in silicon,” J .
Electrochem. SOC., vol. 129, pp. 1093-1097, 1982.
purities in silicon atshort oxidation times: An insight into point defect
kinetics,” J . Appl. Phys., vol. 53, pp. 6788-6796, 1982.
[ I l l P. Fahey, R. W. Dutton, and S . M. Hu, “Supersaturation of self-
interstitials and undersaturation of vacancies during phosphorus dif-
fusion in silicon,” Appl. Phys. Lett,, vol. 44, pp. 777-779, 1984.
[12] Y. Wada and S . Nishimatsu, “Grain growth mechanism of heavily
phosphorus-implanted polycrystalline silicon,” J . Electrochem. Soc.,
VOI. 125, pp. 1499-1504, 1978.
mal oxides grown on TaSiJpolysilicon films,” J . VUC. SOC. Technol.,
VOI.B3, pp. 492-499, 1985.
[14] D. J . Coe, “The lateral diffusion of boron in polycrystalline silicon
and its influence on the fabrication of submicron MOSTS,” Solid-
State Electron., vol. 20, pp. 985-992, 1977.
[15] J. M. Andrews, “Electrical conduction in implanted polycrystalline
silicon,” J . Electron. Mat., vol. 8, pp. 227-246, 1979.
[16] S . Onga, Y.Mizutani, K. Taniguchi, M. Kashiwagi, K. Shibata, and
S. Kohyama, “Characterization of polycrystalline silicon MOS tran-
sistors and its film properties. I.,” Japan. J . Appl. Phys., vol. 21,
pp. 1472-1478, 1982.
[I71 W. B. Jackson, N. M. Johnson, and D. K. Biegelsen, “Density of
gap states of silicon grain boundaries determined by optical absorp-
tion,” Appl. Phys. Lett., vol. 43, pp. 195-197, 1983.

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[I] H. C.Tuan,“Amorphoussilicon thin film and its applications to

large-areaelectronics,” in Muter. Res. SOC.Symp. Proc., vol.33,
pp. 247-258, 1984.
[2] M. J . Powell,“Material properties controlling the performance of
amorphous silicon thin film transistors,” in Muter. Res. SOC. Symp.
Proc., vol. 33, pp. 259-273, 1984.
[3] F. Okumura and S. Kaneko, “Amorphous Si: H linear sensor oper-
ated by a-Si :H TFT array,’’ in Muter. Res. Soc. Symp. Proc., vol.
33, pp. 275-280, 1984.
[4] J. Slowik, private communication.
[ 5 ] S. D. S. Malhi, P. K. Chatterjee, R. F. Pinizzotto, H. W. Lam, C.
E. C. Chen, H. Shichijo, R. R.Shah, and D. W. Bellavance,“p-
Channel MOSFET’s in LPCVD polysilicon,” IEEE Electron Device
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William G . Hawkins was born in Albany, NY,
in 1954. He received the B.S. degree in chemistry
from Union College, Schenectady, NY, in 1976,
and the Ph.D. degree from Cornell University,
Ithaca, NY, in 1980.
He has been a member of the research staff at
the Xerox Webster Research Center since 1980.
He has contributed to the understanding of thin-
film crystal growth of silicon forSO1 applications
and to the development of high-performance thin-
film silicon MOS devices. Other interests include
MOS applications in specialty electronics and orientation-dependent etch-
ing of semiconductor materials.