Computer Architecture

Chapter Five Register Transfer and Microoperations

CHAPTER FIVE

REGISTER TRANSFER

AND MICROOPERATIONS

5.1. Register Transfer Language

The internal hardware organization of a digital computer is best defined
by specifying:

1. The set of registers it contains and their function.

2. The sequence of microoperation performed on the binary information
stored in the register.
3. The control that initiates the sequence of microoperation.

It is more convenient to adopt a suitable symbolic language to describe

the sequence of transfers between registers and the various arithmetic
and logic microoperation associated with the transfers, rather than using
explaining every operation in words.

Register Transfer Language can be defined as, the symbolic notation

used to describe the microoperation transfers among registers. The term
Register Transfer implies the availability of hardware logic circuits that
can perform a stated microoperation and transfer the result of the
operation to the same or another register. The word language is
borrowed from programmers, who apply this term to programming
languages.

Programming language is a procedure for writing symbols to specify a

given computational process. In the same manner, a natural language
such as Arabic is a system for writing symbols and combining them into
words and sentences for the purpose of communication between people.
A Register Transfer Language is a system for expressing the
microoperation sequences among the registers of a digital module in
symbolic form. It can be used to facilitate the design process of digital
systems.

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5.2. Register Transfer

Normally computer registers are designated by capital letters, sometimes
followed by numerals to denote the register function. For example, the
Address Memory Register is designated by (MAR), in which it is function
is to hold an address for the memory unit. Other examples are Program
Counter (PC), Instruction Register (IR), and Processor Register (R1).

The n-bit of the register are numbered in sequence from 0 in the rightmost
position and increasing the numbers toward the left. Figure 5.1 shows
different forms of register representation.

1. Figure 5.1(a) shows the common way to represent a register (a

rectangular box with the name of the register inside).

2. Figure 5.1(b) shows how the individual register bits are

distinguished.

3. Normally the numbering of bits in a 16-bit register is marked on top

of the box as shown in figure 5.1(c).

4. For a partitioned 16-bit register into two parts as shown in figure

5.1(d), bits 0 to 7 are assigned the symbol L (low byte), while bits 8
to15 are assigned the symbol R (high byte), and the name of the
register is PC (Program Counter).here the symbol PC(0-7)or PC(L)
refer to the low-order byte and PC(8-15) or PC(H) to the high-order
byte.

Figure 5.1

Some basic symbols for register transfer are shown in table 5.1.

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Table 5.1

Symbol Description Examples

Letters & Numerals Denotes a Register MAR, R2
Denotes a part
Parentheses ( ) R2(8-15), R2(L)
of a Register
Denotes Transfer
Arrow R2 ← R1
of Information
Separates Two
Comma , R2 ← R1, R1 ← R2
Microoperations
Denotes Transfer of
Information under a
Colon : P: R2 ← R1
Predetermined
Control Condition

Normally registers are denoted by capital letters with numerals may

follow them as shown in the first row of the table.

Parentheses are used to denote a part of register either by specifying

the range of bits or by giving a symbol name to a portion of a register as
shown in the second row of the table.

Arrows denote a transfer of information and the transfer direction as

shown in the third, fourth, and fifth rows of the table.

A Comma is used to separate two or more operations that are executed

at the same time as shown in the fourth row of the table.

A Colon is used to terminate the control condition as shown in the fifth

row of the table.

The statement R2 ← R1 denotes a transfer of the content of register R1

into R2, in which, the content of the source register R1 remains
unchanged.

The statement R2 ← R1, R1 ← R2 denotes an operation that exchanges

the contents of two registers R1 and R2 during one common clock pulse.
The statement P: R2 ← R1 denotes a transfer of the content of register
R1 into R2 provided that the control function P = 1 in which, the content
of the source register R1 remains unchanged.

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Figure 5.2 shows the block diagram that explains the transfer of
information from register R1 to R2 providing that the control function P
= 1.
The n outputs of register R1 are connected to the n inputs of register R2.
Register R2 has a load input that is activated by the control variable P.
Here; it is assumed that the control variable is synchronized with the
same clock as the one applied to the register. The timing diagram shows
P which activated in the control section by the rising edge of a clock pulse
at time t. The next positive transition of the clock at time t+1 finds the load
input active and the data inputs of R2 are then loaded into the register in
parallel. P may go back to 0 at time t+1; otherwise, the transfer will occur
with every clock pulse transition while P remains active.

Figure 5.2

5.3. Bus and Memory Transfers

A Bus is a structure which consists of a set of common lines one for each
bit , through which binary information is transferred one at a time
(between, two registers, Memory and a Register, Register and a
Memory…etc). A more efficient scheme for transferring information
between registers in a multiple-register configuration is a Common Bus
System.
A Common Bus System can be constructed using either multiplexers or
a Three-State Bus Buffers.

1. Constructing A Common Bus System using multiplexers

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A Common Bus System can be constructed using multiplexers, in

which, these multiplexers select the source register whose information
are placed on the bus. Figure 5.3 shows a bus system for four
registers. The bus consists of four 4*1 multiplexers, each having four
data inputs, 0 to 3, and two selection inputs, S1 & S0.
Bits in the same significant position in each register are connected to
the data inputs of one multiplexer to form one line of the bus.
Each of the four registers is assumed to have 4 bits, numbered 0
through 3. In order not to complicate the diagram, labels are used to
show the connections from the outputs of the registers to the inputs of
the multiplexers and not line connection. For example, output 3 of
register B is connected to input 1 of MUX3 because this input is
labeled B3, and so on.
The diagram shows that the bits in the same significant position in
each register are connected to the data inputs of one multiplexer to
form one line of the bus.
The selection lines S1 & S0 choose the four bits of one register and
transfer them into the four-line connection bus. Table 5.2 shows the
register that is selected by the bus for each of the four possible binary
values of the selection lines.

Figure 5.3
In general, a bus system will multiplex k registers of n bits each to
produce an n-line common bus.
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To transfer information from a bus to one of many destination register,

the inputs of all destination registers are connected to the bus lines
and activating the load control of the particular destination register
required.
The symbolic statement for a bus transfer may mention the bus or its
presence may be implied in the statement.
For example, to transfer the content of register A to Register B, the
symbolic statement can be written a follows:

a. The symbolic statement using a bus symbol.

BUS ← A, B ← BUS

b. The symbolic statement without using a bus symbol.

B←A

2. Constructing a Common Bus System using Three-State Bus Buffers

A Three-State gate is a digital circuit that exhibits three states. Two
of the three states are the normal logic states 0 & 1, while the third
state is a high-impedance state. The high-impedance state behaves
like an open circuit (i.e. the output is disconnected and does not have
logic significance). The most gates commonly used in the design of a
bus system are the buffer gate. Figure 5.4 shows the graphic symbol
of a three-state buffer gate, and table 5.3 shows its truth table.

Figure 5.4

Table 5.3
Control Input Normal Input Gate Output
C A X
0 0 High Impedance
0 1 High Impedance
1 0 0
1 1 1
Figure 5.5 shows a single bus line using three-state buffers. A single
bus line is formed by connecting together the outputs of the four

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buffers. The control inputs to the buffers determine which of the four
normal inputs will communicate with the bus line.
To insure that no more than one control input is active at any given
time, a 2*4 decoder is used as shown in the diagram. When the enable
input of the decoder is 0, all of its four outputs are 0, and the bus line
is in a high-impedance state because all four buffers are disabled.
When the enable input is active, one of the three-state buffers will be
active, depending on the binary value in the select inputs of the
decoder. Circuit shown in figure 5.5 can replace one multiplexer in
figure 5.3.

Figure 5.5

For example, to construct a common bus for 4 registers of 4 bits each

using three-state buffers, we need 4 circuits with 4 buffers in each as
shown in figure above. Each group of 4 buffers receives one
significant bit from the 4 registers. Each common output produces one
of the lines for the common bus for a total of 4 lines. Only one decoder
is needed to select between the four registers.

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Memory Transfer
There are two main operations concerning memory transfers, these are:

1. Read Operation which means transfer of information from a

memory word to the outside environment.

In symbolic form, the Read Operation (transfer of information into

Data Register (DR) from the memory word M selected by the
address in the Address Register (AR)) can be stated as follows:

DR ← M [AR]

Where: AR stands for Address Register, from which the memory

receives the address.
DR stands for Data Register that receives data from the
specified memory word.
M stands for the memory word.

2. Write Operation which means transfer of information from the

outside environment into a specified memory word.

In symbolic form, the Write Operation (transfer of information from

Data Register (DR) into the memory word M selected by the
address in the Address Register (AR)) can be stated as follows:

M [AR] ← DR

5.4. Arithmetic Microoperations

Microoperation can be defined as an elementary operation performed
with the data stored in registers.

In Digital Computer Microoperations are classified into four

categories:

1. Register transfer microoperations transfers binary information from

one register to another.
2. Arithmetic microoperations perform arithmetic operations on
numeric data stored in registers.
3. Logic microoperations perform bit manipulation operations on non
numeric data stored in registers.
4. Shift microoperations perform shift operations on data stored in
registers.
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1. Register transfer microoperations

This type of microoperation does not change the information content
when the binary information moves from the source register to the
destination register while, the other three types of microoperations
change the information content during the transfer. The Register
transfer microoperations were introduced in section 5.3.

2. Arithmetic Microoperations
The basic Arithmetic Microoperations are:
a. Addition Microoperation.
b. Subtraction Microoperation.
c. Increment Microoperation.
d. Decrement Microoperation.
e. Shift Microoperation.

Table 5.4 shows the basic arithmetic microoperations except the

shift microoperation, which will be explained later in conjunction
with the shift microoperations.

Table 5.4
Symbolic
description
Designation
R3  R1 + R2 Contents of R1 plus R2 transferred to R3
R3  R1 − R2 Contents of R1 minus R2 transferred to R3
Complement the contents of R2
R2  R2 (1's complement)
R2  R2 + 1 2's complement the contents of R2 (negate)
R1 plus the 2's complement of R2 transferred
R3  R1 + R2 + 1 to R3 (subtraction)
R1  R1 + 1 Increment the contents of R1 by 1
R1  R1 − 1 Decrement the contents of R1 by 1

The arithmetic Multiply and Divide operations are not included in the
table above since in most computers, the multiplication operation is
implemented with a sequence of add and shift microoperations,
while the division operation is implemented with a sequence of
subtract and shift microoperations.

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Hardware implementation of the Arithmetic Microoperation

a. Arithmetic microoperation R3  R1 + R2
To implement this Microoperation we need three registers and
the digital component that performs the addition operation.

b. Arithmetic microoperation R3  R1 − R2
Normally this Arithmetic Microoperation is implemented
through complementation and addition instead of using the
minus operator.

c. Arithmetic microoperations R1  R1 + 1 and R1  R1 − 1

Increment and decrement microoperations are implemented
with a combinational circuit or with a binary up-down counter.

Binary Adder
Figure 5.6 shows a 4-bit binary adder. This adder is constructed with
4 full-adders connected in cascade, with the output carry from one full-
adder connected to the input carry of the next full-adder. The
corresponding augend bits of A and the addend bits of B are the two
inputs to the successive full-adders. The input carry to the binary
adder is C0 and the output carry is C4. The S outputs of the full-adders
generate the required sum bits.

Figure 5.6

For example, to implement the Arithmetic microoperation

R3  R1 + R2 using the above 4-bits binary adder, we will have the 4
data bits for the A inputs come from one register (such as R1), and
the 4 data bits for the B inputs come from another register (such as
R2). The sum can be transferred to a third register (such as R3).

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Binary Adder-Subtractor
Figure 5.7 shows a 4-bit Adder-Subtractor logical circuit. The circuit
combines both addition and subtraction operations. The circuit differs
from the 4-bit binary adder shown in figure 5.6 by including an
exclusive-OR gate which receives input M and one of the inputs (B)
with each full-adder. The mode input M controls the operation of the
circuit as follows:

1. For M = 0
The circuit is an adder, since we have B  0 = B . The full-adders
receive the value of B, the input carry C0 is 0, and the circuit
performs the addition of A to B (i.e. A+B).

2. For M = 1
The circuit becomes a Subtractor, since we have B 1 = B . The full-
adders receive the value of B , the input carry C0 is 1. The B inputs
are all complemented and a 1 is added through the input carry. The
circuit performs the addition of A to 2's complement of B.

Note.
1. For signed numbers, the result is A – B provided that there
is no overflow.
2. For unsigned numbers, the result is A – B for A ≥ B, and the
2's complement of ( B – A ) for A < B.

Figure 5.7

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Binary Incremental
Figure 5.8 shows a 4-bit Combinational Circuit Incrementer. Simply
this logic circuit is implemented by means of half-adders connected in
cascade. One of the inputs to the least significant half-adder is
connected to logic 1 and the other input connected to the least
significant bit of the number to be incremented. The circuit receives
the four bits A0 to A3, adds 1 to it, and generates the incremented
output in S0 to S3. The output carry C4 will be 1 only after incrementing
binary number 1111. This also causes output S0 to S3 to go to 0 (i.e.
0000).
The circuit shown in figure 5.8 can be extended to an n-bit binary
Incrementer by extending the diagram to include n half-adders. Keep
in mind that the least significant bit must have one input connected to
logic 1.

Figure 5.8
Arithmetic Circuit
Figure 5.9 shows a 4-bit arithmetic circuit. The circuit has four full-
adders and four multiplexers for choosing different operations. There
are two 4-bit inputs A and B and a 4-bit output D. the 4 inputs from A
connected directly to the X inputs of the binary adder, while the other
4 inputs from B and their complements are connected to two of the
data inputs of the multiplexers. The remaining two inputs of the
multiplexers are connected to logic 0 and logic 1.
The two selection inputs, S1 & S0 controls the operation of the four
multiplexers. The input carry Cin is connected to the input of the full-
adder FA0, while the other carries are connected from one stage to
the next.
The output of the binary adder s is calculated from the following
arithmetic sum:
D = A + Y + Cin … (5.1)

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Depending on the two selection inputs S1 & S0 and by controlling the

value of Y and Cin, it is possible to generate the arithmetic
microoperations shown in table 5.5.
Table 5.5

Select Output
Input
S1 S0 D=A+Y+ Type of microoperation
Y
Cin Cin
0 0 0 B D = A+ B Add without Carry
0 0 1 B D = A + B +1 Add with Carry
Subtract with Borrow
0 1 0 B D = A+ B (i.e. D = A – B – 1)
Subtraction of B from A
0 1 1 B D = A + B +1 (i.e. A plus 2's Complement of B)
Transfer from input A to output
1 0 0 0 D=A D
1 0 1 0 D = A +1 Increment A by 1
1 1 0 1 D = A −1 Decrement A by 1
Transfer from input A to output
1 1 1 1 D=A D

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Figure 5.9
5.5. Logic Microoperations
Logic microoperations specify binary operations for string of bits stored
in registers. These operations consider each bit of the register separately
and treat them as binary variables.

Examples of these microoperations are the following:

(1) P : R1  R1  R 2

This microoperation performs the exclusive-OR between the individual

bits of registers R1 & R2 provided that the control variable P = 1, and
store the result in register R1. As a numerical example, let the contents
of R1 = 1001 and R2 = 1101, then

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1001 Content of R1
1101 Content of R2
0100 Content of R1 after P = 1

(2) P + Q : R1  R 2 + R3, R 4  R5  R6

This microoperation performs the OR function between the individual bits

of registers R5 & R6, store the result in R4, and adding the contents of
registers R2 and R3 , store the result in R1 provided that the control
variables P OR Q = 1.
In the above statement the + between P & Q is an OR operation, while
the + between R2 and R3 specifies an add microoperation. The symbol
 between registers R5 & R6 stands for the OR microoperation.

Hardware Implementation of Logic Microoperations

Generally, there are 16 logic microoperations, but most computers use
only four, which are AND, OR, XOR, and Complement from which all
others can be derived.
Figure 5.10 shows one stage of a circuit that generates the four basic
logic microoperations. The circuit consists of four logical gates AND, OR,
XOR, and NOT gates and one Multiplexer. The outputs of the four
gates are applied to the data inputs of the multiplexer. The data inputs of
the multiplexer are chosen according to the two selection inputs S1 & S0
as shown in table 5.6.
Note that the diagram shows one typical stage with subscript i. For a
logic circuit with n bits, the diagram must be repeated n times for i = 0, 1,
2,…, n-1. The selection inputs S1 & S0 are applied to all stages.

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5.6. Shift Microoperations

Shift microoperations are used for serial transfer of data. Also these
microoperations are used in conjunction with other operations such as
arithmetic, logic, and other data processing operations.
The contents of a register can be shifted to the right or to the left. At the
same time that the bits are shifted, the first flip-flop receives the binary
information from the serial input.
During a shift left operation, the serial input transfers a bit into the
rightmost position, while during a shift right operation, the serial input
transfers a bit into the leftmost position. The information transferred
through the serial input determines the type of shift.

There are three types of shifts: -

1. Logical Shift.
A logical shift transfers 0 through the serial input. The symbol shl
stands for logical shift-left, while shr stands for logical shift-right.

Examples
(1) R ← shl R
This microoperation, shift to the left one bit the contents of
register R. The bit transferred to the end position through the
serial input is assumed to be 0.

(2) R ← shr R
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This microoperation, shift to the right one bit the contents of

register R. The bit transferred to the end position through the
serial input is assumed to be 0.

2. Circular Shift.
The circular shift circulates the bits of the register around the two
ends without loss of information. This is accomplished by connecting
the serial output of the shift register to its serial input. The symbol cil
stands for circular shift-left, while cir stands for circular shift-right.

Examples
(1) R ← cil R
This microoperation circulates to the left one bit the contents
of register R. No bit transferred to any end positions of the
specified register.

(2) R ← cir R
This microoperation circulates to the right one bit the contents
of register R. No bit transferred to any end positions of the
specified register.

3. Arithmetic Shift.
Arithmetic Shift Microoperations shift a signed binary number to the
left (multiplies the signed binary number by 2) or to the right (divides
the signed binary number by 2).
Arithmetic shifts must leave the sign bit unchanged because the sign
of the number remains the same when the number is multiplied or
divide by 2.
For signed binary numbers, the left bit in a register holds the sign
bit (0 for positive and 1 for negative), and the remaining bits hold the
number magnitude. Negative numbers are in 2's complement
form.
Figure 5.11 shows a typical register of n bits, where bit R n-1 in the
leftmost position holds the sign bit, and Rn-2 is the most significant bit
of the number with R0 the least significant bit.

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Figure 5.11

There are two types of Arithmetic shift microoperations: -

1. Arithmetic Shift-Right Microoperation.

The Arithmetic Shift-Right Microoperation leaves the sign bit
unchanged with shifting the number (including the sign bit) to the
right. Here, Rn-1 remains the same; Rn-2 receives the bit from Rn-1,
and so on for the other bits in the register. The bit in R 0 is lost.

2. Arithmetic Shift-Left Microoperation.

The Arithmetic Shift-Left Microoperation inserts a 0 into R0, and
shifts all other bits to the left. Here, the initial bit of Rn-1 is lost and
replaced by the bit from Rn-2. If the bit in Rn-1 changes in value after
the shift, a sign reversal occurs. This happens if the multiplication
by two causes an overflow.
Hardware Implementation of Shift Microoperations
Figure 5.12 shows the combinational circuit that can performs 4-bit shift
operations. The 4-bit shifter has four data inputs, A0, A1, A2, and A3, with
four data outputs, H0, H1, H2, and H3. There are two serial inputs, one for
shift left (IL) and the other for shift right (IR). When the selection input S =
0, the input data are shifted right (down in the diagram), while when S =
1, the input data are shifted left (up in the diagram).
Table 5.7 is a function table that shows how the data shifts after the shift
operation.

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Figure 5.12

Table 5.7

Select Input Output

S H0 H1 H2 H3
0 IR A0 A1 A2
1 A1 A2 A3 IL

5.7 Arithmetic Logic Shift Unit

In previous sections, we studied individually the circuits that perform the
arithmetic, logic, and Shift microoperations. In computer system, this is not
the case, in which a number of storage registers connected to a common
operational unit called an Arithmetic Logic Unit (ALU) employs these
microoperations.
To perform a microoperation, the contents of specified registers are placed
in the inputs of the common ALU. The ALU performs an operation and the
result of the operation is then transferred to a destination register.

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The shift microoperations are often performed in a separate unit, but

sometimes the shift unit is made part of the overall ALU.

Figure 5.13 shows a one stage of an arithmetic logic shift unit.

Where: -

i: is a subscript designates a typical stage.

Ai and Bi : The two Inputs applied to both the arithmetic and logic units.
S0 to S1: are the selection inputs, which select a particular
microoperation.
S2 to S3: are the selection inputs, which select between Ei, Hi, Ai-1 (the
shift right operation), and Ai+1 (the shift left operation).
Ci: is the input carry of the stage i.
Ci+1: is the output carry of the stage i.
Ei: is the output of the arithmetic circuit.
Hi: is the output of the logic circuit.
Fi: is the output of the stage i

For an n-bit ALU, the circuit of figure 5.13 must be repeated n times. The
output carry Ci+1 of a given arithmetic stage must be connected to the
input carry Ci of the next stage in sequence.

The input carry to the first stage is the input carry C in, which provides a
selection variable for the arithmetic operations.
The circuit shown in the figure provides eight arithmetic operation, four
logic operations, and two shift operations. The operations are selected
according to the variables S3, S2, S1, S0, and Cin. The input carry Cin used
for selecting arithmetic operations only.

Table 5.8 lists the fourteen operations of the ALU. When S3S2 = 00, the
first eight arithmetic operations are selected. For S3S2 = 01, the next four
logic operations are selected. The input carry has no effect during the
logic operations and is marked with don't-care x's. The last two
operations are shift operations and are selected with S3S2 = 10 and 11.
The other three selection inputs have no effect on the shift.

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Figure 5.13

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Table 5.8

Operation Select
Operation Function
S3 S2 S1 S0 Cin
0 0 0 0 0 F =A Transfer A
0 0 0 0 1 F = A +1 Increment A
0 0 0 1 0 F = A+ B Addition
0 0 0 1 1 F = A + B +1 Add with carry
0 0 1 0 0 F = A+ B Subtract with borrow
0 0 1 0 1 F = A + B +1 Subtraction
0 0 1 1 0 F = A −1 Decrement A
0 0 1 1 1 F =A Transfer A
0 1 0 0 x F = A B AND
0 1 0 1 x F = A B OR
0 1 1 0 x F = A B XOR
0 1 1 1 x F=A Complement A
1 0 x x x F = shr A Shift right A into F
1 1 x x x F = shl A Shift left A into F

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