LODIG1 – Register, Divider & Counter

Latches & FlipFlops

Latches are basically similar to flip-flops because they are both a temporary storage device that has
two stable states (bistable). The main difference between latches and flip-flops is in the method used
for changing their sate

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LODIG1 – Register, Divider & Counter
Latches
The latch is a type of temporary storage device that has two stable states (bistable)

Basically, the return of the Output signal to an Input is the idea behind Latches (and Flip-Flops). But
only the return of the output allows to save an Information, it doesn’t allow to reset it.

Therefore, we need a further gate, an AND Gate, to interrupt the return. On that way we have two
different Inputs, o SET- and a RESET-Input

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LODIG1 – Register, Divider & Counter
By using Morgan’s theorems, we can replace the different types of gates through one, same type of
gate.

B A B' A' X B A X' X

0 0 1 1 1 0 0 0 1

0 1 1 0 0 0 1 1 0

1 0 0 1 0 1 0 1 0

1 1 0 0 0 1 1 1 0

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LODIG1 – Register, Divider & Counter
The S-R (Set-Reset) Latch
Logic Symbol

Truth Table
R S Q1
0 0 X No change (save)
0 1 1 Set
1 0 0 Reset
1 1 = Invalid Condition (undefined)

Timing diagram

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LODIG1 – Register, Divider & Counter
Application Example: The Latch as a Contact-Bounce Eliminator.
A good example of an application of an S-R latch is in the elimination of mechanical switch contact
“bounce”. When the pole of a switch strikes the contact upon switch closure, it physically vibrates or
bounces several times before finally making a solid contact.

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LODIG1 – Register, Divider & Counter
The S-R Latch with dominant Reset
Logic Symbol

By external wiring

Truth Table
R S Q1
0 0 X No change (save)
0 1 1 Set
1 0 0 Reset
1 1 0 Reset

Timing diagram

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LODIG1 – Register, Divider & Counter
The Gated S-R Latch
A gated latch requires an enable input EN. The latch will not change until EN is High.

Logic Symbol
Presentation without dependency notation with dependency notation

Truth Table
tn tn+1
R S Q1
0 0 Q1 (n) No change (save)
0 1 1 Set
1 0 0 Reset
1 1 = Invalid Condition (undefined)

Timing diagram

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LODIG1 – Register, Divider & Counter
Edge triggered FlipFlop’s
An edge triggered FlipFlop changes state either at the positive edge (rising edge) or at the negative
edge (falling edge) of the clock pulse and is sensitive to its inputs only at this transition of the clock.

Rising edge (positive edge)

Falling edge (negative edge)

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LODIG1 – Register, Divider & Counter
Positive Edge triggered S-R FlipFlop
Logic Symbol

Truth Table
tn tn+1
K J Q1
0 0 Q1 (n)
0 1 1
1 0 0
1 1 =

Timing diagram

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LODIG1 – Register, Divider & Counter
Positive Edge Triggered D-FlipFlop
The D-FlipFlop is useful when a single data bit is to be stored. The addition of an inverter to an S-R
FlipFlop creates a basic D-FlipFlop.

D-FlipFlop build with a S-R FlipFlop

Logic Symbol

Truth Table
tn tn+1
D Q1
0 0
1 1

Timing diagram

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LODIG1 – Register, Divider & Counter
Register
Serial In – Serial Out (SISO)

Application: FIFO-Memory (First In, First Out)

Multiplication, Division by 2
Serial In – Parallel Out (SIPO)

Application: Convert serial to parallel data format

Parallel In – Serial Out (PISO)

Application: Convert parallel to serial data format

Parallel In – Parallel Out (PIPO)

Application: Buffer Register / Cache

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LODIG1 – Register, Divider & Counter
Application Example: 4-Bit Parallel Access Shift Registers
The 7495 is a 4-bit shift register with serial and parallel synchronous operating modes. The serial shift
right and parallel load are activated by separate clock inputs which are selected by a mode control
input. The data is transferred from serial (SI= Serial Input) or parallel inputs (A,B,C,D) to the Q outputs
synchronous with the High-to-Low transition of the appropriate clock.

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LODIG1 – Register, Divider & Counter
Positive Edge Triggered J-K FlipFlop
Logic Symbol

Truth Table
tn tn+1
K J Q1
0 0 Q1 (n)
0 1 1
1 0 0
1 1 Q1 (n)

Timing diagram

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LODIG1 – Register, Divider & Counter
Negative Edge Triggered J-K FlipFlop
Logic Symbol

Truth Table
tn tn+1
K J Q1
0 0 Q1 (n)
0 1 1
1 0 0
1 1 Q1 (n)

Timing diagram

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LODIG1 – Register, Divider & Counter
Positive Edge Triggered T-FipFlop
T-FlipFlop build with a J-K FlipFlop

Logic Symbol

Truth Table
tn tn+1
T Q1
0 Q1 (n)
1 Q1 (n)

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LODIG1 – Register, Divider & Counter
Application Example: Frequency divider

𝐼 = 8𝑀𝐻𝑧

8𝑀𝐻𝑧
𝐼‘ = = 4𝑀𝐻𝑧
2
4𝑀𝐻𝑧
𝐼‘′ = = 2𝑀𝐻𝑧
2
2𝑀𝐻𝑧
𝑄= = 1𝑀𝐻𝑧
2

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LODIG1 – Register, Divider & Counter
Positive Edge triggered Master Slave FlipFlop
The Information is catched by rising edge

Logic Symbol

Timing diagram

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LODIG1 – Register, Divider & Counter
Negative Edge triggered Master Slave FlipFlop
The Information is catched by falling edge

Logic Symbol

Timing diagram

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LODIG1 – Register, Divider & Counter
Asynchronous Counter (Ripple Counter)
A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external
clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous
counters are also called ripple-counters because of the way the clock pulse ripples it way through the
flip-flops.

Asynchronous counters are slower than synchronous counters because of the delay in the
transmission of the pulses from flip-flop to flip-flop. With a synchronous circuit, all the bits in the
count change synchronously with the assertion of the clock.

Two stage asynchronous count-up dual counter

Counting stage 1 Counting stage 2

Timing diagram

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LODIG1 – Register, Divider & Counter
Assignment of the signal states
Valence Dual Decimal
time pulse
Q2 Q1 number Number
t0 0 0 0 00 0
t1 1 0 1 01 1
t2 2 1 0 10 2
t3 3 1 1 11 3
t4=t0 4 0 0 00 4

Two stage asynchronous count-down dual counter

Timing diagram

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LODIG1 – Register, Divider & Counter
Lab: Four stage asynchronous count-down dual counter

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LODIG1 – Register, Divider & Counter
Lab: Four stage asynchronous count-down dual counter

3TPIF LODIG1 (18-19) ScwM 22