Professional Documents
Culture Documents
Screenshot 2022-06-14 at 09.36.17
Screenshot 2022-06-14 at 09.36.17
Basically, the return of the Output signal to an Input is the idea behind Latches (and Flip-Flops). But
only the return of the output allows to save an Information, it doesn’t allow to reset it.
Therefore, we need a further gate, an AND Gate, to interrupt the return. On that way we have two
different Inputs, o SET- and a RESET-Input
0 0 1 1 1 0 0 0 1
0 1 1 0 0 0 1 1 0
1 0 0 1 0 1 0 1 0
1 1 0 0 0 1 1 1 0
Truth Table
R S Q1
0 0 X No change (save)
0 1 1 Set
1 0 0 Reset
1 1 = Invalid Condition (undefined)
Timing diagram
By external wiring
Truth Table
R S Q1
0 0 X No change (save)
0 1 1 Set
1 0 0 Reset
1 1 0 Reset
Timing diagram
Logic Symbol
Presentation without dependency notation with dependency notation
Truth Table
tn tn+1
R S Q1
0 0 Q1 (n) No change (save)
0 1 1 Set
1 0 0 Reset
1 1 = Invalid Condition (undefined)
Timing diagram
Truth Table
tn tn+1
K J Q1
0 0 Q1 (n)
0 1 1
1 0 0
1 1 =
Timing diagram
Logic Symbol
Truth Table
tn tn+1
D Q1
0 0
1 1
Timing diagram
Multiplication, Division by 2
Serial In – Parallel Out (SIPO)
Truth Table
tn tn+1
K J Q1
0 0 Q1 (n)
0 1 1
1 0 0
1 1 Q1 (n)
Timing diagram
Truth Table
tn tn+1
K J Q1
0 0 Q1 (n)
0 1 1
1 0 0
1 1 Q1 (n)
Timing diagram
Logic Symbol
Truth Table
tn tn+1
T Q1
0 Q1 (n)
1 Q1 (n)
𝐼 = 8𝑀𝐻𝑧
8𝑀𝐻𝑧
𝐼‘ = = 4𝑀𝐻𝑧
2
4𝑀𝐻𝑧
𝐼‘′ = = 2𝑀𝐻𝑧
2
2𝑀𝐻𝑧
𝑄= = 1𝑀𝐻𝑧
2
Logic Symbol
Timing diagram
Logic Symbol
Timing diagram
Asynchronous counters are slower than synchronous counters because of the delay in the
transmission of the pulses from flip-flop to flip-flop. With a synchronous circuit, all the bits in the
count change synchronously with the assertion of the clock.
Timing diagram
Timing diagram