Part04 2 Caches

9/27/2022
ĐẠI HỌC
CÔNG NGHỆ VIETNAM NATIONAL UNIVERSITY HANOI (VNU)
ĐẠI HỌC
CÔNG NGHỆ
VNU UNIVERSITY OF ENGINEERING AND TECHNOLOGY
Computer Architecture
Lecture 5: Caches
Xuan-Tu Tran
VNU University of Engineering and Technology &
VNU Information Technology Institute
Vietnam National University, Hanoi
Email: tutx@vnu.edu.vn www.uet.vnu.edu.vn/~tutx
ĐẠI HỌC
CÔNG NGHỆ
Key Characteristics of Computer Memory Systems
Location Performance
Internal (e.g. processor registers, cache, Access time
main memory) Cycle time
External (e.g. optical disks, magnetic disks, Transfer rate
tapes) Physical Type
Capacity Semiconductor
Number of words Magnetic
Number of bytes Optical
Unit of Transfer Magneto-optical
Word Physical Characteristics
Block Volatile/nonvolatile
Access Method Erasable/nonerasable
Sequential Organization
Direct Memory modules
Random
Associative
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ĐẠI HỌC
CÔNG NGHỆ
Characteristics of Memory Systems
• Location
– Refers to whether memory is internal and external to the
computer
– Internal memory is often equated with main memory
– Processor requires its own local memory, in the form of registers
– Cache is another form of internal memory
– External memory consists of peripheral storage devices that are
accessible to the processor via I/O controllers
• Capacity
– Memory is typically expressed in terms of bytes
• Unit of transfer
– For internal memory the unit of transfer is equal to the number of
electrical lines into and out of the memory module
ĐẠI HỌC
CÔNG NGHỆ
Method of Accessing Units of Data
Sequential Direct Random

Associative
access access access
Organized Involves a a unique, Access based
into units shared physically on a portion of
of data read-write wired-in its contents
called mechanis addressing rather than its
records m mechanism address
unique Access time: its own
Access in address independent addressing
a specific based on and constant mechanism
linear physical
sequence location retrieval time:
random and constant
Access direct access independent of
Access
time is time is location
variable variable Main memory
& cache Cache
memories
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ĐẠI HỌC
CÔNG NGHỆ
Capacity and Performance:
The two most important characteristics of

memory
Three performance parameters are used:
Access time Memory cycle time Transfer rate

(latency) •Access time plus any additional
• The rate at which
time required before second
• For random-access memory it access can commence data can be
is the time it takes to perform •Additional time may be required transferred into or out
a read or write operation for transients to die out on signal
• For non-random-access lines or to regenerate data if they of a memory unit
memory it is the time it takes are read destructively • For random-access
to position the read-write •Concerned with the system bus,
mechanism at the desired not the processor memory it is equal to
location 1/(cycle time)
ĐẠI HỌC
CÔNG NGHỆ
Memory
– The most common forms are:

– Semiconductor memory
– Magnetic surface memory
– Optical
– Magneto-optical
– Several physical characteristics of data storage are important:

– Volatile memory
• Information decays naturally or is lost when electrical power is switched off
– Nonvolatile memory
• Once recorded, information remains without deterioration until deliberately changed
• No electrical power is needed to retain information
– Magnetic-surface memories
• Are nonvolatile
– Semiconductor memory
• May be either volatile or nonvolatile
– Nonerasable memory
• Cannot be altered, except by destroying the storage unit
• Semiconductor memory of this type is known as read-only memory (ROM)
– For random-access memory the organization is a key design issue

– Organization refers to the physical arrangement of bits to form words
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ĐẠI HỌC
CÔNG NGHỆ
Memory Hierarchy
• Design constraints on a computer’s memory can be summed

up by three questions:
– How much, how fast, how expensive
• There is a trade-off among capacity, access time, and cost
– Faster access time, greater cost per bit
– Greater capacity, smaller cost per bit
– Greater capacity, slower access time
• The way out of the memory dilemma is not to rely on a single
memory component or technology, but to employ a memory
hierarchy
ĐẠI HỌC
CÔNG NGHỆ
g-
Re r s
e
i st
Inb e
ch
me oard Ca
mo in
ry Ma ory
m
me
Ou isk
cd
t eti
sto boar gn OM
rag d M a D- R W
e C D -R W
C R M
D-
D V D- R A y
V a
D lu-R
B
Of e
f ta p
sto -line ne
ti c
rag g
e Ma
Figure 4.1 The Memory Hierarchy
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ĐẠI HỌC
CÔNG NGHỆ
Cache example
• Two levels of memory

• L1: 1000 words T1 + T2
– Access time: T1=0.01us
• L2: 100,000 words T2
– Access time: T2=0.1us
Average access time

• Access rule:
– L1: direct processing
– L2: transfer to L1 first
– Ignore the time for processor to
decide the word in L1 or in L2
T1
• Average access time: 95%
hit
0.95T1+0.05(T1+T2)=0.015us 0 1
Fraction of accesses involving only Level 1 (Hit ratio)
Figure 4.2 Performance of a Simple Two-Level Memory
ĐẠI HỌC
CÔNG NGHỆ
Memory
• The use of three levels exploits the fact that semiconductor

memory comes in a variety of types which differ in speed and
cost
• Data are stored more permanently on external mass storage
devices
• External, nonvolatile memory is also referred to as
secondary memory or auxiliary memory
• Disk cache
– A portion of main memory can be used as a buffer to hold data
temporarily that is to be read out to disk
– A few large transfers of data can be used instead of many small
transfers of data
– Data can be retrieved rapidly from the software cache rather than
slowly from the disk
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ĐẠI HỌC
CÔNG NGHỆ
Cache & main memory
Block Transfer
Word Transfer
CPU Cache Main Memory

Fast Slow
(a) Single cache
Level 1 Level 2 Level 3 Main

CPU
(L1) cache (L2) cache (L3) cache Memory
Fastest Fast
Less Slow
fast
(b) Three-level cache organization

Figure 4.3 Cache and Main Memory
ĐẠI HỌC
CÔNG NGHỆ
Cache/Main memory structure
Line Memory
Number Tag Block address
0 0
1 1
2 2 Block 0
3 (K words)
C–1
Block Length
(K Words)
(a) Cache
Block M – 1
2n – 1
Word
Length
(b) Main memory
Figure 4.4 Cache/Main-Memory Structure
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ĐẠI HỌC
CÔNG NGHỆ
START
Receive address
RA from CPU
Is block No Access main

containing RA memory for block
in cache? containing RA
Yes
Fetch RA word Allocate cache

and deliver line for main
to CPU memory block
Load main
Deliver RA word
memory block
to CPU
into cache line
DONE
Figure 4.5 Cache Read Operation
ĐẠI HỌC
CÔNG NGHỆ
Typical Cache organization
Address
Address
buffer
System Bus
Control Control
Processor Cache
Data
buffer
Data
Figure 4.6 Typical Cache Organization
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ĐẠI HỌC
CÔNG NGHỆ
Elements of Cache Design
Cache Addresses Write Policy

Logical Write through
Physical Write back
Cache Size Line Size
Mapping Function Number of caches
Direct Single or two level
Associative Unified or split
Set Associative
Replacement Algorithm
Least recently used (LRU)
First in first out (FIFO)
Least frequently used (LFU)
Random
ĐẠI HỌC
CÔNG NGHỆ
Cache Addresses
• Virtual memory
– Facility that allows programs to address memory from
a logical point of view, without regard to the amount of
main memory physically available
– When used, the address fields of machine instructions
contain virtual addresses
– For reads to and writes from main memory, a
hardware memory management unit (MMU) translates
each virtual address into a physical address in main
memory
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ĐẠI HỌC
CÔNG NGHỆ
Caches with virtual memory
Logical address Physical address

MMU
Processor Main
Cache memory
Data
(a) Logical Cache
Logical address Physical address

MMU
Processor Main
Cache memory
Data
(b) Physical Cache

Figure 4.7 Logical and Physical Caches
ĐẠI HỌC
CÔNG NGHỆ
Cache sizes of some processors
Year of
Processor Type L1 Cachea L2 cache L3 Cache
Introduction
IBM 360/85 Mainframe 1968 16 to 32 kB — —
PDP-11/70 Minicomputer 1975 1 kB — —
VAX 11/780 Minicomputer 1978 16 kB — —
IBM 3033 Mainframe 1978 64 kB — —
IBM 3090 Mainframe 1985 128 to 256 kB — —
Intel 80486 PC 1989 8 kB — —
Pentium PC 1993 8 kB/8 kB 256 to 512 KB —
PowerPC 601 PC 1993 32 kB — —
PowerPC 620 PC 1996 32 kB/32 kB — —
PowerPC G4 PC/server 1999 32 kB/32 kB 256 KB to 1 MB 2 MB
IBM S/390 G6 Mainframe 1999 256 kB 8 MB —
Pentium 4 PC/server 2000 8 kB/8 kB 256 KB —
High-end
IBM SP server/ 2000 64 kB/32 kB 8 MB —
supercomputer
CRAY MTAb Supercomputer 2000 8 kB 2 MB —
Itanium PC/server 2001 16 kB/16 kB 96 KB 4 MB
Itanium 2 PC/server 2002 32 kB 256 KB 6 MB
IBM High-end
2003 64 kB 1.9 MB 36 MB
POWER5 server
CRAY XD-1 Supercomputer 2004 64 kB/64 kB 1MB —
IBM
PC/server 2007 64 kB/64 kB 4 MB 32 MB
POWER6
IBM z10 Mainframe 2008 64 kB/128 kB 3 MB 24-48 MB
Intel Core i7 Workstaton/
EE 990
2011 6 ´ 32 kB/32 kB 1.5 MB 12 MB
server
IBM 24 MB L3
zEnterprise
Mainframe/ 24 ´ 64 kB/
9/27/2022 Server
2011
Xuan-Tu Tran128 kB 24 ´ 1.5 MB 192 MB 18
196 L4
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ĐẠI HỌC
CÔNG NGHỆ
Mapping Function
• Because there are fewer cache lines than main memory

blocks, an algorithm is needed for mapping main memory
blocks into cache lines
• Three techniques can be used:
Direct Associative Set Associative

• The simplest • Permits each main • A compromise that
technique memory block to be exhibits the strengths
loaded into any line of the
• Maps each block of cache of both the direct and
main memory into associative
• The cache control logic approaches while
only one possible interprets a memory
cache line address simply as a Tag reducing their
and a Word field disadvantages
• To determine whether a
block is in the cache, the
cache control logic must
simultaneously examine
every line’s Tag for a
match
ĐẠI HỌC
CÔNG NGHỆ
Example system
• Cache size: 64KB
• Block size: 4 bytes
• Cache lines: 16KB or 214 lines
• Main memory: 16MB or 224 bytes or 4M blocks of 4 bytes
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ĐẠI HỌC
CÔNG NGHỆ
b t b
B0 L0
m lines
Bm–1 Lm–1
First m blocks of
cache memory
main memory
(equal to size of cache) b = length of block in bits
t = length of tag in bits
(a) Direct mapping
t b
L0
one block of
main memory
Lm–1
cache memory
(b) Associative mapping
Figure 4.8 Mapping From Main Memory to Cache:

Direct and Associative
ĐẠI HỌC
CÔNG NGHỆ
Direct mapping
s+w
Cache Main Memory

Memory Address Tag Data WO
Tag Line Word W1 B0
L0 W2
s–r r w W3
s–r
s
W4j
w Li
Compare W(4j+1) Bj
w
W(4j+2)
W(4j+3)
(hit in cache)
1 if match
0 if no match
Lm–1
0 if match
1 if no match
(miss in cache)
Figure 4.9 Direct-Mapping Cache Organization
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ĐẠI HỌC
CÔNG NGHỆ
Main memory address (binary)

Tag
(hex) Tag Line + Word Data
00 000000000000000000000000 13579246
00 000000000000000000000100
00 000000001111111111111000
00 000000001111111111111100
Line
Tag Data Number
16 000101100000000000000000 77777777 00 13579246 0000
16 000101100000000000000100 11235813 16 11235813 0001
16 000101100011001110011100 FEDCBA98 16 FEDCBA98 0CE7
FF 11223344 3FFE
16 000101101111111111111100 12345678 16 12345678 3FFF
8 bits 32 bits
FF 111111110000000000000000 16-Kline cache
FF 111111110000000000000100
FF 111111111111111111111000 11223344
FF 111111111111111111111100 24682468
Note: Memory address values are
in binary representation;
32 bits other values are in hexadecimal
16-MByte main memory
Tag Line Word

Main memory address =
8 bits 14 bits 2 bits
Figure 4.10 Direct Mapping Example
ĐẠI HỌC
CÔNG NGHỆ
Direct Mapping Summary
• Address length = (s + w) bits

• Number of addressable units = 2s+w words or bytes
• Block size = line size = 2w words or bytes
• Number of blocks in main memory = 2s+ w/2w = 2s
• Number of lines in cache = m = 2r
• Size of tag = (s – r) bits
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ĐẠI HỌC
CÔNG NGHỆ
Victim Cache
– Originally proposed as an approach to reduce the conflict

misses of direct mapped caches without affecting its fast
access time
• Fully associative cache
• Typical size is 4 to 16 cache lines
• Residing between direct mapped L1 cache and the next

level of memory
ĐẠI HỌC
CÔNG NGHỆ
s+w
Cache Main Memory

Memory Address Tag Data W0
Tag Word W1
W2
B0
L0
s W3
w Lj
s
W4j
W(4j+1)
Compare w Bj
W(4j+2)
W(4j+3)
(hit in cache)
1 if match
0 if no match
s
Lm–1
0 if match
1 if no match
(miss in cache)
Figure 4.11 Fully Associative Cache Organization
13
058CE7 FEDCBA98 0001
058CE6 000101100011001110011000
058CE7 000101100011001110011100
058CE8 000101100011001110100000
FEDCBA98 FEDCBA98 9/27/2022
3FFFFD 33333333 3FFD
000000 13579246 3FFE
3FFFFF 24682468 3FFF
22 bits 32 bits
16 Kline Cache
3FFFFD 111111111111111111110100 33333333

3FFFFE 111111111111111111111000 11223344
3FFFFF 111111111111111111111100 24682468 Note: Memory address values are
ĐẠI HỌC
CÔNG NGHỆ 16 MByte Main Memory

Tag Word
Tag (hex) Tag Word Data Main Memory Address =
000000 000000000000000000000000 13579246
000001 000000000000000000000100 22 bits 2 bits
Figure 4.12 Associative Mapping Example
Line
Tag Data Number
3FFFFE 11223344 0000
058CE7 FEDCBA98 0001
058CE6 000101100011001110011000
058CE7 000101100011001110011100 FEDCBA98 FEDCBA98
058CE8 000101100011001110100000
3FFFFD 33333333 3FFD
000000 13579246 3FFE
3FFFFF 24682468 3FFF
22 bits 32 bits
16 Kline Cache
3FFFFD 111111111111111111110100 33333333

3FFFFE 111111111111111111111000 11223344
3FFFFF 111111111111111111111100 24682468 Note: Memory address values are
16 MByte Main Memory

Tag Word
Main Memory Address =
22 bits 2 bits
Figure 4.12 Associative Mapping Example
ĐẠI HỌC
CÔNG NGHỆ
Associative Mapping Summary

• Number of blocks in main memory = 2s+ w/2w = 2s
• Number of lines in cache = undetermined
• Size of tag = s bits
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ĐẠI HỌC
CÔNG NGHỆ
Set Associative Mapping
• Compromise that exhibits the strengths of both the direct and

associative approaches while reducing their disadvantages
• Cache consists of a number of sets
• Each set contains a number of lines
• A given block maps to any line in a given set
• e.g. 2 lines per set
– 2 way associative mapping
– A given block can be in one of 2 lines in only one set
B0 L0
ĐẠI HỌC
k lines
CÔNG NGHỆ
Lk–1
B0 L0
Cache memory - set 0
Bv–1
k lines
First v blocks of
main memory
(equal to number of sets)
Lk–1
Cache memory - set 0
Bv–1
First v blocks of
main memory
(equal to number of sets)
Cache memory - set v–1
(a) v associative-mapped caches

Cache memory - set v–1
(a) v associative-mapped caches
B0 L0
one
set
B0 L0
v lines
one
set
v lines
Bv–1 Lv–1
First v blocks of Cache memory - way 1 Cache memory - way k
main memory
Bv–1 (equal to number of sets) Lv–1
First v blocks of Cache memory - way 1 Cache memory - way k
main memory
(equal to number of sets) (b) k direct-mapped caches
(b) k direct-mapped caches
Figure 4.13 Mapping From Main Memory to Cache:

Figure 4.13 Mapping From Main Memory to Cache: k-way Set Associative
k-way Set Associative
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ĐẠI HỌC
CÔNG NGHỆ
s+w
Cache Main Memory

Memory Address Tag Data
B0
Tag Set Word
F0
B1
s–d d w F1
Set 0
s–d Fk–1
Fk s+w
Bj
Compare Fk+i Set 1
(hit in cache) F2k–1

1 if match
0 if no match
0 if match
1 if no match
(miss in cache)
Figure 4.14 k-Way Set Associative Cache Organization
ĐẠI HỌC
CÔNG NGHỆ
Set Associative Mapping Summary

• Number of blocks in main memory = 2s+w/2w=2s
• Number of lines in set = k
• Number of sets = v = 2d
• Number of lines in cache = m=kv = k * 2d
• Size of cache = k * 2d+w words or bytes
• Size of tag = (s – d) bits
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ĐẠI HỌC
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Tag Main Memory Address =
(hex) Tag Set + Word Data
Tag Set Word
000 000000000000000000000000 13579246
000 000000000000000000000100
9 bits 13 bits 2 bits
000 000000001111111111111000
000 000000001111111111111100
Set
Tag Data Number Tag Data
02C 000101100000000000000000 77777777 000 13579246 0000 02C 77777777
02C 000101100000000000000100 11235813 02C 11235813 0001
02C 000101100011001110011100 FEDCBA98 02C FEDCBA98 0CE7
1FF 11223344 1FFE

02C 000101100111111111111100 12345678 02C 12345678 1FFF 1FF 24682468
9 bits 32 bits 9 bits 32 bits

1FF 111111111000000000000000 16 Kline Cache
1FF 111111111000000000000100
1FF 111111111111111111111000 11223344

1FF 111111111111111111111100 24682468
32 bits
Note: Memory address values are
16 MByte Main Memory in binary representation;
other values are in hexadecimal
Figure 4.15 Two-Way Set Associative Mapping Example
ĐẠI HỌC
CÔNG NGHỆ
1.0
0.9
0.8
0.7
Hit ratio
0.6
0.5
0.4
0.3
0.2
0.1
0.0
1k 2k 4k 8k 16k 32k 64k 128k 256k 512k 1M
Cache size (bytes)
direct
2-way
4-way
8-way
9/27/2022 16-way Xuan-Tu Tran 34
Figure 4.16 Varying Associativity over Cache Size
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ĐẠI HỌC
CÔNG NGHỆ
Replacement Algorithms
• Once the cache has been filled, when a new block is brought
into the cache, one of the existing blocks must be replaced
• For direct mapping there is only one possible line for any
particular block and no choice is possible
• For the associative and set-associative techniques a
replacement algorithm is needed
• To achieve high speed, an algorithm must be implemented in
hardware
ĐẠI HỌC
CÔNG NGHỆ
The most common replacement algorithms are:
• Least recently used (LRU)

– Most effective
– Replace that block in the set that has been in the cache longest with
no reference to it
– Because of its simplicity of implementation, LRU is the most popular
replacement algorithm
• First-in-first-out (FIFO)
– Replace that block in the set that has been in the cache longest
– Easily implemented as a round-robin or circular buffer technique
• Least frequently used (LFU)
– Replace that block in the set that has experienced the fewest
references
– Could be implemented by associating a counter with each line
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ĐẠI HỌC
CÔNG NGHỆ
Write Policy
When a block that is resident in

There are two problems to
the cache is to be replaced there
contend with:
are two cases to consider:
If the old block in the cache has not been

altered then it may be overwritten with a More than one device may have access
new block without first writing out the old to main memory
block
If at least one write operation has been A more complex problem occurs when
performed on a word in that line of the multiple processors are attached to the
cache then main memory must be same bus and each processor has its
updated by writing the line of cache out own local cache - if a word is altered in
to the block of memory before bringing in one cache it could conceivably
the new block invalidate a word in other caches
Write Through
and Write Back
ĐẠI HỌC
CÔNG NGHỆ
• Write through
– Simplest technique
– All write operations are made to main memory as well as to the cache
– The main disadvantage of this technique is that it generates
substantial memory traffic and may create a bottleneck
• Write back
– Minimizes memory writes
– Updates are made only in the cache
– Portions of main memory are invalid and hence accesses by I/O
modules can be allowed only through the cache
– This makes for complex circuitry and a potential bottleneck
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ĐẠI HỌC
CÔNG NGHỆ Line Size
block size
Two specific effects
a block increases come into play:
of data more • Larger blocks reduce
is useful data the number of blocks
retrieve are that fit into a cache
d with brought • block becomes larger;
each additional word
adjacen into the is farther from the
t words cache requested word
block size The hit ratio

decrease as the
increases; block becomes
hit ratio will bigger; the
at first probability of using
the newly fetched
increase information < the
because of probability of
the reusing the
principle of information that
has to be replaced
locality
ĐẠI HỌC
CÔNG NGHỆ
Multilevel Caches
• As logic density has increased it has become possible to have

a cache on the same chip as the processor
• The on-chip cache reduces the processor’s external bus
activity and speeds up execution time and increases overall
system performance
– When the requested instruction or data is found in the on-chip cache,
the bus access is eliminated
– On-chip cache accesses will complete appreciably faster than would
even zero-wait state bus cycles
– During this period the bus is free to support other transfers
• Two-level cache:
– Internal cache designated as level 1 (L1)
– External cache designated as level 2 (L2)
• Potential savings due to the use of an L2 cache depends on
the hit rates in both the L1 and L2 caches
• The use of multilevel caches complicates all of the design
issues related to caches, including size, replacement
algorithm, and write policy
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ĐẠI HỌC
CÔNG NGHỆ
0.98
0.96
0.94
0.92
0.90
L1 = 16k
Hit ratio
0.88 L1 = 8k
0.86
0.84
0.82
0.80
0.78
1k 2k 4k 8k 16k 32k 64k 128k 256k 512k 1M 2M
9/27/2022 L2 Cache sizeTran

Xuan-Tu (bytes) 41
Figure 4.17 Total Hit Ratio (L1 and L2) for 8 Kbyte and 16 Kbyte L1
ĐẠI HỌC
CÔNG NGHỆ
Unified Versus Split Caches
• Has become common to split cache:

– One dedicated to instructions
– One dedicated to data
– Both exist at the same level, typically as two L1 caches
• Advantages of unified cache:
– Higher hit rate
• Balances load of instruction and data fetches automatically
• Only one cache needs to be designed and implemented
• Trend is toward split caches at the L1 and unified
caches for higher levels
• Advantages of split cache:
– Eliminates cache contention between instruction fetch/decode
unit and execution unit
• Important in pipelining
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ĐẠI HỌC
CÔNG NGHỆ
Intel Cache Evolution
Processor on which
Feature First
Problem Solution Appears
Add external cache using 386
External memory slower than the system
faster memory
bus.
technology.
Increased processor speed results in Move external cache on- 486
chip, operating at the
external bus becoming a bottleneck for
same speed as the
cache access.
processor.
Internal cache is rather small, due to Add external L2 cache 486
limited space on chip using faster technology
than main memory
Contention occurs when both the Create separate data and Pentium
Instruction Prefetcher and the Execution instruction caches.
Unit simultaneously require access to the
cache. In that case, the Prefetcher is stalled
while the Execution Unit’s data access
takes place.
Create separate back-side Pentium Pro
bus that runs at higher
speed than the main
Increased processor speed results in
(front-side) external bus.
external bus becoming a bottleneck for L2
The BSB is dedicated to
cache access.
the L2 cache.
Move L2 cache on to the Pentium II
processor chip.
Some applications deal with massive Add external L3 cache. Pentium III
databases and must have rapid access to
9/27/2022 large amounts of data. The on-chip caches Move
Xuan-TuL3Tran
cache on-chip. Pentium 4 43
are too small.
ĐẠI HỌC
CÔNG NGHỆ
Pentium 4 Block Diagram
System Bus
Out-of-order L1 instruction Instruction

execution cache (12K mops) fetch/decode
logic unit
64
bits
L3 cache
(1 MB)
Integer register file FP register file
Load Store Simple Simple Complex FP/ FP

address address integer integer integer MMX move
unit unit ALU ALU ALU unit unit L2 cache
(512 KB)
L1 data cache (16 KB) 256

bits
Figure 4.18 Pentium 4 Block Diagram
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ĐẠI HỌC
CÔNG NGHỆ
Table 4.5 Pentium 4 Cache Operating Modes
Control Bits Operating Mode

CD NW Cache Fills Write Throughs Invalidates
0 0 Enabled Enabled Enabled
1 0 Disabled Enabled Enabled
1 1 Disabled Disabled Disabled
Note: CD = 0; NW = 1 is an invalid combination.
Summary
ĐẠI HỌC
CÔNG NGHỆ
Cache
Chapter 4 Memory
– Elements of cache
• Computer memory
design
system overview
– Cache addresses
– Characteristics of
Memory Systems – Cache size
– Memory Hierarchy – Mapping function
• Cache memory – Replacement
algorithms
principles
– Write policy
– Pentium 4 cache
– Line size
organization
– Number of caches
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ĐẠI HỌC
CÔNG NGHỆ
Intel Coffee Lake
ĐẠI HỌC
CÔNG NGHỆ
ARM Cache
24
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ĐẠI HỌC
CÔNG NGHỆ
Tổ chức ARM Cache …
ĐẠI HỌC
CÔNG NGHỆ
Apple A8 CPU
• 2 cores
• Max. CPU clock: 1.38 GHz
• Min. feature size: 20 nm
• Instruction set: ARMv8-A
• L1 cache: Per core: 64 KB instruction + 64 KB data
• L2 cache: 1 MB shared
• L3 cache: 4 MB
• 1 GB of LPDDR3 RAM included in the package
• GPU: PowerVR Series 6XT GX6450 (quad core)
• 2 billion transistors, physical size reduced by 13% to 89 mm2
• Produced by Taiwan Semiconductor Manufacturing Company
Limited (TSMC)
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ĐẠI HỌC
CÔNG NGHỆ
Apple A8X, 10/2014
• Cores: 3
• Max. CPU clock rate: 1.5 GHz
• Min. feature size: 20 nm
• Instruction set: A64, A32, T32
• Microarchitecture: Typhoon ARMv8-A-compatible
• L1 cache Per core: 64 KB instruction + 64 KB data
• L2 cache 2 MB shared
• L3 cache 4 MB
• Predecessor Apple A7
• Successor Apple A9X
• GPU PowerVR Series 6XT GXA6850 (octa-core)
ĐẠI HỌC
CÔNG NGHỆ
Apple A9
• Cores: 2
• Max. CPU clock rate: 2.16 -2.26 GHz
• Min. feature size: 16 (TSMC)->14(Samsung) nm
• L1 cache/core: 64 KB instruction + 64 KB data
• L3 cache 4 MB (not for A9X)
• GPU : PowerVR Series 7XT GT7600 (six-core)
A9X PowerVR Series 7XT (12 cores)
• included 2 GB of LPDDR4 RAM (not for A9X – 4GB)
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ĐẠI HỌC
CÔNG NGHỆ
Apple A10 Fusion
• Cores: 2
• Max. CPU clock rate: 2.34 GHz
• Min. feature size: 16 (TSMC) nm
• L1 cache/core: 64 KB instruction + 64 KB data
• L3 cache 4 MB (not for A9X)
• GPU : (six-core)
• included the LPDDR4 RAM: 2 GB – iPhone 7; 3GB for 7+
ĐẠI HỌC
CÔNG NGHỆ
A11 Bionic
• Min. feature size: 10 nm (4.3 billion transistors on a die 87.66

mm2 in size, 41% smaller than the A10)
• Instruction set: A64, ARMv8-A compatible
• Cores: Hexa-core (2× Monsoon + 4× Mistral)
• L1 cache: 64 KB instruction, 64 KB data
• L2 cache: 8 MB
• GPU: Apple-designed 3 core
• 2 GB of LPDDR4 for iPhone 8

• 3 GB of LPDDR4 for iPhone 8 Plus and iPhone X
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ĐẠI HỌC
CÔNG NGHỆ
A12 Bionic
• Min. feature size: 7nm (6.9 billion transistors on a die

83.27mm2 in size, 5% smaller than the A11)
• Instruction set: A64, ARMv8.3 compatible
• Cores: Hexa-core (2× Vortex + 4×Tempest)
• L1 cache: 128 KB instruction, 128 KB data
• L2 cache: 8 MB
• GPU: Apple-designed 4 core
• 3 GB of LPDDR4 for iPhone XR

• 4 GB of LPDDR4 for iPhone XS, XS Max
ĐẠI HỌC
CÔNG NGHỆ
Qualcomm Snapdragon
SoC Snapdragon 845 Snapdragon 835 Snapdragon 820 Snapdragon 810

4x Kryo 385
4x Kryo 280
Performance 2x Kryo@1.593GHz 4x A53@1.555GHz
Performance
4x256MB L2 512KB(?) L2 cache 512KB L2 cache
CPU @ 2.45GHz 2MB L2
4x Kryo 845 Efficiency 2x Kryo@2.150GHz 4x A57@1.958GHz
4x Kryo 280 Efficiency
4x128KB L2 1MB(?) L2 cache 2MB L2 cache
@ 1.90GHz 1Mb L2
2MB L3
2x 32-bit 2x 32-bit
2x 32-bit @ 1866MHz 2x 32-bit @ 1866MHz
Memory LPDDR4 @ LPDDR4 @
LPDDR4x LPDDR4x
Controller 1803MHz 1555MHz
29.9GB/s 29.9GB/s
28.8GB/s b/w 24.8GB/s b/w
Adreno 630 Adreno 540 Adreno 530 Adreno 430
GPU
@ 710MHz @ 710MHz @ 624MHz @ 600MHz
Mfc.
10nm LPP 10nm LPP 14nm LPP 20nm SoC
Process
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ĐẠI HỌC
CÔNG NGHỆ
Exynos 7 Octa 7420, 2015
• Technology: 14 nm LPE
• Instruction Set: ARMv8-A
• Microarchitecture: Cortex-A57+
Cortex-A53 (big.LITTLE with GTS)
• Cores: 4 (2.1GHz) + 4 (1.5GHz)
• GPU: Mali-T760 MP8 @ 772 MHz
• Samsung Galaxy S6, Samsung Galaxy S6 Edge, Samsung

Galaxy S6 Active, Samsung Galaxy S6 Edge+, Samsung
Galaxy Note 5
ĐẠI HỌC
CÔNG NGHỆ
Exynos 8 Octa 8890
• Technology: 14 nm LPE
• Instruction Set: ARMv8-A
• Microarchitecture: Exynos M1
"Mongoose"+ Cortex-A53 (GTS))
• Cores: 4 (2.2-2.6GHz) + 4 (1.6GHz)
• GPU: Mali-T880 MP12 @ 650 MHz
• RAM LPDDR4, 1794 MHz
• Samsung Galaxy S7, S7 Edge, Note 7
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ĐẠI HỌC
CÔNG NGHỆ
Exynos 9 Series (8895)
• CPU: 4 x 2.5GHz Exynos M2 + 4 x 1.7GHz Cortex-A53

• GPU: Mali™-G71 MP20
• 10nm FinFET Process
30

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9/27/2022

Email: tutx@vnu.edu.vn www.uet.vnu.edu.vn/~tutx

9/27/2022 Xuan-Tu Tran 2

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Sequential Direct Random

The two most important characteristics of

Access time Memory cycle time Transfer rate

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– The most common forms are:

– Several physical characteristics of data storage are important:

– For random-access memory the organization is a key design issue

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• Design constraints on a computer’s memory can be summed

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Figure 4.1 The Memory Hierarchy

• Two levels of memory

– Access time: T2=0.1us

Average access time

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Figure 4.2 Performance of a Simple Two-Level Memory

• The use of three levels exploits the fact that semiconductor

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CPU Cache Main Memory

(a) Single cache

Level 1 Level 2 Level 3 Main

(b) Three-level cache organization

Figure 4.3 Cache and Main Memory

Figure 4.4 Cache/Main-Memory Structure

Is block No Access main

Fetch RA word Allocate cache

Figure 4.5 Cache Read Operation

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Figure 4.6 Typical Cache Organization

Cache Addresses Write Policy

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Logical address Physical address

(a) Logical Cache

Logical address Physical address

(b) Physical Cache

Figure 4.7 Logical and Physical Caches

• Because there are fewer cache lines than main memory

Direct Associative Set Associative

• Cache size: 64KB

• Block size: 4 bytes

• Cache lines: 16KB or 214 lines

• Main memory: 16MB or 224 bytes or 4M blocks of 4 bytes

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Figure 4.8 Mapping From Main Memory to Cache:

Cache Main Memory

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Figure 4.9 Direct-Mapping Cache Organization

Main memory address (binary)

16 000101100011001110011100 FEDCBA98 16 FEDCBA98 0CE7

Tag Line Word

Figure 4.10 Direct Mapping Example

• Address length = (s + w) bits