Intemational Journal of Electrical and Computer System Design www.ijecsd.com BIST Implementation of Multiplier with Proposed High-Speed Low Power Full Adder K.Yeswanth Sai Rama VaraPrasad *', Mr..Dr.Pankaj Rangaree 2 ~ Stusent of E&C Deparment, Vaagdeui college of engineering, Werangal Indi, Kasiyeswanth@gml.com. * Asst. Prot of EBC Department, Vaagdevi calege of engineering, Warangal India, Phrangaree247 @gmall.com. Abstract: Low-power VLSI design circuits are critcal advancement need in recent years due to the high demand for portable consumer electronics. In this regard many innovative designs for basic logic functions using pass transistors and transmission gates have appeared inthe literature recently. ‘This paper presents a novel low-power imply logic-based 1-bit full adder that uses Metal oxide semiconductor transistors (MOS) inits structure. Proposed design work reliably tow supply voltage. In this design, the power-consuming gates are eliminated, Some of the adder cells are compared and analyzed with proposed adder based on power consumption, speed and area efficiency. Intensive simulation runs on a Mentor Graphics Tanner EDA show that the new adder has more than 9% in power savings over a conventional 28-transistor CMOS adder. We know that as circuits getting smaller and smaller testing is also a major challenge. Traditional testing which involves ATE, is very Costly and requires field testing. Many testing methods are introduced in recent years. Among those BIST method has more advantages than conventional method and detects almost 90% of faults, ‘Therefore, 4x4 multiplier is bul and tested using BIST methad in VHDL on Xilinx ISE platform, Keywords: full adder; low-power; multiplier; testing; BIST; imply, 1. Introduction VLSI has been around for a long time and tools that can be used to design VLSI circuits. Alongside, obeying Moore's law, the capability of an IC has increased exponentially over the years, in terms of computation power, utilization of available area, yield, With the explosive evolution of transistor scaling, esearch work related to low-power design of microelectronics circuits have been greatly escalated. Nowadays, a configurable hardware design performance can be evaluated using its operational speed and power. Field Programmable Gate Array (FPGA) is among the configurable devices that cope with the desired and promising power and speed based hardware performance. In FPGA the operation execution is based on the switching of the internal path of current through a combination of hardware resource architecture. A hardware based optimization of any design can be achieved by the skill based modification of the operational circuit architecture, A low power system offers the benefits like device portabilty, long battery fe, good performance criteria, etc. ‘As a result, demand for high performance design of microelectronic circuits has skyrocketed, Many applications require large scale of arithmetic K.Yeswanth Sai Rama VaraPrasad *', Mr..Dr. Pankaj Rangaree 2 operations. Adders and multipliers are crucial building blocks of Arithmetic Logic Units. A 1-bit Full Adder (FA) is considered as fundamental cell for building wide word-length adders for which many improvements have been made to improve its architecture. Hence, performance enhancement of full adder is crucial 2. Literature Survey The power consumption, area_ and. performance of the designs are the major trade-off factors in low power VLSI circuits [5]. ALU performance affects the performance of overall integrated circuits and processors, The exponentially increasing density of transistors makes integrated circuits complex which demands highly efficient testing procedures. Researchers had developed many logic styles to improve the performance as well as to lower the power dissipation and testing of the VLSI circuits. All these state-of-art researched circuits helped to meet the requirements of the rapidly growing semiconductor industry, Minimizing the supply voltage thereby reducing the ‘operating voltage is the one of the method to reduce the power dissipation of the circuits. But reducing the operating voltage degrades driving capability and increases circuit delay. The performance of many other Page No: 1