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M3, M4, M6 have the same length whereas M3,M4 have same width and length, M5 and M8 forms NMOS current mirror have
same length, M1 and M2 have same width and length 45nm technology depends on the performance of parameters such as (W/L)
ratios to make the chip smaller[8][9].

III. METHODOLOGY
The design the operational amplifier for this research, we adopted 45nm technology. Various research were carried out to
understand more about the operational amplifier's effectiveness, or the circuit's process variation. Various limitations have been
taken into consideration. The node was constructed using 45nm technology, 1.8V was chosen as the voltage supply. In order to
keep all MOS transistors in the saturation zone, the Input Common-Mode Range (ICMR) has been set between 0.8V and 1.6V,
while the threshold voltages for nmos and pmos are 0.45V and 0.5V, respectively[2][4].Similarly, 2PF has been chosen for the
load capacitance so that the poles will remain before the 0dB point. This assures the circuit's stability.
For the optimal condition, the gain, slew rate, and gain-bandwidth product (GBW) have been selected. Here, maintaining the
input voltage and output voltage swing within the ICMR range is crucial. The design process begins with research on exceptional
Op-amp topologies that are frequently used [1][8].

The Design procedure of two stage Operational Amplifier specifications for following parameters are:
a) Voltage supply (VDD) : 1.8V
b) Gain(G) at dc : 80dB
c) Gain bandwidth product (GBW) : 30MHZ
d) Input Common Mode Range (ICMR) : 0.8V to 1.6V[ V vin(min) and vin(max) ]
e) E) Load Capacitance ( ) : 2pF
f) F) Slew Rate (SR) :
Calculation of compensation capacitor ( ):
For 80 degree phase margin, 0.22 ( ) = 0.44pF
Selection of :
Determining the min value for the tail current based on Slew rate requirements = SR( ) = 16 A
Calculation of (3,4):
M3 is diode connected, = , D3 & D1 are same where as = & =
( =
Thus W/L of M3 is determined by using max ICMR [Vin(max)]
( =( as M3,M4 form current mirrors
( =
Approximately chooses as 14.
Calculation of (1,2):
Size of M1 & M2 NMOS input transistors
Choose ( =( to achieve the desired dB
( =
Approximately chooses as 6.
Calculation of (5,8):
( =
( =( as M5,M8 form current mirrors
Approximately chooses as 12.
Calculation of (6):

( =(
( =
Approximately chooses as 180.
Calculation of (7):
( =(
Where as =
Approximately chooses as 75.

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The following figure demonstrates the two stage CMOS Op-amp schematic. The schematic is implemented using the calculated
parameters that taken into consideration design requirements and specifications. Five NMOS and three PMOS constitute the
operational amplifier with W/L values [5][8].

Figure 1: Two Stage OP-amp

Figure 2: Schematic of Two stage Op-amp

IV. RESULTS AND DISCUSSIONS

Before Using a Tanner tool and a 45nm node, the design and optimization of a two-stage CMOS Opamp circuit were verified. A
supply voltage of 1.8V was used. To meet the various limitations of the circuit, multiple analysis including DC, AC, Transient,
and Power analysis have been conducted [7][8].

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Transient Analysis:

DC Analysis:

Temperature Analysis:

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AC Analysis:

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Power Analysis

V. CONCLUSION
After For the two-stage Op-amp, Implementation is a multidimensional optimization problem where enhancing one or more
parameters could actually deteriorate other Additionally, when designing circuits for high dc-gain and high bandwidth
applications, the gain-bandwidth-product continually presents challenges to the designers[1]. As a result, the circuit modelling
was carried out using a tanner tool with a 45nm node. The performance is enhanced by altering parameters like (W/L) ratios.
Additionally, this makes use of design equations, including accurate selection and sizing of the proposed circuit's configuration.
This proposed design achieves 80dB gain and phase margin at unity gain configuration and power dissipation[13][14].
VlSI technology nodes such as 45nm came into existence and more would continue to come in future these technologies depends
on the performance of parameters such as (W/L) ratios to make the chip smaller.

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[10] Shem-Tov, M. Kozak and E. G. Friedman, "A high-speed CMOS op-amp design technique using negative Miller
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