IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO.
5, MAY 2010
1.8 pJ/Pulse Programmable Gaussian Pulse
Generator for Full-Band Noncarrier Impulse-UWB
Transceivers in 90-nm CMOS
Bo Qin, Xin Wang, Haolu Xie, Lin Lin, He Tang, Albert Wang, Fellow, IEEE,
Hongyi Chen, Bin Zhao, Fellow, IEEE, Liwu Yang, and Yumei Zhou
Abstract—This paper presents a single-chip ultralow power
programmable Gaussian pulse generator (PG) designed and im-
plemented in the 90-nm CMOS for 3.1–10.6 GHz full-band
impulse-radio ultrawideband (UWB) transmitters. Measurement
shows that this novel simple two-inverter-based PG achieves the
lowest reported power dissipation of merely 1.8 pJ/pulse with
a 100-MHz pulse-repeating frequency at 1-V supply, extremely
short and programmable pulsewidth ranging from 150 to 350 ps
while covering the full 3.1–10.6 GHz UWB spectrum, and a very
small area of 0.0068 mm2 . It supports up to 6 Gb/s data rate
for UWB wireless streaming. A new Federal-Communication-
Commission-aware Gaussian PG design optimization method is
discussed and verified experimentally.
Index Terms—Gaussian pulse generator (PG), impulse radio
(IR), ultrawideband (UWB).
I. I NTRODUCTION
S INCE the Federal Communication Commission (FCC) re-
leased the 3.1–10.6-GHz unlicensed spectrum for commer-
cial ultrawideband (UWB) applications in 2002, research and
development (R&D) efforts for UWB radio technologies have
mushroomed with the ultimate goal of achieving multigigabit-
per-second (Gb/s+) wireless data streaming for video and
multimedia applications [1]. While significant industrial R&D
work has been devoted to multiband orthogonal frequency-
division multiplexing (MB-OFDM) UWB and direct-sequence
UWB (DS-UWB) protocols mainly to inherent existing intel-
lectual assets, such UWB protocols do not take full advantage
of the original UWB radio principle because both divide the
Manuscript received December 20, 2008; revised July 29, 2009. First pub-
lished August 21, 2009; current version published April 14, 2010. This work
was supported in part by the U.S. National Science Foundation under Grant
0808951 and in part by the Chinese National Natural Science Foundation under
Grant 60776025.
B. Qin was with Tsinghua University, Beijing 100084, China. He is
now with Citruscom Semiconductor, Beijing 100029, China (e-mail: bqin@
citruscomsemi.com).
X. Wang, L. Lin, H. Tang, and A. Wang are with the University of California,
Riverside, CA 92521 USA (e-mail: xwang011@ee.ucr.edu; aw@ee.ucr.edu).
H. Xie and B. Zhao are with Freescale Semiconductor, Libertyville, IL
60048-5339 USA (e-mail: xiehaol@iit.edu; bin.zhao@freescale.com).
H. Chen is with the Institute of Microelectronics at Tsinghua University,
Beijing 100084, China (e-mail: chy-ime@tsinghua.edu.cn).
L. Yang is with Semiconductor Manufacturing International Corporation,
Shanghai 201203, China (e-mail: hbtlwy@yahoo.com).
Y. Zhou is with the Institute of Microelectronics, Chinese Academy of
Sciences, Beijing 100029, China (e-mail: ymzhou@ime.ac.cn).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2009.2029591
0278-0046/$26.00 © 2010 IEEE
1555
full available 3.1–10.6-GHz frequency spectrum into several
subbands/channels in system designs, which proportionally re-
duces the data throughput capacity and has to resort to complex
digital-signal processing means, such as fancy modulation and
deep compression, to achieve reasonable data rates required in
applications [2], [3]. Such UWB schemes apparently increases
the complexity, power, and costs of UWB chips. In addition, the
carrier-based transmission approaches used require frequency
mixers and power amplifiers (PAs), which are generally noisy,
power hungry, and difficult for full CMOS implementation to
realize low-power low-cost UWB SoC in CMOS. Alternatively,
impulse-radio (IR) UWB technique transmits extremely short
impulse trains using the full 3.1–10.6-GHz available spectrum
and in a carrier-free scheme. IR-UWB has advantageous fea-
tures, such as much simpler RF front-end architecture without
mixer and PA; simple modulation, e.g., BPSK modulation
and noncompression schemes for simple and low-power dig-
ital baseband; most-digital and full CMOS implementation;
etc., which will eventually make it possible to realize low-
power low-cost CMOS UWB SoC desired for multigigabit-
per-second high quality-of-service (hi-QoS) multimedia and
video wireless-streaming applications [4]. A Gaussian pulse-
generator (PG) circuit plays the core role in a UWB transceiver
because it produces the UWB pulse signals with very short
pulsewidth to enable high data-rate communications.
In order to completely comply with and take full use of
the effective isotropic radiated power (EIRP) spectral mask
over the 3.1–10.6-GHz band regulated by FCC, the pulsewidth
and amplitude of radiated UWB signals must follow very
stringent restriction, i.e., pulsewidth of less than 1 ns and pulse
amplitude of less than 1 V, with tunable features. Therefore, it
is extremely challenging to design UWB PGs and transmitters
meeting such strict specifications while achieving low-power
high-throughput operation to enable low-cost CMOS IR-
UWB systems. Early reported PG designs use step-recovery
diode, microstrip, and surface acoustic-wave technique for
pulse generation [5]–[7], which do not meet the integration,
low-power, and low-cost requirements. Recently reported
UWB PGs have used analog approaches or complex digital
topologies. For example, a complicated up-converted analog
topology is employed in [8] for a Gaussian PG at 5 GHz, which
is fairly power hungry. Reference [9] reports a pulse-position
modulation (PPM) Gaussian PG with calibration to produce
accurate 1-ns pulse, which, however, consumes high power of
1556 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 5, MAY 2010

1.8 nJ/pulse and has a large die size of 1.95 mm2 . Reference
[10] presents a BPSK/PPM transmitter using very complex PG
and phase-locked loop that consumes a 126-pJ/pulse at 1-V
supply in 90-nm CMOS. A three-optional-channel concept
is presented in [11] with a 3-ns pulsewidth and a 550-MHz
bandwidth achieved, which, however, requires a high-pass filter
for FCC compliance. Reference [12] depicts a traditionally
modulated 17-ns PG for the 7–9-GHz band with programmable
carrier, where the bandwidth and pulsewidth greatly limit the
wireless data throughput. Other digital Gaussian PGs using
low-cost low-power topology are also reported. For example,
[13] describes an accurate Gaussian pulse generation under
subthreshold working condition, and [14]–[16] report Gaussian
pulse generation with approximated method; however, all of
them are not easy to control and are sensitive to the process,
voltage, and temperature (PVT) variations.
This paper reports a fully integrated ultralow power program-
mable pulsewidth UWB Gaussian PG for the 7.5-GHz full-band
noncarrier IR-UWB transceivers. Section II discusses basic
pulse-generation principles. Section III describes design details
of the new UWB PG circuit with PVT variations considered.
Section IV presents the measurement results followed by the
conclusions.

II. G AUSSIAN P ULSE G ENERATION

For IR-UWB transceiver, several different waveforms, such
as sinusoidal and rectangular, can be used for UWB signal
transmission. However, Gaussian and its derivative pulses are
favored because their waveform sidelobes have the smallest
energy, making it easier to comply with the strict FCC EIRP
power-spectrum mask. In theory, the time sequence and power-
spectrum density (PSD) of Gaussian pulses can be depicted,
respectively, as
   
1 t2
G0 (t) = A0 √ exp − 2 (1)
2πσ 2σ
 
A2
ε0 (f ) = 0 exp −(2πf σ)2 (2)
Tf
where A0 is the pulse-amplitude parameter, σ is a time constant,
also called variance, and Tf is a pulse interval equal to the
reciprocal of the pulse repeating frequency (PRF).
A. Radiated Signal After Antenna
As shown in (2), the maximum PSD of Gaussian pulse
locates at DC. Considering the FCC-allowable spectrum of
0–960 MHz and 3.1–10.6 GHz, as well as the FCC EIRP
power-mask limitation, there could be two feasible approaches
to implement a Gaussian PG circuit: The first one utilizes
the 0–960-MHz spectrum and uses special wideband antenna
[17], which, however, requires > 1-ns pulsewidth and can only
support lower data throughput due to its limited bandwidth.
The second approach radiates Gaussian pulses through regular
antennas, e.g., impact dipole antenna [18], which has a high-
order-derivative function property that converts an original
Gaussian waveform into higher order derivatives, such as a
second-derivative Gaussian pulse that can be readily transmit-
Fig. 1. Simulated (a) t-domain pulse waveform and (b) f -domain PSD for
Gaussian pulses.
ted over the 3.1–10.6-GHz spectrum. Since the latter approach
can utilize the full 7.5-GHz UWB bandwidth, it has the po-
tential to realize the desired multigigabit-per-second hi-QoS
wireless streaming for multimedia and video applications. This
paper adopts the second approach to design an FCC-compliant
Gaussian PG circuits to produce the desired Gaussian pulses.
A second-derivative Gaussian pulse can be derived from (1)
and (2) and its time and frequency-domain properties are
 2   
t − σ2 t2
G2 (t) = A2 √ exp − 2 (3)
2πσ 5 2σ
 
A22
ε2 (f ) = (2πf )4 exp −(2πf σ)2 . (4)
Tf
Equation (4) reveals that the maximum PSD of a second-
derivative Gaussian pulse shifts from DC to higher frequency,
which can be readily comprehended from its t-domain and
f -domain characteristics shown in Fig. 1. The minor segment
exceeding the FCC power mask, as marked by a circle shown in
Fig. 1, can be taken care of using our new Gaussian PG-design
optimization method that will be discussed in the following
section, where the critical PSD peak and the −10-dB corner
frequencies can be uniquely determined in practical designs.
QIN et al.: 1.8 pJ/PULSE PROGRAMMABLE GAUSSIAN PULSE GENERATOR FOR FULL-BAND UWB TRANSCEIVERS
B. PG-Design Optimization Method
A new Gaussian PG-design optimization method is intro-
duced to ensure optimal PG design completely complying
with the FCC power mask and also fully utilizing the given
FCC spectrum power for enhanced data rate and transmission
distance. The first critical PG-design parameter is the optimal
frequency (fopt ) corresponding to the peak PSD point.
By differentiating (4) against frequency f and setting it to
zero, it gives
√ cordingly, simulated peak amplitude of 200 mV for a Gaussian
2 pulse is selected as optimum value in this design.
fopt = . (5)
2πσ
Obviously, the bell shape of the PSD suggests that the fopt
should be set to the center of the FCC-allowed 3.1–10.6 GHz
spectrum range, i.e., around 7 GHz, which ensures that the gen-
erated second-derivative Gaussian pulse possess the most signal
power allowed by FCC EIRP mask while fully complying with
the regulation. Using (5), the time parameter σ is optimized at
about 32 ps.
The next critical parameter for the second-derivative
Gaussian waveform is the amplitude parameter A2 , which can
be calculated following the −10-dB corner-frequency rule, i.e.,
−10 dB off the −41.3-dBm/MHz FCC PSD limitation from the
10.6-GHz end. Consider that the PSD varies little over a 1-MHz
frequency interval; by integrating (4) for the PSD at 10.6 GHz
across 1 MHz, A2 can be found approximately from
A22  
106 · (2πf )4 exp −(2πf σ)2 = 10−5.13 · 10−3 . (6)
Tf
Assuming PRF = 100 MHz and substituting f = 10.6 GHz
and σ = 32 ps into (6), the preferred A2 is calculated as
1.881 × 10−32 . Then, using the calculated optimum time
parameter (σ) and amplitude parameter (A2 ), the allowable
peak amplitude for a second-derivative Gaussian with FCC
EIRP compliance can be estimated from (3) as
A2
G2 (t)|peak = √ = 229 mV. (7)
2πσ 3
Further, considering complete FCC compliance, two critical
corner frequencies of 1.61 GHz with −75.3 dBm and 10.6 GHz
with −51.3 dBm ought to be used in calculating the optimum
σ and A2 . Therefore, using (6) and (7), the actual optimized
PG parameters of σ = 21 ps and A2 = 5.161 × 10−33 are ob-
tained to ensure a completely FCC-compliant second-derivative
Gaussian pulse with its peak not exceeding 222 mV. These
critical parameters are used in this design following our new
PG-design optimization method.
C. Practical PG-Design Consideration
Using the aforementioned PG-design technique and the es-
timated allowable peak second-derivative Gaussian amplitude
G2 (t)|peak , one can readily derive the required zeroth-order
Gaussian pulse G0 (t)|peak , adopting various antenna models
accordingly. In this paper, a simple antenna model reported in
[18] is used to demonstrate our new design methodology, where
1557
TABLE I
S UMMARY OF THE G AUSSIAN PG D ESIGN PARAMETERS
the inductor value is reasonably reduced for cost concern. Ac-
Next, we consider designing the Gaussian pulsewidth, which
can be derived from the time parameter σ that, in nature,
determines the transmitted pulsewidth. The pulsewidth τ is
defined as the time period across which the energy accumulated
achieves 99.9% of that over an infinite time period, as follows:
τ /2  ∞
G2n (t) G2n (t) ≥ 99.9%. (8)
−∞
−τ /2
From (8), the pulsewidth of the Gaussian and its second-
derivative pulse is found to be about 5σ and 7σ for > 99.9%
pulse-energy coverage, respectively. From (5) and (8), impor-
tant relationships among critical design parameters are ex-
tracted and summarized in Table I. Therefore, following the
new PG-design method and using the aforementioned analysis,
assume a dipole antenna having the required second-derivative
function; the optimum PG design parameters are chosen as
the pulsewidth of 160 ps for the Gaussian pulse and 225 ps
for the radiated second-derivative Gaussian-pulse signal after
the antenna, and fopt = 7 GHz for the maximum spectrum
that is around the center of the FCC-allocated UWB spectrum
of 3.1–10.6 GHz. Therefore, such a narrow Gaussian pulse
generated shall fully comply with the FCC UWB power mask.
In this paper, a 160-ps all-digital Gaussian PG is designed for
low-power low-cost UWB transceivers.
III. PG C IRCUIT D ESIGN
While direct-mapping method to create Gaussian PG accord-
ing to (1) seems to be doable [12], it is practically infeasible in
designing any real-world Gaussian PGs due to the extremely
complicated circuitry and control mechanisms involved in ac-
tual designs. Alternatively, a two-inverter-based approximate
Gaussian pulse-generation algorithm is proposed in this paper,
where the exponential function associated with capacitive-load
charging and discharging procedures serves to generate the
various Gaussian pulses required. Fig. 2 shows the topology of
a Gaussian PG and its two-inverter concept.
As shown in Fig. 2, the two inverters are composed of Mp1,
Mn1, Mp2, and Mn2, while Md1 and Md2 forms the delay cell,
which will generate a delay between signals at nodes X and
Y . C1, C2, and C3 are parasitic capacitors. Clearly, only when
the two signals become “Low” simultaneously that a Gaussian
pulse can be generated at node Z and radiated through the
antenna. To understand it, assume that input changes from “0”
to “1”; the precharged C1 starts to discharge via Mn1 and VX
1558
Fig. 2. Approximate two-inverter-based Gaussian PG topology.
drops gradually to zero, which then turns on Mp2 and moves
it from off to saturation for small VZ . Assume C1 is being
charged to VDD initially, a Gaussian pulse will be generated
at VZ due to the exponential behavior of capacitor charging and
discharging.
The new Gaussian approximation-design method can be
appreciated using (9), showing its output at the bottom
of the page, where η = ζVT C1 /In , M = I0 η/C3 , P =
Kp (VDD − Vth )2 /C3 , Q = P • 2Req Cp1 , Vth is threshold
voltage, In = Kn (VDD − Vth )2 is the saturation current, and
Req = 1/Kn (VDD − Vth ) is the equivalent linear-region resis-
tance for M1n. This output-pulse amplitude, by approximation,
is compared with the ideal Gaussian simulation as shown in
Fig. 3, which shows a good matching. The minor discontinuity
point observed, marked by a dashed circle, is attributed to
the adoption of a simplified two-segment CMOS modeling for
weak inversion to saturation transition in the analysis as shown
in (9), which does not occur in real transistor operation.
Because the designed Gaussian PG features very short
pulsewidth, sensitivity of the two-inverter-based PG topology to
inevitable process, voltage supply, and temperature variations
should be studied. A Monte Carlo simulation is performed
for this design. Unfortunately, at the time of this design, the
90-nm CMOS technology used was in its early qualification
phase, which could not guarantee the desired accuracy level for
both the PDK device models and its Monte Carlo models. Thus,
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 5, MAY 2010
Fig. 3. Fifth-derivative Gaussian pulse obtained by approximation agrees well
with the ideal Gaussian pulse.
it significantly undermines the performance of the PG designed
in this paper.
Fig. 4 shows the Monte Carlo statistics for the PG pulsewidth
and peak amplitude after 2000 simulation iterations. Two obser-
vations are worth a discussion: First, the average pulsewidth and
the peak amplitude obtained shift slightly from the optimized
values using our new design method discussed previously; this
is mainly attributed to the PDK model inaccuracy of the im-
mature 90-nm CMOS technology used in this design. Second,
Monte Carlo simulation reveals that, even in the presence of
process-model inaccuracy, the obtained pulsewidth and peak-
amplitude values are still fairly compact around their center
data, indicating a reasonably good PVT immunity. Neverthe-
less, considering the extremely short pulsewidth and ultrahigh
data rate in practical applications, a programmable pulsewidth-
control mechanism shall still be a value-added feature in UWB
Gaussian PG design to fine tune the PG pulses generated to
accommodate any substantial PVT variations.
Fig. 5 shows a detailed schematic for the embedded program-
mable control circuitry used in this design. Transistors M1–M4
are relatively large to generate clean and sharp square wave
at node X. Transistors M5 and M5a–M5c provide sourcing
current for the delay cell, which sets the delay time between
the two square waves at nodes X and Y . As M5a–M5c switch
on and off, the sourcing current to node Y changes, resulting in
a variation of the delay time. Therefore, if significant PVT vari-
ation occurs, the pulsewidth and the amplitude of the generated
Gaussian waveform can be fine-tuned accordingly. Transistors
M8–M11 constitute the Gaussian-pulse formation block, which
is a simple NOR gate. In order to avoid the charge sharing at
node P , the connection should be fixed as shown in Fig. 5.

⎧  t

⎪
⎨ M eη − 1 , (t ≤ t1 = Vth C1 /In )
VZ =  t1
 t−t 2(t−t )
 (9)
⎪
⎩ M e η − 1 + P (t − t1 ) + Q − Req C1
4e 1 −e
− Req C1
1 −3 , (t > t1 )
4
QIN et al.: 1.8 pJ/PULSE PROGRAMMABLE GAUSSIAN PULSE GENERATOR FOR FULL-BAND UWB TRANSCEIVERS
Fig. 4. Monte Carlo simulation results of the pulsewidth and peak amplitude
for Gaussian PG show tight distribution.
Fig. 5. Schematic for Gaussian PG with embedded tunable control mecha-
nism serves to fine-tune pulsewidth and accommodate possible PVT variations.
IV. M EASUREMENTS AND D ISCUSSIONS
The new programmable zeroth-order Gaussian PG was de-
signed and implemented in a foundry 90-nm CMOS. Fig. 6(a)
shows the die photograph of the PG circuit that occupies a very
1559
Fig. 6. Die photographs for the Gaussian PG circuits design. (a) Zeroth-order
Gaussian PG in 90-nm CMOS. (b) Second-derivative Gaussian PG in 0.13-μm
CMOS.
small area of 0.0068 mm2 . For testing flexibility, three splits
are designed in one tapeout, and the controls Ca, Cb, and Cc
are connected to VDD or GND separately in each split.
Fig. 7 shows a sample measured pulse train and enlarged
waveform that shows a very short pulsewidth of 180 ps and
amplitude of 80 mV. By choosing different combinations of
the controls Ca, Cb, and Cc, the measured Gaussian pulses
can be tuned in both time and frequency domains, as shown
in Fig. 8, to realize the programmable function, which can
tune the pulsewidth from 150 to 350 ps. The measured PG
power consumption is merely 1.8 pJ/pulse at 1.0-V supply
voltage for a 100-MHz PRF, which is the lowest reported PG
power dissipation in the same category, to our best knowledge.
The measured PG spectrum is well predicted by the simulated
zeroth-order Gaussian PG circuit PSD shown in Fig. 1(b). It is
observed that closer to DC, the spectrum becomes higher, and
for smaller pulsewidth, the spectrum spreads wider in the fre-
quency band, both predicted in circuit analysis and simulation.
The measured PSD clearly shows that the peak PSD locates at
the DC end and a higher order derivation function, e.g., second-
derivative Gaussian PG, is needed to ensure FCC power-mask
compliance as verified later.
To confirm experimentally the previous discussion that
higher order Gaussian derivation function, for example, using
antenna, serves to shift the PSD peak to higher frequency end,
which can ensure better FCC EIRP mask compliance, a separate
split of higher order Gaussian PG with simple antenna-model
circuitry on chip were designed and implemented in a 0.13-μm
CMOS, not with the same 90-nm CMOS due to lack of RF
inductors in the 90-nm process at the time of this design.
1560 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 5, MAY 2010

Fig. 7. Measured Gaussian pulse train and single-pulse waveform.

Fig. 6(b) shows the die photograph for the higher order PG
that occupies an area of 0.07 mm2 . Fig. 9 shows the measured
Gaussian-pulse waveform as predicted in Fig. 1(a) for a second-
derivative Gaussian pulse. Fig. 10 shows the measured PSD Fig. 8. Measured tunable Gaussian-pulse waveforms in (a) t-domain and
(b) their PSDs in f -domain under 100-MHz PRF. The PSD curves agree with
spectrum, which clearly shows that the fopt , corresponding to well simulation and confirm that the second-derivative Gaussian function is
the PSD peak, shifts toward higher frequency as predicted, serv- needed to ensure FCC EIRP mask compliance.
ing to convert the non-FCC-compliant zeroth-order Gaussian
pulse to an FCC-compliant Gaussian pulse. The observed minor
PSD exceeding the FCC mask is mainly attributed to the PDK
model inaccuracy problem for the 90-nm CMOS at the time of
this design, which leads to many issues, such as larger than real
parasitic capacitance in the delay cell that caused inaccuracy
in post simulation. Consequently, the measured pulsewidth of
320 ps is bigger than the target of 225 ps, and the central
frequency shifts toward the lower end.
Table II summarizes key circuit specifications for the re-
ported state of the art in the similar Gaussian PG category.
It clearly shows that this design occupies the smallest circuit
size of 0.0068 mm2 due to novel two-inverter-based all-digital
topology, the lowest reported power dissipation of only 1.8 pJ/
pulse, and extremely short and programmable pulsewidth rang-
Fig. 9. Measured waveform of second-derivative Gaussian PG with on-chip
ing from 150 to 350 ps while covering the full 3.1–10.6-GHz antenna model circuitry in 0.13-μm CMOS agrees with simulation.
UWB spectrum.
the lowest reported power dissipation of 1.8 pJ/pulse and
extremely short and programmable pulsewidth ranging from
V. C ONCLUSION
150 to 350 ps while covering the full 3.1–10.6-GHz UWB
This paper has presented a design of a 1.8 pJ/pulse ultralow spectrum. The die area of this design is merely 0.0068 mm2
power fully integrated 3.1–10.6-GHz Gaussian PG fabricated in due to the novel two-inverter-based all-digital topology used.
a foundry 90-nm CMOS. Measurement shows that it achieves A new Gaussian PG-design optimization method has been
QIN et al.: 1.8 pJ/PULSE PROGRAMMABLE GAUSSIAN PULSE GENERATOR FOR FULL-BAND UWB TRANSCEIVERS
Fig. 10. Measured PSD of the second-derivative Gaussian PG with on-chip
antenna model circuitry moves the fopt toward higher end to comply with FCC
EIRP mask. Slight deviation from simulation is mainly attributed to inaccuracy
of the PDK models used.
TABLE II
P ERFORMANCE C OMPARISON W ITH THE S TATE OF THE A RT
presented that is verified experimentally in this paper. This
PG achieves the desired performance for noncarrier full-band
Gb/s+ throughput, low-power low-cost UWB SoCs, which
facilitates many industrial and consumer wireless applications,
such as hi-QoS video and multimedia wireless streaming, in-
dustrial wireless control, in-vehicle wireless communication
and control, etc.
ACKNOWLEDGMENT
The authors would like to thank Semiconductor Manufactur-
ing International Corporation for the IC fabrication.
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[19] L. Smaini, C. Tinella, D. Helal, C. Stoecklin, L. Chabert, C. Devaucelle,
R. Cattenoz, N. Rinaldi, and D. Belot, “Single-chip CMOS pulse gen-
erator for UWB systems,” IEEE J. Solid-State Circuits, vol. 41, no. 7,
pp. 1551–1561, Jul. 2006.
Bo Qin received the B.S. degree in electrical en-
gineering from Xi’an Jiaotong University, Xi’an,
China, and the Ph.D. degree in microelectronics from
Tsinghua University, Beijing, China, in 2004 and
2009, respectively.
He has been with Citruscom Semiconductor,
Beijing, since 2009 as an IC Designer. His research
interests include ultrawideband system and circuit
design, RF circuit design, mixed-signal IC design,
ESD protection design for ICs, and SiP/MCM
subsystems. He has published several peer-reviewed
papers.
Xin Wang received the B.S. degree from Beijing
University of Posts and Telecommunications,
Beijing, China, in 2005, and the M.S. degree
from the Department of Electrical and Computer
Engineering, Illinois Institute of Technology,
Chicago, in 2007. He is currently working toward
the Ph.D. degree in the Department of Electrical
Engineering, University of California, Riverside.
His research interests are UWB RF transceiver and
mixed-signal IC design and on-chip ESD protection
design.
1562
Haolu Xie received the B.S. degree in electrical
engineering from Zhejiang University, Hangzhou,
China, in 2001, and the M.S. and Ph.D. degrees in
electrical engineering from Illinois Institute of Tech-
nology, Chicago, in 2004 and 2007, respectively.
He has been with Freescale Semiconductor,
Libertyville, IL, as an RF IC designer since 2007.
His current research interests include ESD protection
devices design, UWB, GSM, WCDMA, and LTE
transceiver RF/analog IC designs. He designed the
first SAW-less GSM/WCDMA/LTE transceiver IC in
CMOS in the world. He has published more than 20 IC design technical papers.
Lin Lin received the B.S. degree from the University
of Science and Technology Beijing, Beijing, China,
in 2002, and the M.S. degree in electrical engineering
from Illinois Institute of Technology, Chicago, in
2007. She is currently working toward the Ph.D.
degree in the Department of Electrical Engineering,
University of California, Riverside.
Her research interests are UWB RF front-end IC
and on-chip ESD protection designs.
He Tang received the B.S. degree from the Univer-
sity of Electronic Science and Technology of China,
Chengdu, China, in 2005, and the M.S. degree in
electrical engineering from Illinois Institute of Tech-
nology, Chicago, in 2007. He is currently working
toward the Ph.D. degree in the Department of Electri-
cal Engineering, University of California, Riverside.
His research interests are ADC and on-chip ESD
protection designs.
Albert Wang (M’95–SM’00–F’09) received the
B.S. degree in electrical engineering from Tsinghua
University, Beijing, China, in 1985, and the Ph.D.
degree in electrical engineering from the State Uni-
versity of New York at Buffalo, Buffalo, in 1996.
He was with National Semiconductor Corporation
before he joined Illinois Institute of Technology,
Chicago, as a Professor in 1998. Since 2007, he has
been a Professor of electrical and computer engi-
neering at the University of California, Riverside.
His research interests focus on AMS/RF ICs, on-chip
ESD Protection, IC CAD and Modeling, SoC, etc. He is the author of the book
On-Chip ESD Protection for Integrated Circuits (Kluwer, 2002) and more than
140 papers.
Dr. Wang received an NSF CAREER Award in 2002. He is an Editor of the
IEEE E LECTRON D EVICE L ETTERS and Guest Editor for IEEE J OURNAL OF
S OLID -S TATE C IRCUITS . He was an Associate Editor for the IEEE T RANSAC -
TIONS ON C IRCUITS AND S YSTEMS I and II and Guest Editor-in-Chief of the
IEEE T RANSACTIONS ON E LECTRON D EVICES. He is an IEEE Distinguished
Lecturer and the Vice President of the IEEE Electron Devices Society. He
serves on the ITRS Committee, IEEE EDS VLSI Technology and Circuits
Committee and IEEE CAS Analog Signal Processing Technical Committee.
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 57, NO. 5, MAY 2010
Hongyi Chen is a Professor in the Institute of
Microelectronics at Tsinghua University (IMETU),
Beijing, China. His research area is in the field of
semiconductors and integrated-circuit design with
a focus on ASIC and SOC design methodology,
library development, algorithm mapping to hardware
architecture and realization, VLSI-DSP and appli-
cations in multimedia signal processing and infor-
mation security fields, etc. He has published more
than 230 academic articles, copublished two books,
and cotranslated two textbooks. He is the holder of
13 U.S. patents. He was Director of IMETU.
Bin Zhao (S’90–M’94–SM’99–F’08) received the
B.S. degree in electrical engineering from Tsinghua
University, Beijing, China, in 1985, and the M.S. and
Ph.D. degrees from California Institute of Technol-
ogy, Pasadena, in 1988 and 1993, respectively.
He was with SEMATECH, Rockwell International
Corporation, Conexant Systems, and Skyworks So-
lutions. Currently, he is the Director of the Southern
California Development Center, Freescale Semicon-
ductor, Libertyville, IL. His research interests cover
VLSI technology as well as analog/mixed-signal/RF
IC design. He has published 200 papers and three book chapters, and he is the
holder of 45 issued U.S. patents.
Liwu (Lee) Yang received the B.S. degree from
National Tsinghua University, Hsinchu, Taiwan, in
1975, the M.S. degree from Stanford University,
Stanford, CA, in 1982, and the Ph.D. degree from
Yale University, New Haven, CT, in 1985.
He has career experience with Motorola, Ford
Microelectronics, GE, Lockheed Martin, and TRW.
He is currently with Semiconductor Manufacturing
International Corporation (SMIC), Shanghai, China.
His research interests cover semiconductors, IC tech-
nologies, RF ICs, etc. He has published more than
100 papers.
Dr. Yang is an SMIC Fellow.
Yumei Zhou received the B.S. degree in electri-
cal engineering from Tsinghua University, Beijing,
China, in 1985.
Since 1985, she has been with the Institute of
Microelectronics, Chinese Academy of Sciences,
Beijing, where she is currently the Deputy Director.
Her research interests are in the area of semiconduc-
tors and IC designs.