Introduction to compact

modeling
Sivakumar Mudanai
Intel Corp.
 Outline
• What is a compact model
• Why do we need compact models
• Requirements on a compact model
• Building the core long channel compact model
• Adding additional effects: short channel effects,
velocity saturation, noise, NQS
• Examples: Finfet, low effective mass material
modeling
• Good compact modeling practices
• Summary
2
 What is a compact model
• Computationally efficient description of the
terminal properties of a device as a
function of terminal voltages.
[{I}, {Q}] = f(Vg, Vd, Vs, Vb)

• The compact model is implemented inside

a circuit simulation engine.

3
 Two worlds
Technology / process IC design
development
• Design of an electrical
• The process of making
network consisting of
transistors, resistors,
transistors, resistances,
capacitors…etc, through
capacitances… etc, to
a series of complex
perform a specified task.
lithographical and
chemical processes. VDD

4
 Connecting the two worlds

Bridge=
Compact
Model

1.2E-04
Design engineers use
1.0E-04 those transistors build
8.0E-05 logic circuits that
IDS

6.0E-05 perform specific

4.0E-05
functions.
2.0E-05

0.0E+00
0 0.5 1 1.5
VDS

5
 Toy compact model: Examination
• The technology parameters are µ,
Linear region
Cox, Vth.
– These are extracted based on
experimental data.
– The technology parameter set is
what varies between technologies
making the compact model
applicable to different technologies. Saturation region
• The instance parameters L and W,
which are used by the designer.
• Applied bias Vgs, Vds, vbs

6
 A simplified view of circuit simulation

Simulation Engine:

Bias: Vgs, Vds Compact model

Matrix
Solver
[I], [Q]

Model File: Designer

• Simulation engine Input:
Tox = 20A;…
iteratively solves for
Vth = 300mV W=1 µm
Kirchoffs voltage and
µ = 100cm2/Vs L=100nm
current laws.
Design variables
Technology details

7
 Model file characterization
• Technology characterization
i.e. model files are extracted
by using data at multiple
widths and lengths based on

Width
median device data.
• Doping, oxide thickness,
mobility, series resistance etc
are fixed. Length
• Usually at two temperatures.

8
 Compact modeling requirements: I
• Process variations occur within
a die, between dies. 9

• A circuit must be designed so 8

that it “functions” even when 7

there is variation in the 6

transistor characteristics. 5

y
– Example: Gate length 4
variation. 3

• A compact model must 2

produce accurate result when 1
.0 2.5 5.0 7.5 10.0 12.5 15.0
its parameters are varied i.e. it
must be physically based x

Drive current variation across a

wafer.
9
Problems with unphysical
models

10
 Compact model requirement:II
Poly Poly
• Every foundry / company
makes MOSFET transistors N+ N+ N+ N+
that are different.
P P
• Even within a foundry or
Thin gate FET Thick gate FET
company there are different
types of transistors: thick gate
Poly Poly
oxide, thin gate oxide process
etc. N+ P- N+
• A compact model must not be P P
technology dependent.
Retrograde Pocket implanted

11
Compact model requirement: III
• Speed of evaluation.
– Circuit simulation speed and accuracy is critical for timely
design.
• Avoid expensive math functions.
• Avoid Internal nodes, if possible.
– If internal nodes are used, then let the circuit simulator solve for the quantities on
the node
• Reuse computed quantities and intermediate variables
• Model stability and convergence is important.
– continuous functions, no singularities
– Model evaluations that result in 0/0, but have a physical limit
need to be carefully dealt with.
– Consistent derivatives
• Accurate modeling of temperature dependence

12
 The compact model challenge

POISSON

STOCHASTIC LLG

Compact
SCHRODINGER model

Boltzmann Transport

13
Striking the right balance

Physical
scaling

Accuracy Computational speed

14
Developer skill requirements

Basics of digital
analog and RF
circuit design

Semiconductor
Physics

Process flow
understandin
g

15
 Types of compact models
• Macromodels
– Use of circuits to mimic device behavior.
• Table look up model
– {I,Q} = F(L, W, T, VD, VG, VD, VB, more)
– Limited value in early device evaluation.
• Physics based analytical model
– Computationally efficient
– Physically based
– Technology independent

16
 Building the core compact
model: Planar MOSFET
• MOSFETs are 2-D devices, hence need to solve for the potential
based on Poisson’s equation
∂ 2φ ∂ 2φ
∂y 2
+
∂x 2
= −
q
ε Si
( p − n + N d+ − N a− )

– Non – trivial to make approximations to formulate a compact model.

• Gradual channel approximation: In a long channel MOSFET the
variation of the lateral field (channel direction) is much less than the
variation in the perpendicular (to the channel) direction.
d 2φ
dy 2
= −
q
ε Si
(p − n + N d+ − N a− )
– Even in a long channel this assumption is true only upto the pinch off
point.
Identify ways to reduce PDEs to ODE
17
 Solving for φs
Vgb - Vfb
d 2φ
1-D potential equation
dy 2
= −
q
ε Si
(p − n + N d+ − N a− )
Boundary conditions:
1. Vgb – Vfb on the gate side
fs 2. Potential goes to zero at some deep in
the bulk.
Oxide

Gate Si Vfb is the gate voltage needed to restore flat-band

condition.

18
 fs Approaches
1.2
2φ f
1
• Pinned (BSIM3/4):
KT  N dop  0.8

φ s = 2φ f − Vbs φf = ln  0.6

q  ni 

fs
0.4 True
Simple, but valid only at onset of inversion 0.2 solution
0
-0.2
-2 -1 0 1 2
• Non-pinned Vgs

(V gb − V fb − φ s )
2
 Vbd − 2φ f
= Vt exp
  φs     − φs  
 exp  − 1 + Vt exp  − 1 + φ s γ =
2qε Si N A
γ2  Vt   Vt     Vt   Cox

Implicit equation, but valid from accumulation to depletion to inversion.

Solving implicit equation yields continuous solution valid over all

regions  no need for regional solution
19
Analytical modeling approaches
• Threshold voltage approach: BSIM3/4[1]
– Surface potential is constant or pinned above Vgs = “Vth”.
– Below Vth, the current is exponentially related to Vgs.
• Qi, inversion charge approach: EKV[2], BSIM6[1]
– The inversion charge in the channel is solved as the state
variable.
• Surface potential based: PSP[3], MOS11[4],
HiSim[5]
– Surface potential is the state variable.

20
 Basic MOSFET Model
Equations
Drift Diffusion

(1) Continuity:

(2) Gauss’ law

(3) Charge cons:

• Qinv is the integrated electron concentration along the depth
• Qbody is the integrated depletion and hole concentration along
the depth.
• Neither Qinv nor Qbody are simple analytic expressions.
21
 Compact modeling of Qinv and
Qbody
• Charge sheet model approximation Vgb - Vfb

[6]:
– Inversion charge is contained in a
negligibly thin sheet at the surface.
– Since the thickness is negligibly small, fs
the drop across that layer is also
negligibly small.

Oxide
Gate Si
– Hence, Qbody can be modeled similar to
depletion region in a diode

Look at “equivalent” systems for inspiration.

22
 Basic MOSFET Model
Equations
Drift Diffusion

(1) Continuity:

(2) Gauss’ law:

*
(3) Depletion approx.:
(4) Charge cons:

* Not accurate near flatband and accumulation

23
 Channel current
• Assuming mobility is a constant…

Analytical model for the channel current, but circuit simulators also
need compact analytical expressions for charge on all the terminals
to compute all the capacitances.

24
 Charge modeling
Gate node charge:

Bulk node charge:

• The charge associated with the drain and source node

is calculated by partitioning the total inversion charge.
– Trivial at vds = 0
– At non-zero drain bias the partitioning is achieved by the
use of Ward-Dutton partition scheme [7]

25
 Charge modeling
Drain node charge: Ward-Dutton partition scheme [7]

Ward-Dutton partition scheme is valid only for uniform doping and invalid
for drain field dependent mobility[9].

26
 Compact modeling of bulk
charge
• The terms with powers of 3/2
and ½ come from the bulk

Bulk charge
charge expression
• This is overcome by linearizing
the body charge about some
Surface potential
point in the channel

27
 Linearized inversion charge and
current

Where and

The base framework needs to be amenable to both Current and Charge

formulations.

28
 Gummel symmetry
Vb+Vx
• Transistors are designed to be
symmetric w.r.t to source and drain
D
interchange. B
Vg G
• Models, however, need to be
S
intentionally formulated to preserve
this symmetry.
• MOSFET model implementations in Vb-Vx
9
circuit simulators use this symmetry 8
assumption and flip the source and 7

dId/dvx
drain when VDS < 0. 6

• If the model is not symmetric then 5

there will be singularities in the 4

3
higher order derivatives at VDS = 0. -0.3 -0.1 0.1 0.3
Vx

29
 Distortion prediction
AC

DC VDS=0

DC

1st Harmonic

Current(dB)
ideal 3rd harmonic
3rd harmonic

Understand the usage and requirements Vin(dB)

of your designers.

30
 Other effects

Gate oxide
tunneling
Perfect Non-uniform
+++++++++
oxide channel doping
dielectric ----------
QM effects

uniform Band-to-band
channel doping Short-channel effects
tunneling

31
 Compact modeling of SCE
• Long channel assumption breaks down. 0.5

– Changes in vertical and lateral fields are 0.45

comparable. 0.4

Vth(V)
0.35
• Observations: 0.3

– Change in VT with length 0.25

0.2
– VT changes with drain bias, output 0 0.2 0.4 0.6 0.8 1
impedance decreases. Gate length(um)

• Approach: Quasi-2d analysis [14]

– Ignore the mobile charge contribution Long channel
approximation is
– Solve for the potentials distribution
not valid.
– Evaluate the change in barrier height in
going from long channel to short channel

32
 Modeling velocity saturation
• Traditionally a challenging
component of a compact model. µ eff E
v=
• Most commonly used   µ eff E  n 
1/ n

1 +   
expression was formulated by   Vsat  
Caughey-Thomas[18] Electrons : n = 2
• N=2 makes the current and Holes : n = 1
charge derivations iterative [19].
µ
– Most compact models use N=1 I ch = f (φss , φsd )ϕ ds
ϕ ds
1+ κ
L

33
Modeling velocity saturation
Solve for drain side surface potential φsdsat at the onset
of velocity saturation:
µ
I ch =
ϕ sat
f (φ ss , φ sat
sd )
ϕ ds = WQsat vsat
sat

1 + κ ds
L

Solve for sat

VDS = VDS at which φsd = φsdsat

sat
Limit VDS to VDS

34
 Gain compression and distortion
For a sinusoidal excitation at the gate

I Drain = A1vSin(ωt ) + A2 v 2 Sin 2 (ωt ) + A3v 3 Sin 3 (ωt ) + 

P1 DB

G1 = A1 + 3 A3v 2
• Gain is linear only 4

Pout
for a small signal
amplitude. ∂ n I drain
An ∝
∂Vgsn
Pin

35
 Mobility Modeling: field
dependence
• Higher order derivatives are determined
by the right modeling of gate field
dependent mobility [17]
• Mobility is not included in the integral
when the long channel current is derived.
• Hence typically an effective field [15,16] is
used to account for the gate bias
dependence.
– Can’t be empirical
– important for analog and RF. Source: [12]Takagi
et al, pp 398-401,
Higher order derivatives are important for analog and RF IEDM 1988
applications. The compact model is required to
reproduce this without having to explicitly fit to data.
36
 Mobility Modeling: gate field
dependence
1 1 1 1
Matthiessen’s Rule: = + + QB + ηQi
µ eff µCou µ ph µ SR Eeff =
ε Si
 Qi 
Scattering due to dopant atoms µCou = F 
N 
 dop 
Scattering lattice vibrations µ Ph = K Ph Eeff− m
Scattering due to surface roughness of
the Si-SiO2 interface.
µ SR = K SR E −n
eff

The exact equations vary depending on the compact model.

37
 Non-uniform doping
• Scaling requires the use of Halo Gate
implants for control of short
channel devices Source Low doped
centre: Nbulk
Drain

• Lateral non uniform doping Halo Doped

region: Nhalo
– Reverse short channel effect
– Long channel DIBL [20] Lateral
doping
– Degradation of output resistance
at longer lengths [21] Distance along the channel

• Vertical non-uniform doping

Vertical
– Back bias dependent doping doping

concentration.

Distance perpendicular to the channel

38
 Reverse short channel effect
Measured
• Effective / net doping increases as 0.4 This model

the channel length is reduced. Vds = 50 mV, Vbs = -1.2V

0.3
• Resulting in an increase in Vds = 50 mV, Vbs = 0V

Vt (V)
threshold voltage as the gate length 0.2

reduced.
0.1

Vds = 1.2V, Vbs = 0V

0
Doping concentration

0.01 0.1 1 10
L > 2 Lhalo L (µm)

Doping concentration
LHalo LHalo 2LHalo
NHalo Nnet
NHalo
L = 2 Lhalo
Nbulk Nnet

Distance along the channel Distance along the channel

39
 Reverse short channel effect
• In compact models RSCE is modeled by using
a length dependent doping concentration.
Halo
– Match the subthreshold current across the
3 transistors to extract an equivalent
doping [22].
Bulk
• The core quantities in a compact model are
calculated assuming a uniform doping.
– Charge and current need different doping!.
Halo
Doping concentration

LHalo LHalo
NHalo Electrical engineering based
concepts are also used to solve
Nbulk problems

L > 2 Lhalo
40
 Long channel DIBL modeling
• Even for long channel devices, sub-
threshold current increases with
increased drain bias.
• In subthreshold, current is
controlled by the conductance of
the region around the potential
peaks corresponding to the halos.
– Applying the drain bias can
effecting eliminate one of these
peaks by increasing the current by
a maximum of 2X! [20].

Use numerical simulations to thoroughly understand the

problem before compact model development.
41
 Non Quasi-Static Effects
• Quasi-static approaches assume that Gate
capacitors charge instantaneously in
Source Drain
response to a change in voltage.
• Quasi-static approximations only
work when the applied signal has a
long rise or fall time so that a steady-
state condition can be achieved with 1.E+00

Normalized Cgg (Ygg/(2PI*f)

the applied signal.

normalized to Cgg @ f=0)

1.E+00

• Non-quasi-static effects (NQS) 8.E-01

become important when the transient 6.E-01

signal is comparable or changes 4.E-01
Cgg* (L=.32)
Cgg* (L=.64)
faster than the carrier transit time Cgg* (L=1.3)
2.E-01
[23]. Cgg* (L=2)

0.E+00
1.E+08 1.E+09 1.E+10 1.E+11 1.E+12

Frequency

42
 Small-Signal NQS Compact
Model
• NQS effect can be Gate
reproduced by
segmenting the
channel. Source Drain

• Application of weighted   
residuals method [24] is ∂qi ∂   qi  ∂qi 
+ µ  − vt  =0
computationally ∂t ∂x  i
dq  ∂x 
 dφ s  
efficient.

Compact models are derived under quasi-static assumption.

However, some applications don’t meet this condition
43
 Noise Characteristics

Current through a resistor

• Different types of noise are
important at different
frequencies [25]
• Thermal noise and 1/f noise
models are common.
• Noise modeling and
characterization is critical for
analog and RF designs Time
(LNA)
– Digital designs suffer from
phase noise in PLLs
leading to jitter.

44
Noise sources and modeling
• Thermal Noise in a Resistor
– Origin: Thermal agitation of carriers.
– Frequency independent, white noise.
• Modeling
4 KT∆f
vn2 = 4 KTR∆f or in2 =
R

• Shot Noise, example: Gate current noise

– Origin: Granular nature of charge, randomness of
charge transport across a barrier.
– Associated with the flow of current. in2 = 2qI G ∆f
– White noise

45
 Noise sources and modeling
• Flicker Noise
– Origin: Charge trapping and de-
K
trapping i = ∆f
2
n
– Random Telegraph Signals (RTS) f
• Observable in small devices
• Example: Drain current fluctuations
as a function of time.
– 1/f noise
• Superposition of several RTS events,
leading to a 1/f distribution
• Modeled as fluctuations in number of
carriers and mobility fluctuations [26]

46
 Other models… Important
nonetheless
• Narrow width models
– The change in device characteristic with reducing width.
– The narrow width characteristics are a strong function of the
fabrication process and sequence.
– These models are typically more empirical in nature to
accommodate the application of the model to several processes.
• Stress effect: modeling based on layout

47
Core compact models for
recent devices

48
 Double gate FET

Drain
LG
LG

Source

Tox Gate Gate

Hsi
N+ N+

Wsi

Non-Planar Double gate

Planar

Improved SCE, reduced variability.

49
Poisson equation for a Double gate
MOSFET
∂ 2φ ∂ 2φ ∂ 2φ
z
y
+ +
∂x 2 ∂y 2 ∂z 2
= −
q
ε Si
(
p − n + N +
d − N −
a )
Gradual channel approximation
x

∂ 2φ ∂ 2φ
+
∂x 2 ∂y 2
= −
q
ε Si
(p − n + N +
d − N −
a )
Gate x
Variation in potential along the
Z direction is negligible.
z
d 2φ
Gate
dx 2
= −
q
ε Si
(p − n + N +
d − N −
a )

50
 Modeling Double gate transistors
Vgb - Vfb Vgb - Vfb • Symmetric double gate mosfet
– Need the solution for φs and
φc(implicitly) to evaluate the
device characteristics.
– In deriving the surface potential
Gate for a planar MOSFET φc is set to
Gate
φs φs zero.
φc – Typically these devices are
Oxide

doped low enough that the

Oxide

Si
d 2φ q Poisson’s equation can be solved
= n only for the electron contribution
Gate dx 2
ε Si (for an Ntype fet)[28]
– Compact modeling is more
involved for DG MOSFETs
especially if doping also needs to
be taken into account.

Gate

51
 Multi gate model
Gate Gate
Gate

Si

Gate
oxide
double gate finfet bulk finfet

Gate Gate Gate

trigate pi-gate omega gate

A Universal Core Model for Multiple-Gate Field-Effect Transistors,
[29] 52
 Low effective mass device
modeling
• Motivation: GATE
– Need higher drive currents oxide
without higher caps. Source Channel Drain
– Higher mobility oxide
– Low DOS means lower GATE
charge, but also low cap
2.0E-06
• For target supply voltages Without Wave function penetration
With wavefunction penetration
upto two subbands were 1.5E-06 Compact model
occupied.

CGG in F/cm^2
1.0E-06
• Need physical model that
correctly predicts the cap with 5.0E-07 tox = 1nm, mox=0.55, me=0.04
εox=3.9, εSe=13.6
changes in oxide and
semiconductor properties like 0.0E+00
0.0 0.5 1.0 1.5
Gate Voltage(V)
effective mass, barrier height
etc.
53
 Low effective mass device
modeling -I
• Solve for subband energies
assuming wave function
penetration into the oxide
and finite well height.
– Iterative solve, but gives
physical result with changes
in barrier height and oxide
thickness
• Use Fermi-Dirac(FD)
statistics to capture the DOS
effect.
– Will produce physical
scaling with changes in
effective mass
54
 Low effective mass device
modeling -II
• Integration of Poisson is
2.0E-06
non-trivial with FD.
– Treat the variation in φ as 1.5E-06

negligible in

CGG (F/cm2)
semiconductor 1.0E-06
W=7nm m=0.1
• Account for charge centroid W=10nm m=0.04
5.0E-07 W=5nm m=0.05
effects by assuming ideal W=7nm m = 0.04

wavefunction forms 0.0E+00

compact model

0.0 0.2 0.4 0.6 0.8 1.0

(sinusoids), then make Gate Voltage(V)

engineering
t se ε ox
approximations, [30], [31]. t eff
= t ox + 0.7
4 ε se
ox

55
 Modeling MRAM devices
• Most modeling is done using
MATLAB…
• Designers need a model inside
standard circuit simulation
engines.
• 0th order model:
– DC model with bias dependent
resistance with a “state” variable.
– Sufficient for biasing evaluation.
– Insufficient for timing read and
write V
Hysteresis cannot be handled by
table lookup model
56
Option 1: equivalent circuit models
• MRAM does not switch its state
instantly.
J • Vc is modeled using ideal
circuit elements such as
Resitances, capacitances,
Schmidt trigger etc [32]
τ
• For use in memory block design
– For timing simulations
– Need to know the delay in
switching for a given current
level.
R(Vc)

57
Option 2: Physical model

LLG
Thermal noise

58
 Good compact modeling
practices - I
• Use numerical simulations to fully understand the physics of
the problem.
– Should be able to explain the mechanism to a design engineer.
• Model needs to be true for asymptotic behaviors.
– Strong inversion limit, short channel limit, weak inversion limit.
• Let physics dictate the bias dependence (never let the data
dictate the bias dependence of a phenomenon).
– Helps to make sure that the model naturally transitions when the
effect is not significant
– No artificial smoothing needed to splice regions together.

59
 Good compact modeling
practices -II

(V gb − V fb − φs )
2
 Vbd − 2φ f
= Vt exp
 φ
 exp s
    −φ
 − 1 + Vt exp s
 
 − 1 + φs
γ2  Vt   Vt     Vt  

60
Good compact modeling
practices -III
0.6

0.5

VDS smooth
0.4
m=2
0.3
m=4
0.2 m=8

0.1

0
0 0.2 0.4 0.6 0.8 1 1.2
VDS

61
 Good compact modeling
practices -IV
• Validate, validate, validate
– Over all available data
– well beyond the range of application
– On as many circuits as available

62
 Summary
• Compact models act as bridge of information between the
manufacturing/Process team and the design teams
• Compact models are developed with very stringent requirements of
(1) accuracy, (2) speed and (3) predictability based on true physics.
• The core model is developed based on a long channel assumption.
All the additional complex behaviors due to short channel behavior
are added as corrections to the core model.
• Understanding the usage of the compact model in actual design is
important.
• NQS, Noise, higher order derivatives are all important irrespective of
the device

63
 Acknowledgements
• Ananda Roy
• Mark Stettler
• Rios Rafael
• Mark Lundstrom

64
 References
1) http://www-device.eecs.berkeley.edu/bsim/
2) http://legwww.epfl.ch/ekv/
3) http://pspmodel.asu.edu/
4) http://www.nxp.com/models/simkit/mos-models.html
5) M. Miura-Mattausch et al., IEEE TED, pp. 1994-2007, no.9, vol. 53, 2006.
6) J. R. Brews, Solid State Electron 1978, 21:345.
7) S. Y. Oh et al., IEEE TED Vol. 27, pp. 1571-1578, 1980.
8) C. C. McAndrew et al., IEEE TED Vol. 49, No. 1, pp. 72-81, January
2002.
9) A. S. Roy et al. , IEEE EDL, vol. 27, no. 8, 2006
10) P. Bendix et al., IEEE Custom Integrated Circuits conference, 2004.
11) T. L. Chen et al., IEE Electronic Letters, vol. 37, No. 12, 2001.
12) C. C. McAndrew, IEEE TED vol. 53, no. 9, 2006.
13) Xin Li et al., IEEE TED, vol. 56, no. 2, 2009
14) Z. H. Liu et al., IEEE TED, pp. 86-94, no. 1, vol. 40, 1993.
15) H. Shin et al., Solid-State Electron., vol. 34, no. 6, pp. 545–552,1991.
16) S. Takagi et al., IEDM Tech. Dig., p. 398-401, 1988
17) R. V. Langevelde et al., IEEE TED, vol. 44, no. 11, pp. 2044-2052, 1997 65
 References
19) N. Arora, et al., IEEE Trans. Electron Devices, ED-41, pp. 988-997, 1994.
20) A. S. Roy et al., IEEE TED vol. 58, no. 4, pp. 979- 984, 2011.
21) S. Mudanai et al., IEEE TED, pp. 2091, no. 9, vol. 53, 2006.
22) R. Rios, et al., IEDM Tech. Digest, pp.113-116, 2002.
23) C. Turchetti et al., IEEE Journal of Solid State Circuits, vol. SSC-21,no. 5,
1986.
24) H. Wang et al., IEEE TED, vol. 53, no.9, 2006
25) Scholten et al., IEEE TED, pp. 618-632, no. 3, vol. 20, 2003.
26) K. K. Hung et al., IEEE Trans. Electron Devices, vol. 37, pp. 654–665,
1990.
27) F. M. Klassen et al.,” Philips Res. Reps., vol 22, pp. 504-514, 1967.
28) Y. Taur et al., IEEE EDL, pp. 107-109, no.2, vol. 25, 2004.
29) J. P. Duarte, IEEE TED, vol. 60, no. 2, 2013.
30) S. Mudanai et al., IEEE TED, vol. 58, no.12, 2011.
31) A. S. Roy et al., IEEE TED, vol. 61, no. 2, 2014.
32) J. Harms et al., IEEE TED, vol. 57, no. 6, pp. 1425-1430, 2010
66
33) G. Panagopoulos et al., IEEE TED, vol. 60, no. 9, 2013.