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5 4 3 2 1

D D

Z61Ae SCHEMATIC V2.0


PAGE Content PAGE Content Notice
SYSTEM PAGE REF. POWER PAGE REF.
01 The Z61Ae project code is ?
4 DOTHAN CPU-1 43 POWER-ON SEQUENCE
5 DOTHAN CPU-2 44 VCORE ADP3205 02 CON17/CON19 are SMT Level(SMT Request);DC Jack J6 is DIP Level.
6 CPU CAP & THERMAL SENSOR 45 SYSTEM CN1/J1/U23 are changed to DIP Level(They will drop in SMT reflow ).
7 ALVISO: CPU 46 2.5V & 1.5V & 1.8V & 1.05V 03 J4 is changed to DIP.Due to it will broken in reflow.
8 ALVISO: DDR2 & DMI & PEG 47 1.5VA & DDR2
9 ALVISO: DDR2 48 PIC16C54/PWROK 04 Need to add ME and Power 59 level BOM in EE 60 BOM
10 ALVISO: POWER & Caps 49 BATCONN
11 ALVISO: GND & NCTF & Straps 50 CHARGER 05 Check FWH IC 05-001017122 in BOM.
12 DDR2 SO-DIMM_0 51 BATLOW/SD# Alviso U49 need to be changed to C1 version 02-010002640 (INTEL
06 ALVISO-GM SL8G2),second source is 02-010002610(C0 version)
13 DDR2 SO-DIMM_1 52 LOAD SWITCH
14 DDR2 ADDRESS TERMINATION 53 +5VLCM AMI BIOS LABEL P/N:15-135001010.
C
07 It need to add in P/R 59-MID BOM by ME.
C

15 LVDS & INVERTER CONNECTOR


16 CRT
08 J2 need to be unmounted at PR stage for ATS power test
17 ICH6M--SATA/LPC/IDE/PM (1)
18 ICH6M--PCI/DMIUSB/PCIE (2) R501(255 ohm) 10G213255013010 need to add second source 10-003412515.
09
19 ICH6M--PWR/GND(3)
20 ICH6M--PULL UP/STRAP (4) Add ACCL PCB Vendor 08-26ZA0020W???-->Need to create in SMT level.
10
21 CLOCK ICS954206 Need add other PCB vendors by document manager.
22 HDD & SWAP BAY CONN All 0.01uF/25V/X7R (P/N:11-034110320) need to add 11-034110323
11
23 USB PORTS into second source.
24 SUPER I/O LPC47N217 MINIPCI Connector (P/N:12-023511240) need to add 12-023521243
25 SCREW HOLE 12 into second source.
26 PORT BAR 3 All CHIP RES. ARRAY 10 OHM(0402) 8R16P (P/N:10-124901000) need
13
27 KBC 38857 to add 10-12490100A into second source.(ECR is NA12958)
28 SM BUS & POWER PORT
14 If delete debug card function,R876 and R628 mount 0 ohm.
29 LAN-RTL8101L
30 RJ45 / RJ11
15 If use another power
31 MINIPCI switch method.D30 unmount.
32 PCI CARDBUS R5C841
16 If use another power
B 33 PCI PCMCIA SOCKET A switch method.C616 B

34 PCI IEEE1394A & 3 IN1 CON mount 0.1uF/0402


35 FAN CONTROL
36 FWH BIOS/Bluetooth Conn.
37 AUDIO CODEC ALC880
38 AUDIO_AMP_MB (TPA0212)
39 MIC AMP & MDC Conn.
40 LED BOARD
41 TP CONN
42 DISCHARGE MOS/EMI

A A

Title : Z61AE PAGE REF.


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 1 of 57
5 4 3 2 1
5 4 3 2 1

Z61Ae: DOTHAN/ALVISO-GM BLOCK DIAGRAM


Main Battery is Li-ION 8 cells(4*2),16.8V(4.2V*4),4400mAH(2200mAH*2),65W(3.7V*4cell*4.4A) battery pack.
Second battery is Li-ION 6 cells(3*2),12.6V(4.2*3),3600mAH(1800mAH*2),40W(3.7V*3 cells*3.6A)battery pack.

BATTERY
2 TYPE SWITCH BOARD CON
CLOCK
D D
GEN. 3 X 2 & FUNCTION KEY LED
ICS954206 4 X 2 TOUCHPAD CONN
PAGE 21 PAGE 49
PAGE 40 PAGE 41

Dothan CPU
POWER
RESET SM_BUS
SCREW DISCHARGE

PAGE 4,5
478 uFCPGA
.... PAGE 6
CAP
SEQENCE
PAGE 43 PAGE 43 PAGE 28
HOLE
PAGE 25
CIRCUIT
PAGE 42
LVDS &
INV. HOST BUS
PAGE 15 AGTL
1.468V,133MHZ
CRT DDR2 400/533 FAN
DDR2 SDRAM 400/533MHz DDR RTC
PAGE 16
CONN
ALVISO
Intel 915GM C1 version
SODIMM X2
+1.8V
.... CAP/RES
CON.
+0.9VS PAGE 13,14 PAGE 35 PAGE 17
TO PORT BAR3 1257 uFCBGA
PAGE 12,13
CONN. SWITCH PAGE 7,8,9,10,11
(FOR CRT) H/W MONITOR
C PAGE 16
THERMAL C
PAGE 26 DMI x4 (ADT7463)
PAGE 35

USB X4 USB2.0 PCI_BUS 3.3V, 33MHz


TO PORT BAR3 PAGE 23 SATA BUS
CONN. PATA BUS ICH6-M AC LINK / ACZ
(FROM USB Intel ICH6 B2 version
PORT2) 3 IN 1 CARD CARDBUS LAN 10/100M MINI PCI
PAGE 26
609 BGA READER RICOH LAN-RTL8101L TYPE III
HDD SATA TO PATA SWAP BAY PAGE 17,18,19,20 (MMC/SD/ R5C841
Master SII3811CNU (HOT PAGE 31
TO BLUETOOTH MS-PRO) PAGE 32,33 PAGE 29
PAGE 22 PAGE 22 PLUG)
PAGE 22
(FROM USB PAGE 34
PORT5)
R1.1-S01 LPC, 33MHz RJ11 JACK
PAGE 31
LAN IO RJ45
Azalia
CARDBUS CONN
PAGE 30
ALC880-H 1 SLOT PAGE 30
1394 VCCA, VCCB
SUPER I/O KEYBOARD PAGE 37
SLOT VPPA, VPPB
CONTROLLER PAGE 34 PAGE 33 SWITCH
LPC47N217 M3885XHP AMI 4MB FLASH AUDIO AMP MDC CONN.
B
PAGE 24 PAGE 27
FWH TPA0212 PAGE 26
B

PAGE 38 PAGE 39
PAGE 36
VCORE
PAGE 44 TO PORT BAR3
TO PORT BAR3 INTERNAL
CONN.
SYSTEM CONN. KEYBOARD SPDIF
(FOR LAN)
PAGE 45 (FOR LPT) PAGE 38 PAGE 26
PAGE 26 PAGE 27
1.5V,1.8V,
MIC AMP
1.05V,2.5V PAGE 46 MIC IN
NJM2100
PAGE 39 PAGE 38
CHARGE
PAGE 50

PIC16C54
BATCON PAGE 48,49

BATLOW/SD# PORT BAR III part number is 90-N6W1P1010


PAGE 51,53

LOAD Switch CON2 PIN1 CON1 PIN1

PAGE 52 PIN2 PIN2


A A
+0.9VS
PAGE 47
PORT BAR 3
DC IN (19V TOP VIEW
DC,3.42A,65W)
PAGE 53
CON5 CON4 CON3
CN2 CN3 J1
Title : BLOCK DIAGRAM
CRT USB USB RJ45 LPT DCIN ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 2 of 57
5 4 3 2 1
5 4 3 2 1

***********GPIO setting is not final in this page.*********


***********Please reference Z61Ae GPIO setting document.*********

D
IDSEL# REQ/GNT# Interrupts PC/PCI
Azalia : PCI_INTB# D

PCI Device
USB 0,1 : PCI_INTA#
Chipset (Host to PCI) (AD30 internal) n/a USB 2,3 : PCI_INTD#
Mini_PCI AD18 3 B,D USB 4,5 : PCI_INTC#
LAN-RTL8101L AD16 0 C
CardBus AD17 1 B
1394 AD17 1 A SMBUS ADDRESS : CLK = 1101001x ( D2 )
3 IN 1 1 C DDR_SODIMM0 = 1010010x ( A4 )
DDR_SODIMM1 = 1010000x ( A0 )

ICH6M_GPIO Use As Signal Name Power M38857_GPIO USE_AS SIGNAL_NAME


GPI 00 GPI KBDDT0 P23 GPO M38857_GPIO USE_AS SIGNAL_NAME
GPI 01 GPI KBDDT1
GPI 02 GPI N/A (PIRQE#) P22 GPO BAT_LEARN P27 GPO SCROLLOCK#
GPI 03 GPI N/A (PIRQF#) P21 GPO BAT_SEL P26 GPO NUM_LED#
GPI 04 GPI N/A (PIRQG#)
GPI 05 GPI N/A (PIRQH#) P20 GPO KBCRSM P25 GPO CAP_LED#
GPI 06 GPI BMBUSY# P42 GPO WATCHDOG P24 GPO SET_PCIRSTNS#
C
GPI 07 GPI C

GPI 08 GPI EXT_SMI#_3A P43 GPI CHG_FULL_OC P41 GPO EMAIL_LED#


GPI 09 GPI N/A (USB_OC#4) P44 GPO KBDCPURST_3Q P40 GPO KBC_EXTSMI
GPI 10 GPI N/A (USB_OC#5)
GPI 11 GPI LID_ICH_3A P45 GPO KBC_GA20
GPI 12 GPI KBDSCI_3 P46 GPO KBSCI_3Q R5C593_GPIO USE_AS SIGNAL_NAME
GPI 13 GPI BAT1_LLOW#_ICH6
GPI 14 GPI BAT2_LLOW#_ICH6 P47 GPI PM_CLKRUN# IRQ3 GPO
GPI 15 GPI P50 GPO BAT_LOW#_KBC IRQ4 GPO
GPO 16 GPO
GPO 17 GPO P51 GPO XIDE_EN#_3 IRQ5 GPO
GPO 19 BLINK P52 GPO BAYDOCK_IN# IRQ7 GPO
GPO 21 GPO BACK_OFF#
GPO 23 GPO FWH_WP# P53 GPO BT_ON
GPIO24 GPO CB_SD# P54 GPI BAY_RST
GPIO25 GPO IHZ_ICH6
GPI 26 GPI P55 GPI BAT1_IN#_OC
GPIO27 GPI PCB_VID0 P56 GPO 47N217_GPIO USE_AS SIGNAL_NAME
GPIO28 GPI PCB_VID1
B B
GPI 29 GPI PCB_VID2 P57 GPO ADJ_BL GPI23 GPI
GPI 30 GPI P67 GPI BAT2_IN#_OC GPI40 GPI PID_0
GPI 31 GPI ACIN_OC_3
GPIO33 GPO P66 GPI DISTP# GPI41 GPI PID_1
GPIO34 GPO OP_SD# P65 GPI MARATHON_# GPI42 GPI
GPI 40 GPI PCB_VID3
GPI 41 GPI BATSEL_2P P64 GPI ACIN_OC GPI43 GPI
GPO 48 GPO P63 GPI LID_ICH#_3 GPI44 GPI BAY_IN0
GPO 49 GPO N/A (CPUPWRGD)
P62 GPI 802_ON GPI45 GPI BAY_IN1

P61 GPI INTERNET# GPI46 GPO

P60 GPI EMAIL# GPI47 GPO

P76 GPIO SMD_BAT

P77 GPIO SMC_BAT

A A

Title : Schematic information


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 3 of 57
5 4 3 2 1
5 4 3 2 1

CPU Socket P/N : 12-046004791


H_D#[63:0] <7>
U48B U48A
<7> H_A#[16:3]
H_A#16 AA2 N2 H_D#15 C25 Y25 H_D#47
A[16]# ADS# H_ADS# <7> D[15]# D[47]#
H_A#15 Y3 A10 H_D#14 E23 AA26 H_D#46
D A[15]# PRDY# H_BPM#4 <6> D[14]# D[46]# D
H_A#14 AA3 B10 H_D#13 B23 Y23 H_D#45
A[14]# PREQ# H_BPM#5 <6> D[13]# D[45]#
H_A#13 U1 H_D#12 C26 V26 H_D#44
H_A#12 A[13]# H_D#11 D[12]# D[44]# H_D#43
Y1 A[12]# BNR# L1 H_BNR# <7> E24 D[11]# D[43]# U25
H_A#11 Y4 J3 H_D#10 D24 V24 H_D#42
A[11]# BPRI# H_BPRI# <7> D[10]# D[42]#

ADDRESS GROUP 0
H_A#10 H_D#9 H_D#41

DATA GROUP 0

2
W2 A[10]# B24 D[9]# D[41]# U26
H_A#9 T4 H_D#8 C20 AA23 H_D#40

DATA GROUP
H_A#8 A[9]# H_D#7 D[8]# D[40]# H_D#39
W1 A[8]# DBR# A7 H_DBRESET# <6,17> B20 D[7]# D[39]# R23
H_A#7 V2 H_D#6 A21 R26 H_D#38
H_A#6 A[7]# H_D#5 D[6]# D[38]# H_D#37
R3 A[6]# B26 D[5]# D[37]# R24
H_A#5 V3 H_D#4 A24 V23 H_D#36
H_A#4 A[5]# H_D#3 D[4]# D[36]# H_D#35
U4 A[4]# DEFER# L4 H_DEFER# <7> B21 D[3]# D[35]# U23
H_A#3 P4 H2 H_D#2 A22 T25 H_D#34
A[3]# DRDY# H_DRDY# <7> D[2]# D[34]#
U3 M2 H_D#1 A25 AA24 H_D#33
<7> H_ADSTB#0 ADSTB[0]# DBSY# H_DBSY# <7> D[1]# D[33]#
H_REQ#4 T1 H_D#0 A19 Y26 H_D#32
H_REQ#3 REQ[4]# D[0]# D[32]#
P1 REQ[3]# <7> H_DINV#0 D25 DINV[0]# DINV[2]# T24 H_DINV#2 <7>
H_REQ#2 T2 C23 W25
REQ[2]# <7> H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 <7>
H_REQ#1 P3 C22 W24
REQ[1]# <7> H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 <7>
H_REQ#0 R2 REQ[0]# H_D#31 H_D#63
<7> H_REQ#[4:0] N4 H_BR0# <7> K25 AF26

CONTROL
BR0# +VCCP H_D#30 D[31]# D[63]# H_D#62
N25 D[30]# D[62]# AF22
H_D#29 H26 AF25 H_D#61
H_IERR# H_D#28 D[29]# D[61]# H_D#60
IERR# A4 2 1 M25 D[28]# D[60]# AD21
OD R468 56Ohm H_D#27 N24 AE21 H_D#59
<7> H_A#[31:17] D[27]# D[59]#
H_A#31 AF1 H_D#26 L26 AF20 H_D#58
A[31]# D[26]# D[58]#

3
H_A#30 H_D#25 H_D#57

DATA GROUP 1
AE1 A[30]# INIT# B5 H_INIT# <17> +VCCP J25 D[25]# D[57]# AD24
H_A#29 H_D#24 H_D#56

DATA GROUP
AF3 A[29]# M23 D[24]# D[56]# AF23
H_A#28 AD6 H_D#23 J23 AE22 H_D#55
A[28]# D[23]# D[55]#

ADDRESS GROUP 1
H_A#27 AE2 J2 H_D#22 G24 AD23 H_D#54
A[27]# LOCK# H_LOCK# <7> D[22]# D[54]#

2
H_A#26 AD5 H_D#21 F25 AC25 H_D#53
H_A#25 A[26]# R228 H_D#20 D[21]# D[53]# H_D#52
AC6 A[25]# H24 D[20]# D[52]# AC22
H_A#24 AB4 H_D#19 M26 AC20 H_D#51
H_A#23 A[24]# 54.9Ohm H_D#18 D[19]# D[51]# H_D#50
AD2 A[23]# L23 D[18]# D[50]# AB24
H_A#22 AE4 1% /* H_D#17 G25 AC23 H_D#49

1
H_A#21 A[22]# H_D#16 D[17]# D[49]# H_D#48
AD3 A[21]# RESET# B11 H_CPURST# <7> H23 D[16]# D[48]# AB25
H_A#20 AC3 L2 H_RS#2 J26 AD20
A[20]# RS[2]# <7> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <7>
H_A#19 AC7 K1 H_RS#1 K24 AE24
A[19]# RS[1]# <7> H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 <7>
H_A#18 AC4 H1 H_RS#0 L24 AE25
A[18]# RS[0]# <7> H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 <7>
C H_A#17 AF4 Reserve for ITP C
A[17]# H_RS#[2:0] <7>
AE5 M3 Place resistance close ITP SOCKET479P
<7> H_ADSTB#1 ADSTB[1]# TRDY# H_TRDY# <7>
R1.1-S30
HIT# K3 H_HIT# <7>
<7> DPWR# C19 DPWR# HITM# K4 H_HITM# <7>
+1.8VS_VCCA
SOCKET479P
+1.8VS_PROC
P/N = 12-046004791

1
T68 T73 C167 C170 C264 C262 C168 C169 C263 C260
10UF/10V 10UF/10V 10UF/10V 10UF/10V

2
0.01UF 0.01UF 0.01UF 0.01UF
1

U48C
B15 /* /* /*
<21> CLK_CPU_BCLK BCLK[0]
B14 A-2 STEPPING 1.8V/1.5V
HOSTCLK

<21> CLK_CPU_BCLK# BCLK[1]


R4552 1 49.9Ohm 1% A16 AB1 H_COMP3 B STEPPING 1.5V only
R4562 ITP_CLK[0] COMP[3] H_COMP2
1 49.9Ohm 1% A15 ITP_CLK[1] COMP[2] AB2 Place near CPU pin
P26 H_COMP1
COMP[1] H_COMP0
<17> H_A20M# C2 A20M# COMP[0] P25
OD D3
<17> H_FERR# FERR#
Layout note:
LEGACY CPU

<17> H_IGNNE# A3 IGNNE#


<17> H_DPSLP# B7 DPSLP# BPM[3]# C9 H_BPM#0 <6> COMP0 and COMP2 need to be Zo=27.4ohm traces.
<7,17> H_CPUSLP# A6 SLP# BPM[2]# A9 H_BPM#1 <6> Best estimate is 18mil wide trace for outer
D1 B8 +VCCP H_COMP3 2 1
<17> H_INTR LINT0 BPM[1]# H_BPM#2 <6> layers and
D4 C8 H_COMP2 R2322 1 54.9Ohm 1%
<17> H_NMI LINT1 BPM[0]# H_BPM#3 <6>
B4 H_COMP1 R2332 1 27.4Ohm 1% 14mil if on internal layer. See RDDP of
<17> H_SMI# SMI#
2
C6 H_COMP0 R1431 2 54.9Ohm 1% Banias.
<17> H_STPCLK# STPCLK# R144 R142 27.4Ohm 1%
OD Traces should be shorter than 0.5". Refer to
<17> H_PWRGD E4 PWRGOOD GTLREF[3] AC1 1
G1 T100 1KOhm latest CS layout
<44> VR_VID[5:0] GTLREF[2] H_DPRSTP# <17>
VR_VID5 H4 E26 1
1

VR_VID4 VID[5] GTLREF[1] T238 GTLREF0


G4 VID[4] GTLREF[0] AD26 COMP1, COMP3 should be routed as Zo=55ohm
1.05V OUTPUT VR_VID3 G3 Z0=55 ohm < 0.5''
VID[3] traces shorter than 0.5"
2

VR_VID2 F3 R145
B
VR_VID1 VID[2] B
F2 VID[1]
VCCA layout: T / S : VR_VID0 E2 C5 2 1
VID[0] TEST1 R4661
100 mil / 25 mil TEST2 F23 2 1KOhm /* 2KOhm
R147 1KOhm /* 1%
MISC

+1.8VS_VCCA AC26 VCCA[3]


N1 R1.1-S29
120mA VCCA[2] TDI <6>

S 2
+1.8VS_VCCA +1.8VS_PROC

D
B1 VCCA[1] TCK A13 TCK <6>

3
+1.8VS_PROC F26 C12 2 1
VCCA[0] TDI +VCCP
R461 150Ohm

G
TDO A12 TDO <6>

1
B18 C11 Q16 SI2302DS
<35> H_THERMDA THERMDA TMS TMS <6> R148
<35> H_THERMDC A18
C17
THERMDC TRST# B13 2
R459
1
680Ohm 2 1
/* For FSB(400/533)
<6> H_THRMTRIP_S# THERMTRIP# TRST# <6> +5V +3VS +3VS
H_PROCHOT_S# B17 PROCHOT# VCCSENSE 10KOhm 3 U20
VCCSENSE AE7 2 1 D
E1 R184 54.9Ohm Q18 R146
<44> PM_PSI# RSVD5

2
C16 1% /* 2 1 1 5 VCCA_FB
<21> CPU_BSEL0 RSVD4 /* 1 <17,21,29,32,37,40,43,48,52> PM_SUSB# SHDN# SET
1 C3 R139 2
RSVD3 VCCA_1.8_EN# <21> GND
T264 C14 G 100KOhm 0Ohm 3 4 +1.8VS_PROC
<21> CPU_BSEL1 RSVD2 S 2 IN OUT
1 AF7 2N7002 /*
RSVD1

1
T87 1 B2 AF6 VSSSENSE 2 1 C172

1
RSVD0 VSSSENSE

2
T263 R201 54.9Ohm G913C C166
A-STEP B-STEP A

1
SOCKET479P 1% /* /* C171 0.1UF Vset=1.25

2
FSB BSEL1 BSEL0 BSEL0 CPU_F_SEL Vout=1.25*(1+A/B)
0.01UF R136

2
+1.8VS_VCCA 20KOhm 2200P
400 0 N/A 1

1
VCCA_FB
533 0 N/A 0 100 OTHER

2
4

2
R137
SW2 If CPU_F_SEL=LOW B
R138
+VCCP +VCCP +VCCP
SWITCH_4P -->+1.8VS_PROC=1.81V 100KOhm

1
CPU_F_SEL=OPEN 80.6KOhm

1
CPU_F_SEL
-->+1.8VS_PROC=1.5V
1

2
2

R464 R453 R234 DOTHAN 3


D
A 133 A
Reserve for ITP R838 Q17
56Ohm 56Ohm 200Ohm +1.8VS_PROC 1
/* <21> VCCA_1.8_EN 1 2
G 2N7002
1

H_BPM#5 0Ohm 2 S /*
H_PROCHOT_S# OD R235 Switch default is PIN3 and PIN4 ON. /*
H_PWRGD 2 1 H_PWRGD_ITP <6> For FSB 400 CPU.
1KOhm /* R2.0-S11
Reserve for ITP SW2 switch TO PIN1 "pin1 & 4 OPEN"==>133MHz/1.5V"VCCA0
SW2 switch TO PIN4 "pin1 & 4 SHORT"==>100MHz/1.8V"VCCA0 Title : DOTHAN CPU (1)
ASUSTECH CO.,LTD. Engineer: Sam Wang
SW2 switch TO PIN2 "pin2 & 3 OPEN"==>DOTHAN 533
Size Project Name Rev
SW2 switch TO PIN3 "pin2 & 3 SHORT"=>CELERON/BANIAS/DOTHAN400 C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 4 of 57
5 4 3 2 1
5 4 3 2 1

D D

+VCCP +VCORE

AD25
AD22
AD19
AD17
AD15
AD13
AD11
AE26
AE23
AE20
AE18
AE16
AE14
AE12
AE10
AF24
AF21
AF19
AF17
AF15
AF13
AF11
U48D

AD9
AD7
AD4
AD1
AE8
AE6
AE3
AF9
AF5
AF2
VCC1 D6
W4 D8 U48E
VCCQ[1] VCC2
P23 D18 A2 AC24

VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VCCQ[0] VCC3 VSS1 VSS160
VCC4 D20 A5 VSS2 VSS159 AC21
VCC5 D22 A8 VSS3 VSS158 AC18
VCC6 E5 A11 VSS4 VSS157 AC16
VCC7 E7
E9
A14
A17
VSS5 VSS156 AC14
AC12
MOBILE DOTHAN VID TABLE
VCC8 VSS6 VSS155
D10 VCCP1 VCC9 E17 A20 VSS7 VSS154 AC10
D12 VCCP2 VCC10 E19 A23 VSS8 VSS153 AC8
D14 VCCP3 VCC11 E21 A26 VSS9 VSS152 AC5 VID[5..0] Voltage VID[5..0] Voltage
D16 VCCP4 VCC12 F6 B3 VSS10 VSS151 AC2
E11 VCCP5 VCC13 F8 B6 VSS11 VSS150 AB26
E13 VCCP6 VCC14 F18 B9 VSS12 VSS149 AB23
E15 VCCP7 VCC15 F20 B12 VSS13 VSS148 AB21 000000 1.708V 100000 1.196V
F10 F22 B16 AB19
F12
VCCP8 VCC16
G5 B19
VSS14 VSS147
AB17 000001 1.692V 100001 1.180V
VCCP9 VCC17 VSS15 VSS146
F14 VCCP10 VCC18 G21 B22 VSS16 VSS145 AB15 000010 1.676V 100010 1.164V
F16 H6 B25 AB13
K6
VCCP11 VCC19
H22 C1
VSS17 VSS144
AB11 000011 1.660V 100011 1.148V
VCCP12 VCC20 VSS18 VSS143
L5 J5 C4 AB9 000100 1.644V 100100 1.132V
L21
M6
M22
VCCP13
VCCP14
VCCP15
VCCP16
VCCVCC21
VCC22
VCC23
VCC24
J21
K22
U5
C7
C10
C13
VSS19
VSS20
VSS21
VSS22
VSS142
VSS141
VSS140
VSS139
AB7
AB5
AB3
000101
000110
1.628V
1.612V
100101
100110
1.116V
1.100V
N5 V6 C15 AA25
N21
VCCP17 VCC25
V22 C18
VSS23 VSS138
AA22 000111 1.596V 100111 1.084V
VCCP18 VCC26 VSS24 VSS137
P6 VCCP19 VCC27 W5 C21 VSS25 VSS136 AA20 001000 1.580V 101000 1.068V
P22 W21 C24 AA18
R5
VCCP20 VCC28
Y6 D2
VSS26 VSS135
AA16 001001 1.564V 101001 1.052V
C
R21
T6
T22
VCCP21
VCCP22
VCCP23
VCCP24
VCC29
VCC30
VCC31
VCC32
Y22
AA5
AA7
D5
D7
D9
VSS27
VSS28
VSS29
VSS30
GND VSS134
VSS133
VSS132
VSS131
AA14
AA12
AA10
001010
001011
1.548V
1.532V
101010
101011
1.036V
1.020V
C

U21 VCCP25 VCC33 AA9 D11 VSS31 VSS130 AA8 001100 1.516V 101100 1.004V
AA11 D13 AA6
VCC34
AA13 D15
VSS32 VSS129
AA4 001101 1.500V 101101 0.988V
VCC35 VSS33 VSS128
VCC36 AA15 D17 VSS34 VSS127 AA1 001110 1.484V 101110 0.972V
AA17 D19 Y24
VCC37
AA19 D21
VSS35 VSS126
Y21 001111 1.468V 101111 0.956V
VCC38 VSS36 VSS125
VCC39 AA21 D23 VSS37 VSS124 Y5 010000 1.452V 110000 0.940V
AB6 D26 Y2
VCC40
AB8 E3
VSS38 VSS123
W26 010001 1.436V 110001 0.924V
VCC41 VSS39 VSS122
VCC42 AB10 E6 VSS40 VSS121 W23 010010 1.420V 110010 0.908V
AB12 E8 W22
VCC43
AB14 E10
VSS41 VSS120
W6 010011 1.404V 110011 0.892V
VCC44 VSS42 VSS119
VCC45 AB16 E12 VSS43 VSS118 W3 010100 1.388V 110100 0.876V
AB18 E14 V25
VCC46
AB20 E16
VSS44 VSS117
V21 010101 1.372V 110101 0.860V
VCC47 VSS45 VSS116
VCC48 AB22 E18 VSS46 VSS115 V5 010110 1.356V 110110 0.844V
AC9 E20 V4
VCC49
AC11 E22
VSS47 VSS114
V1 010111 1.340V 110111 0.828V
VCC50 VSS48 VSS113
VCC51 AC13 E25 VSS49 VSS112 U24 011000 1.324V 111000 0.812V
AC15 F1 U22
VCC52
AC17 F4
VSS50 VSS111
U6 011001 1.308V 111001 0.796V
VCC53 VSS51 VSS110
VCC54 AC19 F5 VSS52 VSS109 U2 011010 1.292V 111010 0.780V
AD8 F7 T26
VCC55
AD10 F9
VSS53 VSS108
T23 011011 1.276V 111011 0.764V
VCC56 VSS54 VSS107
VCC57 AD12 F11 VSS55 VSS106 T21 011100 1.260V 111100 0.748V
AD14 F13 T5
VCC58
AD16 F15
VSS56 VSS105
T3 011101 1.244V 111101 0.732V
VCC59 VSS57 VSS104
AD18 F17 R25 011110 1.228V 111110 0.716V
VCC72
VCC71
VCC70
VCC69
VCC68
VCC67
VCC66
VCC65
VCC64
VCC63
VCC62
VCC61

VCC60 VSS58 VSS103


F19 R22
F21
VSS59 VSS102
R6 011111 1.212V 111111 0.700V
VSS60 VSS101
F24 VSS61 VSS100 R4
SOCKET479P G2 R1
AF18
AF16
AF14
AF12
AF10
AF8
AE19
AE17
AE15
AE13
AE11
AE9

VSS62 VSS99
G6 VSS63 VSS98 P24
G22 P21
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS64 VSS97

B B
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
SOCKET479P

A A

Title : DOTHAN CPU (2)


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 5 of 57
5 4 3 2 1
5 4 3 2 1

VCORE 10uF/10V * 35
220uF/2V *4
VCCP 0.1uF * 10 for CPU
150uF * 1 for CPU
+VCORE 10uF is 0.1uF * 10 for Alviso
150uF * 2 for Alviso
D
/6.3V/0805/X5R as 4.7uF * 1 for Alviso
D

M7V R2.0 2.2uF


0.47uF
* 1 for Alviso
* 2 for Alviso on A6 B2 G1 V1
0.22uF * 2 for Alviso on A6 B2 G1 V1
+VCORE +VCCP
Decoupling guide from INTEL
R1.1-S32 27A for 1.8G

2
R462 R460 R465
1

1
C202 C198 C229 C214 C215 C216 C184 C181 C180 C199
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 39.2Ohm 54.9Ohm 1KOhm
2

1
1% 1% /* /*
1 CLK_ITP_BCLK <21>
T270 1 CLK_ITP_BCLK# <21>
T269 1 H_CPURST#_ITP <7>
T111 1 H_DBRESET# <4,17>
T74 1 TDO <4>
1

1
T251 1 TRST# <4>
C228 C196 C195 C197 C462 C231 C466 C482 C192 C232 T248 1 TDI <4>
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF T253 1 TMS <4>
2

2
T254
1

1
C211 C212 C227 C220 C218 C219 C190 C191 C188 C478
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
2

2
<4> H_BPM#5 1
1 T257
<4> H_BPM#4
T256
C
<4> H_BPM#3 1 C
1

1
+ + + 1 T83
<4> H_BPM#2
1

CE9 CE11 CE20 T82


C230 1
220UF/2V 220UF/2V 220UF/2V <4> H_BPM#1
10UF 1 T258
<4> H_BPM#0
2

2
/* T79
<4> H_PWRGD_ITP 1
1 T124
<8> CTL_CLK
1 T277
<8> CTL_DATA
T273

2
<4> TCK 1
R498 R497 T245

1
+2.5VS 2.2KOhm 2.2KOhm R458
/* /*

1
27.4Ohm
1%

2
+VCCP NEAR CPU NEAR CPU
PIN W4 PIN P23
R1.1-S32 2.5A for 1.8G
1

+
1

1
CE19 C469 C465 C479 C472 C463 C474 C471

150U/4.0V 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF


2

2
1

C464 C480 C481

0.1UF 0.1UF 0.1UF


2

H_THRMTRIP# <17>

B +VCCP B

+VCCP
DOTHAN VID TABLE

2
R445

2
CPU HFM LFM C3/C4
FREQ. VOLTAGE 1.6G 1.4G 1.2G 1G 0.6G R127 330Ohm
C457

1
75Ohm
1 2
1.8G 1.308V 1.292V 1.260V 1.228V 1.196V 0.844V 0.748V Q90

1 B
1
0.1UF

S 2
1.7G R452 2 1 0Ohm Q84

D
<4> H_THRMTRIP_S# OTP_RESET# <43,48>

3
C
2
E

3
R457 2 1 0Ohm 2N7002

G
<8> GMCH_THRMTRIP# PMBS3904

1
/*

<8,17,18,22,24,27,36> BUF_PLT_RST#

A A

Title : CPU CAP/THERMAL


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 6 of 57
5 4 3 2 1
5 4 3 2 1

U49 Original P/N is 02-010002600(ALVISO-PM)


Z61AE R1.0 use C0 version part number is 02-010002610 (ALVISO GM)
U49 need to change to new C1 version 02-010002640 (INTEL ALVISO-GM SL8G2)
D
H_XRCOMP R1.1 has changed it in symbol. D

2
R478

24.9Ohm
1%

1
<4> H_D#[0..63]
H_A#[3..31] <4>
U49D
H_D#0 E4 G9 H_A#3
H_D#1 HD0# HA3# H_A#4
E1 HD1# HA4# C9
H_D#2 F4 E9 H_A#5
H_D#3 HD2# HA5# H_A#6
H7 HD3# HA6# B7
+VCCP H_D#4 E2 A10 H_A#7
H_D#5 HD4# HA7# H_A#8
F1 HD5# HA8# F9
H_D#6 E3 D8 H_A#9
H_D#7 HD6# HA9# H_A#10
D3 HD7# HA10# B10

2
H_D#8 K7 E10 H_A#11
R479 H_D#9 HD8# HA11# H_A#12
F2 HD9# HA12# G10
H_D#10 J7 D9 H_A#13
54.9Ohm H_D#11 HD10# HA13# H_A#14
J8 HD11# HA14# E11
1% H_D#12 H6 F10 H_A#15

1
H_D#13 HD12# HA15# H_A#16
F3 HD13# HA16# G11
H_XSCOMP H_D#14 K8 G13 H_A#17
H_D#15 HD14# HA17# H_A#18
H5 HD15# HA18# C10
H_D#16 H1 C11 H_A#19
H_D#17 HD16# HA19# H_A#20
H2 HD17# HA20# D11
H_D#18 K5 C12 H_A#21
+VCCP H_D#19 HD18# HA21# H_A#22
K6 HD19# HA22# B13
H_D#20 J4 A12 H_A#23
H_D#21 HD20# HA23# H_A#24
G3 HD21# HA24# F12
2

H_D#22 H3 G12 H_A#25


R474 H_D#23 HD22# HA25# H_A#26 +VCCP
J1 HD23# HA26# E12
H_D#24 L5 C13 H_A#27
221Ohm H_D#25 HD24# HA27# H_A#28
K4 HD25# HA28# B11
1% H_D#26 J5 D13 H_A#29
1

HD26# HA29#

2
C H_D#27 P7 A13 H_A#30 C
H_XSWING H_D#28 HD27# HA30# H_A#31 R216
L7 HD28# HA31# F13
H_D#29 J3 HD29#
2

R473 H_D#30 P5 F8 H_ADS# 100Ohm


HD30# HADS# H_ADS# <4>
1

H_D#31 L3 B9 H_ADSTB#0 1%
H_ADSTB#0 <4>

1
HD31# HADSTB0#
1

100Ohm C491 C494 H_D#32 U7 E13 H_ADSTB#1


HD32# HADSTB1# H_ADSTB#1 <4>
1% 10UF/10V H_D#33 V6 J11
2

0.1UF H_D#34 HD33# HVREF H_BNR#


R6 A5 H_BNR# <4>
1

H_D#35 HD34# HBNR# H_BPRI#


R5 HD35# HBPR# D5 H_BPRI# <4>

2
/* H_D#36 P3 E7 H_BR0#
HD36# HBREQ0# H_BR0# <4>

1
H_D#37 T8 H10 H_CPURST# R217 C257
HD37# HCPURST# H_CPURST# <4>
H_D#38 R7 HD38#

HOST
H_D#39 R8 2 1 200Ohm 0.1UF
H_CPURST#_ITP <6>

2
H_YRCOMP H_D#40 HD39# R225 22.6Ohm 1%
U8

1
H_D#41 HD40# 1% /*
R4 HD41# HCLKINN AB1 CLK_MCH_BCLK# <21>
H_D#42 T4 AB2
HD42# HCLKINP CLK_MCH_BCLK <21>
2

H_D#43 T5
R472 H_D#44 HD43#
R1 HD44# HDBSY# C6 H_DBSY# <4>
H_D#45 T3 E6
HD45# HDEFER# H_DEFER# <4>
24.9Ohm H_D#46 V8 H8 H_DINV#0
HD46# HDINV0# H_DINV#0 <4>
1% H_D#47 U6 K3 H_DINV#1
H_DINV#1 <4>
1

H_D#48 HD47# HDINV1# H_DINV#2


W6 HD48# HDINV2# T7 H_DINV#2 <4>
H_D#49 U3 U5 H_DINV#3
HD49# HDINV3# H_DINV#3 <4>
H_D#50 V5 G6
HD50# HDPWR# DPWR# <4>
H_D#51 W8 F7
HD51# HDRDY# H_DRDY# <4>
H_D#52 W7 G4 H_DSTBN#0
HD52# HDSTBN0# H_DSTBN#0 <4>
H_D#53 U2 K1 H_DSTBN#1
HD53# HDSTBN1# H_DSTBN#1 <4>
H_D#54 U1 R3 H_DSTBN#2
HD54# HDSTBN2# H_DSTBN#2 <4>
+VCCP H_D#55 Y5 V3 H_DSTBN#3
HD55# HDSTBN3# H_DSTBN#3 <4>
H_D#56 Y2 G5 H_DSTBP#0
HD56# HDSTBP0# H_DSTBP#0 <4>
H_D#57 V4 K2 H_DSTBP#1
HD57# HDSTBP1# H_DSTBP#1 <4>
H_D#58 Y7 R2 H_DSTBP#2
HD58# HDSTBP2# H_DSTBP#2 <4>
2

H_D#59 W1 W4 H_DSTBP#3
HD59# HDSTBP3# H_DSTBP#3 <4>
R476 H_D#60 W3 F6 TP_H_EDRDY# 1 T121
H_D#61 HD60# HEDRDY#
Y3 HD61# HHIT# D4 H_HIT# <4>
54.9Ohm H_D#62 Y6 D6
HD62# HHITM# H_HITM# <4>
1% H_D#63 W2 B3 H_LOCK# <4>
1

HD63# HLOCK# TP_H_PCREQ# T274


B HPCREQ# A11 1 B
H_YSCOMP H_XRCOMP C1 A7 H_REQ#0
HXRCOMP HREQ0# H_REQ#0 <4>
H_XSCOMP C2 D7 H_REQ#1
HXSCOMP HREQ1# H_REQ#1 <4>
H_XSWING D1 B8 H_REQ#2
HXSWING HREQ2# H_REQ#2 <4>
H_YRCOMP T1 C7 H_REQ#3
HYRCOMP HREQ3# H_REQ#3 <4>
H_YSCOMP L1 A8 H_REQ#4
HYSCOMP HREQ4# H_REQ#4 <4>
+VCCP H_YSWING P1 A4 H_RS#0
HYSWING HRS0# H_RS#0 <4>
C5 H_RS#1
HRS1# H_RS#1 <4>
B4 H_RS#2
HRS2# H_RS#2 <4>
2

HCPUSLP# G8 H_CPUSLP# <4,17>


R470 B5
HTRDY# H_TRDY# <4>
221Ohm ALVISO_BGA1257
1% 02-010002640
1

H_YSWING
2

R471 C489
C490
100Ohm 10UF/10V 0.1UF
2

1%
1

/*

A A

Title : Alviso--CPU (1)


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 7 of 57
5 4 3 2 1
5 4 3 2 1

SDVOCRTL_DATA Int PD Disable TV_OUT :


SDVO SMbus have TVDAC A/B/C and TVIRTN A/B/C and TV_REFSET
internal pull down
0 : No SDVO device
and VCCA_TVDAC A/B/C ... ( ALL TV POWER )
D 1 : SDVO device present connect to GND D

U49F
T106 1 SDVO_SMDATA H24 D36

MISC
<18> DMI_TXN[0..3] SDVOCTRL_DATA EXP_COMPI
U49A T103 1 SDVO_SMCLK H25 D34
DMI_TXN0 SDVOCTRL_CLK EXP_ICOMPO
AA31 DMIRXN0 CFG0 G16 2 1 +2.5VS <21> CLK_MCH_3GPLL# AB29 GCLKN
DMI_TXN1 AB35 H13 R229 1KOhm AC29 E30
DMIRXN1 CFG1 MCH_SEL1 <21><21> CLK_MCH_3GPLL GCLKP EXP_RXN0
DMI_TXN2 AC31 G14 F34
DMIRXN2 CFG2 MCH_SEL0 <21> EXP_RXN1
DMI_TXN3 AD35 F16 CFG3 1 T116 G30
<18> DMI_TXP[0..3] DMIRXN3 CFG3 EXP_RXN2
F15 CFG4 1 T120 TVDAC_A_GM A15 H34
DMI_TXP0 CFG4 CFG5 TVDAC_B_GM TVDAC_A EXP_RXN3
Y31 DMIRXP0 CFG5 G15 CFG5 <11> C16 TVDAC_B EXP_RXN4 J30
DMI_TXP1 AA35 E16 CFG6 TVDAC_C_GM A17 K34
DMIRXP1 CFG6 CFG6 <11> TVDAC_C EXP_RXN5
DMI_TXP2 AB31 D17 CFG7 TV_REFSET_GM J18 L30

TV
DMIRXP2 CFG7 CFG7 <11> TV_REFSET EXP_RXN6
DMI_TXP3 AC35 J16 CFG8 1 T123 TVDAC_A_GM# B15 M34
<18> DMI_RXN[0..3] DMIRXP3 CFG8 TV_IRTNA EXP_RXN7
D15 CFG9 TVDAC_B_GM# B16 N30
CFG9 CFG9 <11> TV_IRTNB EXP_RXN8
DMI_RXN0 AA33 E15 CFG10 1 T137 TVDAC_C_GM# B17 P34
DMI_RXN1 DMITXN0 CFG10 CFG11 T135 TV_IRTNC EXP_RXN9
AB37 DMITXN1 CFG11 D14 1 EXP_RXN10 R30

DMI
DMI_RXN2 AC33 E14 CFG12 1 T125 T34
DMI_RXN3 DMITXN2 CFG12 CFG13 T115 EXP_RXN11
<18> DMI_RXP[0..3] AD37 DMITXN3 CFG13 H12 1 EXP_RXN12 U30
C14 CFG14 1 T140 V34
DMI_RXP0 CFG14 CFG15 T138 EXP_RXN13
DMI_RXP1
Y33 DMITXP0 CFG15 H15
CFG16
1 EXP_RXN14 W30 PCI-E signals can be left NC, If unused.
AA37 J15 T122 E24 Y34
DMITXP1 CFG16 CFG16 <11> <16> DDC2BC_GM DDCCLK EXP_RXN15
DMI_RXP2 AB33 H14 CFG17 1 E23
DMITXP2 CFG17 <16> DDC2BD_GM DDCDATA
DMI_RXP3 AC37 G22 CFG18 TPC28t DAC_B_GM E21 D30

VGA
DMITXP3 CFG18 CFG18 <11> <16> DAC_B_GM BLUE EXP_RXP0
G23 CFG19 DAC_B_GM# D21 E34
CFG19 CFG19 <11> BLUE# EXP_RXP1
AM33 D23 CFG20 1 T132 DAC_G_GM C20 F30
<13> DCLK0 SM_CK0 CFG20 <16> DAC_G_GM GREEN EXP_RXP2
AL1 G25 1 T126 DAC_G_GM# B20 G34
<13> DCLK1 SM_CK1 RSVD21 GREEN# EXP_RXP3

PCI-EXPRESS GRAPHICS
T63 TP_SMCK2 T109 DAC_R_GM
1 AE11 SM_CK2 RSVD22 G24 1 <16> DAC_R_GM A19 RED EXP_RXP4 H30
AJ34 J17 1 T131 DAC_R_GM# B19 J34
<12> DCLK3 SM_CK3 RSVD23 RED# EXP_RXP5
AF6 A31 1 T142 VSYNC_GM H21 K30
T70 <12> DCLK4 SM_CK4 RSVD24 VSYNC EXP_RXP6
1 TP_SMCK5 AC10 A30 1 T146 HSYNC_GM G21 L34
SM_CK5 RSVD25 T133 REFSET_GM HSYNC EXP_RXP7
RSVD26 D26 1 J20 REFSET EXP_RXP8 M30
AN33 D25 1 T136 N34
<13> DCLK0# SM_CK0# RSVD27 EXP_RXP9
<13> DCLK1# AK1 P30

DDR MUXING
T69 TP_SMCK#2 SM_CK1# EXP_RXP10
1 AE10 SM_CK2# EXP_RXP11 R34
<12> DCLK3# AJ33 SM_CK3# EXP_RXP12 T30
<12> DCLK4# AF5 SM_CK4# EXP_RXP13 U34
T72 TP_SMCK#5
C 1 AD10 SM_CK5# <15> ADJ_BL_GM E25 LBKLT_CRTL EXP_RXP14 V30 C
<15> LCD_BACKEN_GM F25 LBKLT_EN EXP_RXP15 W34
<13,14> SCKE0 AP21 SM_CKE0 <6> CTL_CLK C23 LCTLA_CLK
<13,14> SCKE1 AM21 SM_CKE1 <6> CTL_DATA C22 LCTLB_DATA EXP_TXN0 E32
AH21 J23 DDCCLK_GM F23 F36
<12,14> SCKE2 SM_CKE2 BM_BUSY# PM_BMBUSY# <17> <15> DDCCLK_GM LDDC_CLK EXP_TXN1
AK21 J21 PM_EXTTS#0 DDCDATA_GM F22 G32
PM
<12,14> SCKE3 SM_CKE3 EXT_TS0# <15> DDCDATA_GM LDDC_DATA EXP_TXN2
Layout Note: EXT_TS1# H22 PM_EXTTS#1 <15> LCD_VDD_EN_GM F26 LVDD_EN EXP_TXN3 H36
AN16 F5 1 T143 L_IBG C33 J32
Route as short <13,14> SCS0# SM_CS0# THRMTRIP# GMCH_THRMTRIP# <6> LIBG EXP_TXN4
AM14 AD30 MCH_PWROK 1 T141 L_LVBG C31 K36

LVDS
<13,14> SCS1# SM_CS1# PWROK LVBG EXP_TXN5
as possible. AH15 AE29 2 1 1 T150 L_LVREFH F28 L32
<12,14> SCS2# SM_CS2# RSTIN# BUF_PLT_RST# <6,17,18,22,24,27,36> LVREFH EXP_TXN6
AG16 R173 100Ohm 1 T145 L_LVREFL F27 M36
<12,14> SCS3# SM_CS3# LVREFL EXP_TXN7
A24 1% N32
CLK

M_OCDCOMP0 DREF_CLKN DREFCLK# <21> EXP_TXN8


AF22 SM_OCDCOMP0 DREF_CLKP A23 DREFCLK <21> <15> LVDS_CLKAM_GM B30 LACLKN EXP_TXN9 P36
M_OCDCOMP1 AF16 C37 B29 R32
SM_OCDCOMP1 DREF_SSCLKN DREFSSCLK# <21> <15> LVDS_CLKAP_GM LACLKP EXP_TXN10
DREF_SSCLKP D37 DREFSSCLK <21> <15> LVDS_CLKBM_GM C25 LBCLKN EXP_TXN11 T36
2

<13,14> ODT0 AP14 SM_ODT0 <15> LVDS_CLKBP_GM C24 LBCLKP EXP_TXN12 U32
2

R677 R678 AL15 AP37 TP_NC1 1 T47 V36


<13,14> ODT1 SM_ODT1 NC1 EXP_TXN13
40.2Ohm 40.2Ohm AM11 AN37 TP_NC2 1 T49 B34 W32
<12,14> ODT2 SM_ODT2 NC2 <15> LVDS_YA0M_GM LADATAN0 EXP_TXN14
1% 1% AN10 AP36 TP_NC3 1 T48 B33 Y36
<12,14> ODT3 SM_ODT3 NC3 <15> LVDS_YA1M_GM LADATAN1 EXP_TXN15
AP2 TP_NC4 1 T51 B32
<15> LVDS_YA2M_GM
1

M_RCOMPN NC4 TP_NC5 1 T54 LADATAN2


NC

AK10 AP1 D32


1

M_RCOMPP SMRCOMPN NC5 TP_NC6 1 T53 EXP_TXP0


AK11 SMRCOMPP NC6 AN1 EXP_TXP1 E36
VTT_REF AF37 B1 TP_NC7 1 T268 A34 F32
SMVREF0 NC7 <15> LVDS_YA0P_GM LADATAP0 EXP_TXP2
AD1 A2 TP_NC8 1 T275 A33 G36
SMVREF1 NC8 <15> LVDS_YA1P_GM LADATAP1 EXP_TXP3
SMXSLEW AE27 B37 TP_NC9 1 T267 B31 H32
SMXSLEWIN NC9 <15> LVDS_YA2P_GM LADATAP2 EXP_TXP4
Zo=55 ohm AE28 A36 TP_NC101 T272 J36
+1.8V SMYSLEW SMXSLEWOUT NC10 TP_NC111 T271 EXP_TXP5
AF9 SMYSLEWIN NC11 A37 EXP_TXP6 K32
Zo=55 ohm AF10 C29 L36
SMYSLEWOUT <15> LVDS_YB0M_GM LBDATAN0 EXP_TXP7
R150 D28 M32
<15> LVDS_YB1M_GM LBDATAN1 EXP_TXP8
1 2 ALVISO_BGA1257 C27 N36
<15> LVDS_YB2M_GM LBDATAN2 EXP_TXP9
2

02-010002640 P32
80.6Ohm R158 EXP_TXP10
EXP_TXP11 R36
1% 80.6Ohm C28 T32
<15> LVDS_YB0P_GM LBDATAP0 EXP_TXP12
1% <15> LVDS_YB1P_GM D27 LBDATAP1 EXP_TXP13 U36
<15> LVDS_YB2P_GM C26 V32
1

LBDATAP2 EXP_TXP14
EXP_TXP15 W36

ALVISO_BGA1257
B B
02-010002640

+5V MCH_PWROK 1 2 VCC_MCH_VRPWRGD <44,48>


R202 1 2 0Ohm /* +2.5VS
+1.8V ICH6_PWROK <17,43>
R203 0Ohm
1

C724
2

R725 DAC_B_GM R246 1 2 150Ohm DAC_B_GM#


2

0.1UF RN50A PM_EXTTS#0


1 10KOhm 2
VTT_REF DAC_G_GM R252 1 2 150Ohm DAC_G_GM# 3 4 RN50B PM_EXTTS#1
10KOhm 10KOhm
T340 5 6 RN50C DDCDATA_GM
10KOhm
5

U65 DAC_R_GM R253 1 2 150Ohm DAC_R_GM# 7 8 RN50D DDCCLK_GM


10KOhm
1

1 V+
1

+
4 REFSET_GM R501 1 2 255Ohm
2

3 10G213255013010 R499
-
1

C725 R726 V- 255 ohm main source is 10G213255013010. 1 2 L_IBG


1

LMV321
Second source is 10-003412515.
2

0.01UF C726 1.5KOhm 1%


2

10KOhm
1

1UF/10V
R222
1 2 VSYNC_GM
<16> DAC_VSYNC_GM
R227
1 39Ohm 2 HSYNC_GM
<16> DAC_HSYNC_GM
39Ohm

A A

Title : Z61Ae
ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 8 of 57
5 4 3 2 1
5 4 3 2 1

D D

<13> M_A_DQ[0..63] <12> M_B_DQ[0..63]


U49B
M_A_DQ0 AG35 AK15 U49C
SADQ0 SA_BS0# M_A_BS#0 <13,14>
M_A_DQ1 AH35 AK16 M_B_DQ0 AE31
SADQ1 SA_BS1# M_A_BS#1 <13,14> SBDQ0
M_A_DQ2 AL35 AL21 M_B_DQ1 AE32 AJ15
SADQ2 SA_BS2# M_A_BS#2 <13,14> SBDQ1 SB_BS0# M_B_BS#0 <12,14>
M_A_DQ3 AL37 M_B_DQ2 AG32 AG17
SADQ3 M_A_DM[0..7] <13> SBDQ2 SB_BS1# M_B_BS#1 <12,14>
M_A_DQ4 AH36 AJ37 M_A_DM0 M_B_DQ3 AG36 AG21
SADQ4 SA_DM0 SBDQ3 SB_BS2# M_B_BS#2 <12,14>
M_A_DQ5 AJ35 AP35 M_A_DM1 M_B_DQ4 AE34
SADQ5 SA_DM1 SBDQ4 M_B_DM[0..7] <12>
M_A_DQ6 AK37 AL29 M_A_DM2 M_B_DQ5 AE33 AF32 M_B_DM0
M_A_DQ7 AL34 SADQ6 SA_DM2 M_A_DM3 M_B_DQ6 AF31 SBDQ5 SB_DM0 M_B_DM1
SADQ7 SA_DM3 AP24 SBDQ6 SB_DM1 AK34
M_A_DQ8 AM36 AP9 M_A_DM4 M_B_DQ7 AF30 AK27 M_B_DM2
M_A_DQ9 AN35 SADQ8 SA_DM4 M_A_DM5 M_B_DQ8 AH33 SBDQ7 SB_DM2 M_B_DM3
SADQ9 SA_DM5 AP4 SBDQ8 SB_DM3 AK24
M_A_DQ10 AP32 AJ2 M_A_DM6 M_B_DQ9 AH32 AJ10 M_B_DM4
M_A_DQ11 AM31 SADQ10 SA_DM6 M_A_DM7 M_B_DQ10 AK31 SBDQ9 SB_DM4 M_B_DM5
SADQ11 SA_DM7 AD3 SBDQ10 SB_DM5 AK5
M_A_DQ12 AM34 M_B_DQ11 AG30 AE7 M_B_DM6
SADQ12 M_A_DQS[0..7] <13> SBDQ11 SB_DM6
M_A_DQ13 AM35 AK36 M_A_DQS0 M_B_DQ12 AG34 AB7 M_B_DM7
M_A_DQ14 AL32 SADQ13 SA_DQS0 M_A_DQS1 M_B_DQ13 AG33 SBDQ12 SB_DM7
SADQ14 SA_DQS1 AP33 SBDQ13 M_B_DQS[0..7] <12>

DDR SYSTEM MEMORY A


C M_A_DQ15 AM32 AN29 M_A_DQS2 M_B_DQ14 AH31 AF34 M_B_DQS0 C
M_A_DQ16 AN31 SADQ15 SA_DQS2 M_A_DQS3 M_B_DQ15 AJ31 SBDQ14 SB_DQS0 M_B_DQS1
SADQ16 SA_DQS3 AP23 SBDQ15 SB_DQS1 AK32
M_A_DQ17 AP31 AM8 M_A_DQS4 M_B_DQ16 AK30 AJ28 M_B_DQS2
M_A_DQ18 AN28 SADQ17 SA_DQS4 M_A_DQS5 M_B_DQ17 AJ30 SBDQ16 SB_DQS2 M_B_DQS3
SADQ18 SA_DQS5 AM4 SBDQ17 SB_DQS3 AK23
M_A_DQ19 AP28 AJ1 M_A_DQS6 M_B_DQ18 AH29 AM10 M_B_DQS4
SADQ19 SA_DQS6 SBDQ18 SB_DQS4

DDR SYSTEM MEMORY B


M_A_DQ20 AL30 AE5 M_A_DQS7 M_B_DQ19 AH28 AH6 M_B_DQS5
M_A_DQ21 AM30 SADQ20 SA_DQS7 M_B_DQ20 AK29 SBDQ19 SB_DQS5 M_B_DQS6
SADQ21 M_A_DQS#[0..7] <13> SBDQ20 SB_DQS6 AF8
M_A_DQ22 AM28 AK35 M_A_DQS#0 M_B_DQ21 AH30 AB4 M_B_DQS7
M_A_DQ23 AL28 SADQ22 SA_DQS0# M_A_DQS#1 M_B_DQ22 AH27 SBDQ21 SB_DQS7
SADQ23 SA_DQS1# AP34 SBDQ22 M_B_DQS#[0..7] <12>
M_A_DQ24 AP27 AN30 M_A_DQS#2 M_B_DQ23 AG28 AF35 M_B_DQS#0
M_A_DQ25 AM27 SADQ24 SA_DQS2# M_A_DQS#3 M_B_DQ24 AF24 SBDQ23 SB_DQS0# M_B_DQS#1
SADQ25 SA_DQS3# AN23 SBDQ24 SB_DQS1# AK33
M_A_DQ26 AM23 AN8 M_A_DQS#4 M_B_DQ25 AG23 AK28 M_B_DQS#2
M_A_DQ27 AM22 SADQ26 SA_DQS4# M_A_DQS#5 M_B_DQ26 AJ22 SBDQ25 SB_DQS2# M_B_DQS#3
SADQ27 SA_DQS5# AM5 SBDQ26 SB_DQS3# AJ23
M_A_DQ28 AL23 AH1 M_A_DQS#6 M_B_DQ27 AK22 AL10 M_B_DQS#4
M_A_DQ29 AM24 SADQ28 SA_DQS6# M_A_DQS#7 M_B_DQ28 AH24 SBDQ27 SB_DQS4# M_B_DQS#5
SADQ29 SA_DQS7# AE4 SBDQ28 SB_DQS5# AH7
M_A_DQ30 AN22 M_B_DQ29 AH23 AF7 M_B_DQS#6
SADQ30 M_A_A[0..13] <13,14> SBDQ29 SB_DQS6#
M_A_DQ31 AP22 AL17 M_A_A0 M_B_DQ30 AG22 AB5 M_B_DQS#7
M_A_DQ32 AM9 SADQ31 SA_MA0 M_A_A1 M_B_DQ31 AJ21 SBDQ30 SB_DQS7#
SADQ32 SA_MA1 AP17 SBDQ31 M_B_A[0..13] <12,14>
M_A_DQ33 AL9 AP18 M_A_A2 M_B_DQ32 AG10 AH17 M_B_A0
M_A_DQ34 AL6 SADQ33 SA_MA2 M_A_A3 M_B_DQ33 AG9 SBDQ32 SB_MA0 M_B_A1
SADQ34 SA_MA3 AM17 SBDQ33 SB_MA1 AK17
M_A_DQ35 AP7 AN18 M_A_A4 M_B_DQ34 AG8 AH18 M_B_A2
M_A_DQ36 AP11 SADQ35 SA_MA4 M_A_A5 M_B_DQ35 AH8 SBDQ34 SB_MA2 M_B_A3
SADQ36 SA_MA5 AM18 SBDQ35 SB_MA3 AJ18
M_A_DQ37 AP10 AL19 M_A_A6 M_B_DQ36 AH11 AK18 M_B_A4
M_A_DQ38 AL7 SADQ37 SA_MA6 M_A_A7 M_B_DQ37 AH10 SBDQ36 SB_MA4 M_B_A5
SADQ38 SA_MA7 AP20 SBDQ37 SB_MA5 AJ19
M_A_DQ39 AM7 AM19 M_A_A8 M_B_DQ38 AJ9 AK19 M_B_A6
M_A_DQ40 AN5 SADQ39 SA_MA8 M_A_A9 M_B_DQ39 AK9 SBDQ38 SB_MA6 M_B_A7
SADQ40 SA_MA9 AL20 SBDQ39 SB_MA7 AH19
M_A_DQ41 AN6 AM16 M_A_A10 M_B_DQ40 AJ7 AJ20 M_B_A8
M_A_DQ42 AN3 SADQ41 SA_MA10 M_A_A11 M_B_DQ41 AK6 SBDQ40 SB_MA8 M_B_A9
SADQ42 SA_MA11 AN20 SBDQ41 SB_MA9 AH20
M_A_DQ43 AP3 AM20 M_A_A12 M_B_DQ42 AJ4 AJ16 M_B_A10
M_A_DQ44 AP6 SADQ43 SA_MA12 M_A_A13 M_B_DQ43 AH5 SBDQ42 SB_MA10 M_B_A11
SADQ44 SA_MA13 AM15 SBDQ43 SB_MA11 AG18
M_A_DQ45 AM6 M_B_DQ44 AK8 AG20 M_B_A12
M_A_DQ46 AL4 SADQ45 M_B_DQ45 AJ8 SBDQ44 SB_MA12 M_B_A13
SADQ46 SA_CAS# AN15 M_A_CAS# <13,14> SBDQ45 SB_MA13 AG15
M_A_DQ47 AM3 AP16 M_B_DQ46 AJ5
SADQ47 SA_RAS# M_A_RAS# <13,14> SBDQ46
M_A_DQ48 AK2 AF29 TP_MA_RCVENIN# T57 1 TPC28t M_B_DQ47 AK4 AH14
SADQ48 SA_RCVENIN# SBDQ47 SB_CAS# M_B_CAS# <12,14>
M_A_DQ49 AK3 AF28 TP_MA_RCVENOUT# T65 1 TPC28t M_B_DQ48 AG5 AK14
SADQ49 SA_RCVENOUT# SBDQ48 SB_RAS# M_B_RAS# <12,14>
M_A_DQ50 AG2 AP15 M_B_DQ49 AG4 AF15 TP_MB_RCVENIN# T60 1 TPC28t
SADQ50 SA_WE# M_A_WE# <13,14> SBDQ49 SB_RCVENIN#
M_A_DQ51 AG1 M_B_DQ50 AD8 AF14 TP_MB_RCVENOUT# T62 1 TPC28t
M_A_DQ52 AL3 SADQ51 M_B_DQ51 AD9 SBDQ50 SB_RCVENOUT#
B SADQ52 SBDQ51 SB_WE# AH16 M_B_WE# <12,14> B
M_A_DQ53 AM2 M_B_DQ52 AH4
M_A_DQ54 AH3 SADQ53 M_B_DQ53 AG6 SBDQ52
M_A_DQ55 AG3 SADQ54 M_B_DQ54 AE8 SBDQ53
M_A_DQ56 AF3 SADQ55 M_B_DQ55 AD7 SBDQ54
M_A_DQ57 AE3 SADQ56 M_B_DQ56 AC5 SBDQ55
M_A_DQ58 AD6 SADQ57 M_B_DQ57 AB8 SBDQ56
M_A_DQ59 AC4 SADQ58 M_B_DQ58 AB6 SBDQ57
M_A_DQ60 AF2 SADQ59 M_B_DQ59 AA8 SBDQ58
M_A_DQ61 AF1 SADQ60 M_B_DQ60 AC8 SBDQ59
M_A_DQ62 AD4 SADQ61 M_B_DQ61 AC7 SBDQ60
M_A_DQ63 AD5 SADQ62 M_B_DQ62 AA4 SBDQ61
SADQ63 M_B_DQ63 AA5 SBDQ62
SBDQ63
ALVISO_BGA1257
02-010002640 ALVISO_BGA1257
02-010002640

A A

Title : Alviso--DDR2 (3)


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 9 of 57
5 4 3 2 1
A
B
C
D

Int VGA
2 1

+2.5VS
R1.1-S18

C761

0.1UF
1
R857

4.3Ohm
2
/*

C762
2 1 2 1

5
5

R1.1-S32
R783
0Ohm

+1.5VS
2.2UF/16V

+1.5VS
C495
C496
2 1 1 2

1
0.1UF
0.1UF

1
+2.5VS_CRTDAC

L78
L37
2 1 2 1

2
2
+VCCP

C475
C492

120Ohm/100Mhz
0.1UF
0.1UF

120Ohm/100Mhz
CAP4
/*
1UF

1.05V
C759

2 1 1 2 VTT51 G1

+
+2.5VS
2 1 M1 CE13 2 1

VCCP_GMCH_CAP3
VCCP_GMCH_CAP2
VCCP_GMCH_CAP1

/*
VTT50

+1.5VS
VTT49 N1

0.1UF
C265
150U/4.0V
G37 VSSA_3GBG VTT48 V1

CE18
C233
+1.5VS_3GPLL
F37 B2 2 1

1
0.1UF
VCCA_3GBG VTT47
+

150U/4.0V
VTT46 M2
2 1 2 1 Y27 VCCA_3GPLL2 VTT45 N2 2 1

L36
Y28 VCCA_3GPLL1 VTT44 M3
Y29 N3

2
+1.5VS_PCIE
VCCA_3GPLL0 VTT43

C248
C267

M4

0.1UF
VTT42

C239
0.01UF

2 1 J37 VCC3G6 VTT41 N4 2 1


L37 M5

120Ohm/100Mhz
10UF/10V
VCC3G5 VTT40
N37 VCC3G4 VTT39 N5
R37 A6
C243

VCC3G3 VTT38

C241
2 1 U37 M6 2 1
0.1UF

VCC3G2 VTT37
W37 N6

10UF/10V
VCC3G1 VTT36
AE37 VCC3G0 VTT35 M7 2 1

+1.5VS_DDRDLL

C205
C261

N7

0.1UF
0.1UF

VTT34
2 1 AF18 VCCA_SM3 VTT33 M8

+
AF19 VCCA_SM2 VTT32 N8
C240

AP19 VCCA_SM1 VTT31 J9


AF20 L9
10UF/10V

VCCA_SM0 VTT30

CE10
VTT29 M9

150U/4.0V
N9

+2.5VS
VTT28
R1.1-S18

A27 VCCTX_LVDS2 VTT27 P9


A28 VCCTX_LVDS1 VTT26 R9
2 1 B28 VCCTX_LVDS0 VTT25 U9
W9

4
4

VTT24
AE1 VCCSM64 VTT23 Y9
AM1 J10

C499
VCCSM63 VTT22
AP8 K10

0.1UF
VCCSM62 VTT21
+2.5VS_CRTDAC

2 1 AB9 VCCSM61 VTT20 M10


+2.5VS

2 1 AB10 N10

+1.5VS
VCCSM60 VTT19
AB11 VCCSM59 VTT18 P10 2 1
AC11 R10

C237
VCCSM58 VTT17
AD11 T10

0.1UF
VCCSM57 VTT16

C503
C760

2 1 AE12 U10 2 1
0.1UF

VCCSM56 VTT15
+
R1.1-S18

V1.8_DDR_CAP3
V1.8_DDR_CAP4
V1.8_DDR_CAP6
2 1 AF12 V10

10UF/10V
VCCSM55 VTT14
AG12 VCCSM54 VTT13 W10

C207
AH12 K11

0.1UF
VCCSM53 VTT12
CE17
VCC_SYNC

R785
R784

AJ12 L11
1
1

VCCSM52 VTT11

C224
150U/4.0V

2 1 AK12 VCCSM51 VTT10 M11

A25, B25, B26


shorted internally. AL12 N11

10UF/10V
VCCSM50 VTT9

Place near pin


AM12 VCCSM49 VTT8 P11 2 1

C458
AN12 R11

0.1UF
VCCSM48 VTT7
Note: All VCCSM pins

AP12 T11
2
2

/*

VCCSM47 VTT6
+1.5VS_MPLL

C476

2 1 AE13 U11
0Ohm
0.1UF

VCCSM46 VTT5
AF13 V11
0Ohm

VCCSM45 VTT4
AG13 VCCSM44 VTT3 W11

10UF/10V
C186
C449
AH13 K12
1

0.1UF AJ13
VCCSM43 VTT2
J13
VCCSM42 VTT1
2 1 AK13 VCCSM41 VTT0 K13
VCC_SYNC
L76

AL13 VCCSM40
AM13 H20
2

VCCSM39 VCC_SYNC
VCCA_CRTDAC

C453
AN13

0.1UF
VCCSM38
2 1 AP13 VCCSM37
2 1 2 1 AE14 G19
120Ohm/100Mhz

VCCSM36 VSSA_CRTDAC
AE15 E19

+2.5VS
VCCSM35 VCCA_CRTDAC1
AE16 VCCSM34 VCCA_CRTDAC0 F19
C454

2 1 AE17
0.1UF

C500
VCCSM33
+
+1.8V

AE18 AA2

0.1UF
VCCSM32 VCCA_MPLL
2 1 AE19 VCCSM31 VCCA_HPLL AA1
2 1 AE20 VCCSM30 VCCA_DPLLB C35
AE21 B23
CE28

VCCSM29 VCCA_DPLLA
C461

AE22 AC1
0.1UF

VCCSM28 VCCH_MPLL0

C501
150U/4.0V

AE23 VCCSM27 VCCH_MPLL1 AC2 2 1


+

0.01UF
2 1 AE24 VCCSM26 2 1
+

AE25 K17

3
3

shorted internally.

VCCSM25 VCC48
AF25 VCCSM24 VCC47 K18
CE12

C459

AG25 T18
0.1UF

VCCSM23 VCC46
CE14

Note: All VCCSM pins


150U/4.0V

AH25 V18

Place near pin A35


VCCSM22 VCC45
150U/4.0V

AJ25 VCCSM21 VCC44 W18


AK25 VCCSM20 VCC43 K19 2 1
AL25 U19 2 1
+1.5VS_HPLL

VCCSM19 VCC42
AM25 VCCSM18 VCC41 V19
C223

+1.5VS_DPLLB

AN25 K20
1

0.1UF

POWER

VCCSM17 VCC40
C271

AP25 T20
1

0.1UF

VCCSM16 VCC39
AE26 VCCSM15 VCC38 U20
+2.5VS
L38

AF26 VCCSM14 VCC37 W20


L43

C509

AG26 K21
2

VCCSM13 VCC36
AH26 K22
2

VCCSM12 VCC35
10UF/10V

2 1 AJ26 VCCSM11 VCC34 K23


V1.8_DDR_CAP1
V1.8_DDR_CAP2
V1.8_DDR_CAP5

AK26 K24
120Ohm/100Mhz

VCCSM10 VCC33
AL26 J25
120Ohm/100Mhz

VCCSM9 VCC32
AM26 VCCSM8 VCC31 K25
C502

AN26 H26
0.1UF

VCCSM7 VCC30
2 1 AP26 VCCSM6 VCC29 K26
AC27 VCCSM5 VCC28 H27
AD27 VCCSM4 VCC27 J27
AD28 VCCSM3 VCC26 K27
AP29 VCCSM2 VCC25 L27
AH37 VCCSM1 VCC24 M27
AM37 VCCSM0 VCC23 N27 2 1
+

VCC22 P27
A21 VCCHV2 VCC21 R27
B21 VCCHV1 VCC20 T27
CE15

150U/4.0V

2 1 B22 VCCHV0 VCC19 U27


V27 2 1
+1.5VS

VCC18
A35 VCCA_LVDS VCC17 G28
C498

H28 2 1
0.1UF

VCC16
+1.5VS_DPLLA

C272

2 1 A25 J28
0.1UF

VCCD_LVDS2 VCC15
B25 VCCD_LVDS1 VCC14 K28
B26 VCCD_LVDS0 VCC13 L28
C250

C497

M28
1

VCC12
0.01UF

VCCDQ_TVDAC H17 N28 2 1


10UF/10V

VCCD_TVDAC VCCDQ_TVDAC VCC11


D19 VCCD_TVDAC VCC10 P28
L42

VCC9 R28
G18 T28
2

2
2

VSSA_TVBG VCC8
C244

VCCA_TVBG H18 U28


VCCA_TVBG VCC7
V28 2 1
10UF/10V

VCC6
E18 J29
120Ohm/100Mhz

VCCA_TVDACC VCCA_TVDACC1 VCC5


F18 VCCA_TVDACC0 VCC4 K29
C18 VCCA_TVDACB1 VCC3 M29
C247

VCCA_TVDACB D18 N29


VCCA_TVDACB0 VCC2
E17 VCCA_TVDACA1 VCC1 R29 2 1
+1.5VS

VCCA_TVDACA F17 T29


VCCA_TVDACA0 VCC0
C236

10UF/10V 0.1UF

U49G

2 1
3VS:
1.8V:
C246

0.1UF

02-010002640

2 1
ALVISO_BGA1257
/*
R1.1-S18

+2.5VS_CRTDAC
RN60

Disable TV_OUT
10Ohm

C255

0.1UF

120mA
2.5VS: 293mA
1.05V
+VCC_GMCH_CORE

2
1.5VS: 1264mA

1 2 3
3 4 1
5 6
7 8
/*
D67
+VCC_GMCH_CORE

1.05VS:850mA for CPU

C
Date:
BAT54C

Size
==> All TV POWER short to GND
+2.5VS

2
1 2 3
ASUSTECH CO.,LTD.
3100mA for external gfx

3 4 1
Project Name

5 6
2A for DDR2 400 2 channel
1A for DDR2 400 1 channel

7 8
Thursday, June 09, 2005
2.7A for DDR2 533 2 channel
1.3A for DDR2 533 1 channel
+VCC_GMCH_CORE

D38

Z61Ae
BAT54C

1
1

+3VS

2
RN49 RN52A
10Ohm 22Ohm

1 2 3
1
+1.5VS

Engineer:

Sheet

3 4
D41
BAT54C

10

5 6
22Ohm 22Ohm
RN52B RN52C

of

7 8
Sam Wang

57
Title : Alviso--POWER (4)
22Ohm
RN52D

2.0
Rev
A
B
C
D
A
B
C
D

5
5

<8>
<8>

CFG7
CFG5
B36 VSSALVDS
VSS267 AL24
VSS266 AN24
Y1 VSS271 VSS265 A26
1 2 1 2 D2 VSS270 VSS264 E26
G2 VSS269 VSS263 G26
J2 J26

/*
/*
VSS268 VSS262
L2 B27

R251
R245
VSS260 VSS261
P2 E27

CFG7 : CPU STRAP


VSS259 VSS129
T2 G27

+1.8V
VSS258 VSS128

2.2KOhm
2.2KOhm
V2 VSS257 VSS127 W27
AD2 VSS256 VSS126 AA27

+VCC_GMCH_CORE
AE2 VSS255 VSS125 AB27

CFG5 : LOW = DMI X 2


AH2 VSS254 VSS124 AF27
VCCSM_NCTF31 AB12 AL2 VSS253 VSS123 AG27
VCCSM_NCTF30 AC12 AN2 VSS252 VSS122 AJ27
VCCSM_NCTF29 AD12 A3 VSS251 VSS121 AL27
VCCSM_NCTF28 AB13 C3 VSS250 VSS120 AN27
VCCSM_NCTF27 AC13 AA3 VSS249 VSS119 E28

V HIGH = DMI X 4 (Default)


VCCSM_NCTF26 AD13 AB3 VSS248 VSS118 W28

LOW = Mobile Prescott


VCCSM_NCTF25 AC14 AC3 VSS247 VSS117 AA28
VCCSM_NCTF24 AD14 AJ3 VSS246 VSS116 AB28
VCCSM_NCTF23 AC15 C4 VSS245 VSS115 AC28
VCCSM_NCTF22 AD15 H4 VSS244 VSS114 A29

V HIGH = Dothan CPU (Default)


AC16 L4 D29

<8>
VCCSM_NCTF21 VSS243 VSS113
AD16 P4 E29

<8>
VCCSM_NCTF20 VSS242 VSS112
VCCSM_NCTF19 AC17 U4 VSS241 VSS111 F29
VCCSM_NCTF18 AD17 Y4 VSS240 VSS110 G29
VCCSM_NCTF17 AC18 AF4 VSS239 VSS109 H29
VCCSM_NCTF16 AD18 AN4 VSS238 VSS108 L29
AC19 E5 P29

CFG18
VCCSM_NCTF15 VSS237 VSS107

CFG9
AD19 W5 U29

4
4

VCCSM_NCTF14 VSS236 VSS106


VCCSM_NCTF13 AC20 AL5 VSS235 VSS105 V29
VCCSM_NCTF12 AD20 AP5 VSS234 VSS104 W29
L12 VTT_NCTF17 VCCSM_NCTF11 AC21 B6 VSS233 VSS103 AA29
M12 VTT_NCTF16 VCCSM_NCTF10 AD21 J6 VSS232 VSS102 AD29
N12 VTT_NCTF15 VCCSM_NCTF9 AC22 L6 VSS231 VSS101 AG29
1 2 P12 VTT_NCTF14 VCCSM_NCTF8 AD22 P6 VSS230 VSS100 AJ29
1 2 R12 VTT_NCTF13 VCCSM_NCTF7 AC23 T6 VSS229 VSS99 AM29

+2.5VS
T12 AD23 AA6 C30

/*
VTT_NCTF12 VCCSM_NCTF6 VSS228 VSS98
U12 AC24 AC6 Y30

/*

R238
VTT_NCTF11 VCCSM_NCTF5 VSS227 VSS97
V12 AD24 AE6 AA30

R249
VTT_NCTF10 VCCSM_NCTF4 VSS226 VSS96

1KOhm
W12 VTT_NCTF9 VCCSM_NCTF3 AC25 AJ6 VSS225 VSS95 AB30
L13 VTT_NCTF8 VCCSM_NCTF2 AD25 G7 VSS224 VSS94 AC30

2.2KOhm
M13 VTT_NCTF7 VCCSM_NCTF1 AC26 V7 VSS223 VSS93 AE30
N13 VTT_NCTF6 VCCSM_NCTF0 AD26 AA7 VSS222 VSS92 AP30
P13 VTT_NCTF5 AG7 VSS221 VSS91 D31
R13 VTT_NCTF4 VCC_NCTF78 L17 AK7 VSS220 VSS90 E31
T13 M17 AN7 F31

HIGH = 1.5V
CFG9 : PCIE GRAPHIC LANE
VTT_NCTF3 VCC_NCTF77 VSS219 VSS89
U13 VTT_NCTF2 VCC_NCTF76 N17 C8 VSS218 VSS88 G31
V13 VTT_NCTF1 VCC_NCTF75 P17 E8 VSS217 VSS87 H31
W13 T17 L8 J31

CFG18 : GMCH CORE SELECT


VTT_NCTF0 VCC_NCTF74 VSS216 VSS86
VCC_NCTF73 U17 P8 VSS215 VSS85 K31
VCC_NCTF72 V17 Y8 VSS214 VSS84 L31
W17 AL8 M31

V LOW = 1.05V (Default)


VCC_NCTF71 VSS213 VSS83
VCC_NCTF70 L18 A9 VSS212 VSS82 N31
M18 H9 P31

LOW = REVERSE LANE


VCC_NCTF69 VSS211 VSS81
Y12 VSS_NCTF68 VCC_NCTF68 N18 K9 VSS210 VSS80 R31
AA12 VSS_NCTF67 VCC_NCTF67 P18 T9 VSS209 VSS79 T31
Y13 VSS_NCTF66 VCC_NCTF66 R18 V9 VSS208 VSS78 U31
AA13 VSS_NCTF65 VCC_NCTF65 Y18 AA9 VSS207 VSS77 V31
L14 VSS_NCTF64 VCC_NCTF64 L19 AC9 VSS206 VSS76 W31
M14 VSS_NCTF63 VCC_NCTF63 M19 AE9 VSS205 VSS75 AD31
N14 VSS_NCTF62 VCC_NCTF62 N19 AH9 VSS204 VSS74 AG31
P14 VSS_NCTF61 VCC_NCTF61 P19 AN9 VSS203 VSS73 AL31
R14 R19 D10 A32
V HIGH = NORMAL OPERATION (Default)
VSS_NCTF60 VCC_NCTF60 VSS202 VSS72
T14 VSS_NCTF59 VCC_NCTF59 Y19 L10 VSS201 VSS71 C32
U14 VSS_NCTF58 VCC_NCTF58 L20 Y10 VSS200 VSS70 Y32
V14 M20 AA10 AA32
<8>

VSS_NCTF57 VCC_NCTF57 VSS199 VSS69


W14 N20 F11 AB32
VSS

VSS_NCTF56 VCC_NCTF56 VSS198 VSS68


Y14 VSS_NCTF55 P20 H11 AC32
NCTF

VCC_NCTF55 VSS197 VSS67


AA14 R20 Y11 AD32

3
3

VSS_NCTF54 VCC_NCTF54 VSS196 VSS66


AB14 VSS_NCTF53 VCC_NCTF53 Y20 AA11 VSS195 VSS65 AJ32
L15 VSS_NCTF52 VCC_NCTF52 L21 AF11 VSS194 VSS64 AN32
M15 M21 AG11 D33
CFG16

VSS_NCTF51 VCC_NCTF51 VSS193 VSS63


N15 VSS_NCTF50 VCC_NCTF50 N21 AJ11 VSS192 VSS62 E33

400 1 0 1
533 0 0 1
P15 P21 AL11 F33
CFG [ 2 : 0 ]
VSS_NCTF49 VCC_NCTF49 VSS191 VSS61
R15 VSS_NCTF48 VCC_NCTF48 T21 AN11 VSS190 VSS60 G33
T15 VSS_NCTF47 VCC_NCTF47 U21 B12 VSS189 VSS59 H33
U15 VSS_NCTF46 VCC_NCTF46 V21 D12 VSS188 VSS58 J33
V15 VSS_NCTF45 VCC_NCTF45 W21 J12 VSS187 VSS57 K33
1 2 W15 VSS_NCTF44 VCC_NCTF44 L22 A14 VSS186 VSS56 L33

SDVOCRTL_DATA :
Y15 VSS_NCTF43 VCC_NCTF43 M22 B14 VSS185 VSS55 M33
AA15 N22 F14 N33
/*

VSS_NCTF42 VCC_NCTF42 VSS184 VSS54


AB15 P22 J14 P33
R223

VSS_NCTF41 VCC_NCTF41 VSS183 VSS53


L16 VSS_NCTF40 VCC_NCTF40 R22 K14 VSS182 VSS52 R33
M16 VSS_NCTF39 VCC_NCTF39 T22 AG14 VSS181 VSS51 T33
2.2KOhm

N16 VSS_NCTF38 VCC_NCTF38 U22 AJ14 VSS180 VSS50 U33


P16 VSS_NCTF37 VCC_NCTF37 V22 AL14 VSS179 VSS49 V33
R16 W22 AN14 W33
CFG [13:12]

VSS_NCTF36 VCC_NCTF36 VSS178 VSS48


T16 L23 C15 AD33
1 0 : Z MODE

VSS_NCTF35 VCC_NCTF35 VSS177 VSS47


CFG16 : FSB DYNAMIC ODT

U16 VSS_NCTF34 VCC_NCTF34 M23 K15 VSS176 VSS46 AF33


0 1 : Xor MODE

CFG[17..3] have internal pullup resistors.


V16 VSS_NCTF33 VCC_NCTF33 N23 A16 VSS175 VSS45 AL33
W16 VSS_NCTF32 VCC_NCTF32 P23 D16 VSS174 VSS44 C34
LOW = No SDVO device present (Default)

Y16 R23 H16 AA34


CFG[19..18] have internal pulldown resistors.

VSS_NCTF31 VCC_NCTF31 VSS173 VSS43


AA16 T23 K16 AB34
1 1 : Normal operation

VSS_NCTF30 VCC_NCTF30 VSS172 VSS42


AB16 VSS_NCTF29 VCC_NCTF29 U23 AL16 VSS171 VSS41 AC34
R17 VSS_NCTF28 VCC_NCTF28 V23 C17 VSS170 VSS40 AD34
SDVOCRTL_DATA has internal pulldown resistors.

Y17 VSS_NCTF27 VCC_NCTF27 W23 G17 VSS169 VSS39 AH34


AA17 L24 AF17 AN34
NCTF pin can share the via each other or even leave NC

VSS_NCTF26 VCC_NCTF26 VSS168 VSS38


AB17 VSS_NCTF25 VCC_NCTF25 M24 AJ17 VSS167 VSS37 B35
AA18 VSS_NCTF24 VCC_NCTF24 N24 AN17 VSS166 VSS36 D35
AB18 VSS_NCTF23 VCC_NCTF23 P24 A18 VSS165 VSS35 E35
AA19 R24 B18 F35
LOW = Dynamic ODT Disabled

VSS_NCTF22 VCC_NCTF22 VSS164 VSS34


AB19 VSS_NCTF21 VCC_NCTF21 T24 U18 VSS163 VSS33 G35
AA20 VSS_NCTF20 VCC_NCTF20 U24 AL18 VSS162 VSS32 H35
AB20 VSS_NCTF19 VCC_NCTF19 V24 C19 VSS161 VSS31 J35
R21 VSS_NCTF18 VCC_NCTF18 W24 H19 VSS160 VSS30 K35
Y21 VSS_NCTF17 VCC_NCTF17 L25 J19 VSS159 VSS29 L35
V HIGH = Dynamic ODT Enabled (Default)

AA21 VSS_NCTF16 VCC_NCTF16 M25 T19 VSS158 VSS28 M35


AB21 VSS_NCTF15 VCC_NCTF15 N25 W19 VSS157 VSS27 N35
Y22 P25 AG19 P35

2
2

VSS_NCTF14 VCC_NCTF14 VSS156 VSS26


AA22 VSS_NCTF13 VCC_NCTF13 R25 AN19 VSS155 VSS25 R35
AB22 VSS_NCTF12 VCC_NCTF12 T25 A20 VSS154 VSS24 T35
Y23 U25 D20 U35
<8>
<8>

VSS_NCTF11 VCC_NCTF11 VSS153 VSS23


AA23 VSS_NCTF10 VCC_NCTF10 V25 E20 VSS152 VSS22 V35
AB23 VSS_NCTF9 VCC_NCTF9 W25 F20 VSS151 VSS21 W35
Y24 VSS_NCTF8 VCC_NCTF8 L26 G20 VSS150 VSS20 Y35
AA24 VSS_NCTF7 VCC_NCTF7 M26 V20 VSS149 VSS19 AE35
AB24 VSS_NCTF6 VCC_NCTF6 N26 AK20 VSS148 VSS18 C36
CFG6

Y25 P26 C21 AA36


CFG19

VSS_NCTF5 VCC_NCTF5 VSS147 VSS17


AA25 VSS_NCTF4 VCC_NCTF4 R26 F21 VSS146 VSS16 AB36
AB25 VSS_NCTF3 VCC_NCTF3 T26 AF21 VSS145 VSS15 AC36
Y26 VSS_NCTF2 VCC_NCTF2 U26 AN21 VSS144 VSS14 AD36
AA26 VSS_NCTF1 VCC_NCTF1 V26 A22 VSS143 VSS13 AE36
AB26 VSS_NCTF0 VCC_NCTF0 W26 D22 VSS142 VSS12 AF36
E22 VSS141 VSS11 AJ36
1 2 1 2 J22 VSS140 VSS10 AL36
AH22 VSS139 VSS9 AN36
U49E

+2.5VS

AL22 E37
/*

VSS138 VSS8
H23 H37
R250
R239

VSS137 VSS7
AF23 VSS136 VSS6 K37
1KOhm
+VCC_GMCH_CORE

B24 VSS135 VSS5 M37


02-010002640

2.2KOhm

D24 VSS134 VSS4 P37


F24 T37
ALVISO_BGA1257

VSS133 VSS3
J24 VSS132 VSS2 V37
AG24 VSS131 VSS1 Y37
CFG19 : CPU VTT SELECT

AJ24 VSS130 VSS0 AG37


C
Date:
HIGH = 1.2V

Size
CFG6 : LOW = DDR2 SDRAM V
U49H

V LOW = 1.05V (Default)


02-010002640

HIGH = DDR SDRAM (Default)

ASUSTECH CO.,LTD.
Project Name
ALVISO_BGA1257

Thursday, June 09, 2005


Z61Ae
1
1

Engineer:

Sheet
11
of
Sam Wang

57
2.0
Rev
Title : Alviso-GND/NCTF/Strap(5)
A
B
C
D
5 4 3 2 1

<9,14> M_B_A[0..13]
R1.1-S20 M_B_DQ[0..63] <9>

CON21B
M_B_A0 B102 B5 M_B_DQ0
M_B_A1 B:A0 B:DQ0 M_B_DQ6
B101 B:A1 B:DQ1 B7
M_B_A2 B100 B17 M_B_DQ2
M_B_A3 B:A2 B:DQ2 M_B_DQ3
B99 B:A3 B:DQ3 B19
M_B_A4 B98 B4 M_B_DQ7
DCLK3 M_B_A5 B:A4 B:DQ4 M_B_DQ1
D B97 B:A5 B:DQ5 B6 D
M_B_A6 B94 B14 M_B_DQ5
M_B_A7 B:A6 B:DQ6 M_B_DQ4
B92 B:A7 B:DQ7 B16

2
C722 M_B_A8 B93 B23 M_B_DQ8
10PF PLACE NEAR SO-DIMM_0 M_B_A9 B:A8 B:DQ8 M_B_DQ9
B91 B:A9 B:DQ9 B25
c0402 M_B_A10 B105 B35 M_B_DQ15

1
M_B_A11 B:A10/AP B:DQ10 M_B_DQ14
B90 B:A11 B:DQ11 B37
DCLK3# M_B_A12 B89 B20 M_B_DQ12
M_B_A13 B:A12 B:DQ12 M_B_DQ13
B116 B:A13 B:DQ13 B22
B86 B36 M_B_DQ11
B:A14 B:DQ14 M_B_DQ10
B84 B:A15 B:DQ15 B38
DCLK4 B85 B43 M_B_DQ20
<9,14> M_B_BS#2 B:A16_BA2 B:DQ16
B107 B45 M_B_DQ16
<9,14> M_B_BS#0 B:BA0 B:DQ17
B106 B55 M_B_DQ19
<9,14> M_B_BS#1 B:BA1 B:DQ18

2
C723 B110 B57 M_B_DQ18
<8,14> SCS2# B:S0# B:DQ19
10PF PLACE NEAR SO-DIMM_0 B115 B44 M_B_DQ17
<8,14> SCS3# B:S1# B:DQ20
c0402 B30 B46 M_B_DQ21
<8> DCLK3

1
B:CK0 B:DQ21 M_B_DQ22
<8> DCLK3# B32 B:CK0# B:DQ22 B56
DCLK4# B164 B58 M_B_DQ23
<8> DCLK4 B:CK1 B:DQ23
B166 B61 M_B_DQ29
<8> DCLK4# B:CK1# B:DQ24
B79 B63 M_B_DQ28
<8,14> SCKE2 B:CKE0 B:DQ25
B80 B73 M_B_DQ26
<8,14> SCKE3 B:CKE1 B:DQ26
B113 B75 M_B_DQ27
<9,14> M_B_CAS# B:CBS# B:DQ27
B108 B62 M_B_DQ24
<9,14> M_B_RAS# B:RAS# B:DQ28
B109 B64 M_B_DQ25
<9,14> M_B_WE# B:WE# B:DQ29
B198 B74 M_B_DQ30
B:SA0 B:DQ30 M_B_DQ31
B200 B:SA1 B:DQ31 B76
B197 B123 M_B_DQ32
<13,21,28,35> SCL_3S B:SCL B:DQ32
R724 B195 B125 M_B_DQ36
<13,21,28,35> SDA_3S B:SDA B:DQ33
10KOhm M_B_DQ34
1 2
R2.0-S03 B114
B:DQ34 B135
B137 M_B_DQ38
C +3VS <8,14> ODT2 B:ODT0 B:DQ35 C
B119 B124 M_B_DQ33
<8,14> ODT3 B:ODT1 B:DQ36
GND B126 M_B_DQ37
<9> M_B_DM[0..7] B:DQ37
r0402 M_B_DM0 B10 B134 M_B_DQ39
M_B_DM1 B:DM0 B:DQ38 M_B_DQ35
B26 B:DM1 B:DQ39 B136
M_B_DM2 B52 B141 M_B_DQ45
M_B_DM3 B:DM2 B:DQ40 M_B_DQ44
B67 B:DM3 B:DQ41 B143
M_B_DM4 B130 B151 M_B_DQ42
M_B_DM5 B:DM4 B:DQ42 M_B_DQ47
B147 B:DM5 B:DQ43 B153
M_B_DM6 B170 B140 M_B_DQ40
M_B_DM7 B:DM6 B:DQ44 M_B_DQ41
B185 B:DM7 B:DQ45 B142
B152 M_B_DQ43
<9> M_B_DQS[0..7] B:DQ46
M_B_DQS0 B13 B154 M_B_DQ46
M_B_DQS1 B:DQS0 B:DQ47 M_B_DQ53
B31 B:DQS1 B:DQ48 B157
M_B_DQS2 B51 B159 M_B_DQ48
M_B_DQS3 B:DQS2 B:DQ49 M_B_DQ54
B70 B:DQS3 B:DQ50 B173
M_B_DQS4 B131 B175 M_B_DQ50
M_B_DQS5 B:DQS4 B:DQ51 M_B_DQ52
B148 B:DQS5 B:DQ52 B158
M_B_DQS6 B169 B160 M_B_DQ49
M_B_DQS7 B:DQS6 B:DQ53 M_B_DQ55
<9> M_B_DQS#[0..7] B188 B:DQS7 B:DQ54 B174
M_B_DQS#0 B11 B176 M_B_DQ51
M_B_DQS#1 B:DQS0# B:DQ55 M_B_DQ61
B29 B:DQS1# B:DQ56 B179
M_B_DQS#2 B49 B181 M_B_DQ56
M_B_DQS#3 B:DQS2# B:DQ57 M_B_DQ60
B68 B:DQS3# B:DQ58 B189
M_B_DQS#4 B129 B191 M_B_DQ58
M_B_DQS#5 B:DQS4# B:DQ59 M_B_DQ59
B146 B:DQS5# B:DQ60 B180
Layout Note: Place these High-Freq decoupling Caps near the GMCH M_B_DQS#6 B167 B182 M_B_DQ57
M_B_DQS#7 B:DQS6# B:DQ61 M_B_DQ62
B186 B:DQS7# B:DQ62 B192
B194 M_B_DQ63
B:DQ63
+1.8V Layout Note: Place these Caps near SO DIMM 0
1

B
+1.8V B111 B:VDD2 B:VSS26 B127 B
C727 C728 C729 C730 B117 B139
B:VDD3 B:VSS27

1
0.1UF 0.1UF 0.1UF 0.1UF B95 B145
2

c0402 c0402 c0402 c0402 C731 C732 C733 C734 B:VDD5 B:VSS29
B81 B:VDD7 B:VSS30 B165
2 0.1UF 0.1UF 0.1UF 0.1UF B87 B171

2
GND GND GND GND c0402 c0402 c0402 c0402 B:VDD9 B:VSS31
B103 B:VDD10 B:VSS33 B177
B:VSS34 B187
GND GND GND GND B47 B9
B:VSS1 B:VSS37
B133 B:VSS2 B:VSS38 B21
B183 B:VSS3 B:VSS39 B33
B77 B:VSS4 B:VSS40 B155
GND B71 B3
+3VS B:VSS9 B:VSS47
B121 B:VSS11 B:VSS48 B15
1

1
B193 B:VSS14 B:VSS49 B27
Layout Note: Place these resistors near the GMCH C735 C736 B41 B39
0.1UF 0.1UF B:VSS18 B:VSS50
B53 B149
2

c0402 c0402 B:VSS19 B:VSS51


B59 B:VSS22 B:VSS52 B161
B65 B:VSS23
GND GND
+1.8V
B199 B:VDDSPD B:NC1 B83
1

B120 GND
C737 C738 C739 C740 C741 B:NC2
VTT_REF B1 B:VREF B:NC3 B50
2.2uF/6.3V 2.2uF/6.3V 2.2uF/6.3V 2.2uF/6.3V 2.2uF/6.3V B69
2

B:NC4
VREF -> 10/10 B:NCTEST B163
1

1
GND GND GND GND GND
mils C742 C743 DDR_DIMM_331P
2.2uF/6.3V 0.1UF
2

2
c0402

A
GND
Layout Note: Place these Caps near SO DIMM 0
GND DDR2 DIMM SOCKET and A

SCHEMATC is the same as A6V.

Title : DDR2 SO-DIMM_0


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
Custom Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 12 of 57
5 4 3 2 1
5 4 3 2 1

<9,14> M_A_A[0..13]
R1.1-S20 M_A_DQ[0..63] <9>
CON21A
M_A_A0 A102 A5 M_A_DQ5
M_A_A1 A:A0 A:DQ0 M_A_DQ4
A101 A:A1 A:DQ1 A7
M_A_A2 A100 A17 M_A_DQ2
M_A_A3 A:A2 A:DQ2 M_A_DQ7
A99 A:A3 A:DQ3 A19
M_A_A4 A98 A4 M_A_DQ0
M_A_A5 A:A4 A:DQ4 M_A_DQ1
A97 A:A5 A:DQ5 A6
M_A_A6 A94 A14 M_A_DQ6
M_A_A7 A:A6 A:DQ6 M_A_DQ3
D A92 A:A7 A:DQ7 A16 D
M_A_A8 A93 A23 M_A_DQ9
M_A_A9 A:A8 A:DQ8 M_A_DQ12
A91 A:A9 A:DQ9 A25
DCLK0 M_A_A10 A105 A35 M_A_DQ14
M_A_A11 A:A10/AP A:DQ10 M_A_DQ15
A90 A:A11 A:DQ11 A37
M_A_A12 A89 A20 M_A_DQ8
2
C744 M_A_A13 A:A12 A:DQ12 M_A_DQ13
A116 A:A13 A:DQ13 A22
10PF PLACE NEAR SO-DIMM_1 A86 A36 M_A_DQ10
c0402 A:A14 A:DQ14 M_A_DQ11
A84 A38
1

A:A15 A:DQ15 M_A_DQ21


<9,14> M_A_BS#2 A85 A:A16_BA2 A:DQ16 A43
DCLK0# A45 M_A_DQ23
A:DQ17 M_A_DQ19
<9,14> M_A_BS#0 A107 A:BA0 A:DQ18 A55
A106 A57 M_A_DQ22
<9,14> M_A_BS#1 A:BA1 A:DQ19
A110 A44 M_A_DQ16
<8,14> SCS0# A:S0# A:DQ20
DCLK1 A115 A46 M_A_DQ17
<8,14> SCS1# A:S1# A:DQ21
A30 A56 M_A_DQ18
<8> DCLK0 A:CK0 A:DQ22
A32 A58 M_A_DQ20
<8> DCLK0# A:CK0# A:DQ23
2

C745 A164 A61 M_A_DQ28


<8> DCLK1 A:CK1 A:DQ24
10PF PLACE NEAR SO-DIMM_1 A166 A63 M_A_DQ29
<8> DCLK1# A:CK1# A:DQ25
c0402 A79 A73 M_A_DQ26
<8,14> SCKE0
1

A:CKE0 A:DQ26 M_A_DQ27


<8,14> SCKE1 A80 A:CKE1 A:DQ27 A75
DCLK1# A113 A62 M_A_DQ24
<9,14> M_A_CAS# A:CAS# A:DQ28
A108 A64 M_A_DQ25
<9,14> M_A_RAS# A:RAS# A:DQ29
A109 A74 M_A_DQ30
<9,14> M_A_WE# A:WE# A:DQ30
A198 A76 M_A_DQ31
A:SA0 A:DQ31 M_A_DQ32
A200 A:SA1 A:DQ32 A123
A197 A125 M_A_DQ33
<12,21,28,35> SCL_3S A:SCL A:DQ33
R2.0-S03 A195 A135 M_A_DQ35
<12,21,28,35> SDA_3S A:SDA A:DQ34
A137 M_A_DQ34
A:DQ35 M_A_DQ37
<8,14> ODT0 A114 A:ODT0 A:DQ36 A124
A119 A126 M_A_DQ36
C <8,14> ODT1 A:ODT1 A:DQ37 C
A134 M_A_DQ38
<9> M_A_DM[0..7] A:DQ38
M_A_DM0 A10 A136 M_A_DQ39
M_A_DM1 A:DM0 A:DQ39 M_A_DQ45
A26 A:DM1 A:DQ40 A141
GND GND M_A_DM2 A52 A143 M_A_DQ40
M_A_DM3 A:DM2 A:DQ41 M_A_DQ43
A67 A:DM3 A:DQ42 A151
M_A_DM4 A130 A153 M_A_DQ42
M_A_DM5 A:DM4 A:DQ43 M_A_DQ41
A147 A:DM5 A:DQ44 A140
M_A_DM6 A170 A142 M_A_DQ44
M_A_DM7 A:DM6 A:DQ45 M_A_DQ47
A185 A:DM7 A:DQ46 A152
A154 M_A_DQ46
<9> M_A_DQS[0..7] A:DQ47
M_A_DQS0 A13 A157 M_A_DQ53
M_A_DQS1 A:DQS0 A:DQ48 M_A_DQ52
A31 A:DQS1 A:DQ49 A159
M_A_DQS2 A51 A173 M_A_DQ51
M_A_DQS3 A:DQS2 A:DQ50 M_A_DQ50
A70 A:DQS3 A:DQ51 A175
M_A_DQS4 A131 A158 M_A_DQ48
M_A_DQS5 A:DQS4 A:DQ52 M_A_DQ49
A148 A:DQS5 A:DQ53 A160
M_A_DQS6 A169 A174 M_A_DQ55
M_A_DQS7 A:DQS6 A:DQ54 M_A_DQ54
<9> M_A_DQS#[0..7] A188 A:DQS7 A:DQ55 A176
M_A_DQS#0 A11 A179 M_A_DQ60
M_A_DQS#1 A:DQS0# A:DQ56 M_A_DQ61
A29 A:DQS1# A:DQ57 A181
M_A_DQS#2 A49 A189 M_A_DQ62
M_A_DQS#3 A:DQS2# A:DQ58 M_A_DQ63
A68 A:DQS3# A:DQ59 A191
M_A_DQS#4 A129 A180 M_A_DQ57
M_A_DQS#5 A:DQS4# A:DQ60 M_A_DQ56
A146 A:DQS5# A:DQ61 A182
M_A_DQS#6 A167 A192 M_A_DQ58
M_A_DQS#7 A:DQS6# A:DQ62 M_A_DQ59
A186 A:DQS7# A:DQ63 A194

Layout Note: Place these Caps near SO DIMM 1


+1.8V A112 A:VDD1 A:VSS21 A54
B A96 A:VDD4 A:VSS24 A60 B
1

1
A118 A:VDD6 A:VSS25 A66
C746 C747 C748 C749 A82 A128
0.1UF 0.1UF 0.1UF 0.1UF A:VDD8 A:VSS28
A88 A172
2

2
c0402 c0402 c0402 c0402 A:VDD11 A:VSS32
A104 A:VDD12 A:VSS35 A178
Layout Note: Place these Caps near SO DIMM 1 GND GND GND GND A:VSS36 A190
A12 A:VSS5 A:VSS41 A34
+1.8V A48 A:VSS6 A:VSS42 A132
A184 A:VSS7 A:VSS43 A144
GND A78 A156
A:VSS8 A:VSS44
1

+3VS A72 A:VSS10 A:VSS45 A168


C750 C751 C752 C753 C754 A122 A2
A:VSS12 A:VSS46
1

1
2.2uF/6.3V 2.2uF/6.3V 2.2uF/6.3V 2.2uF/6.3V 2.2uF/6.3V A196 A28
2

C755 C756 A:VSS13 A:VSS53


A8 A:VSS15 A:VSS54 A40
0.1UF 0.1UF A18 A138
2

2
GND GND GND GND GND c0402 c0402 A:VSS16 A:VSS55
A24 A:VSS17 A:VSS56 A150
A42 A:VSS20 A:VSS57 A162
GND GND
A199 A:VDDSPD A:NC1 A83
A:NC2 A120
VTT_REF A1 A:VREF A:NC3 A50

NP_NC1
NP_NC2
NP_NC3
NP_NC4
A:NC4 A69

GND1
GND2
GND3
GND4
A:NCTEST A163
VREF -> 10/10
SO-DIMM 1 is placed father from
1

mils 1
C757 C758 DDR_DIMM_331P
the GMCH than SO-DIMM 0

201
202
203
204

205
206
208
207
2.2uF/6.3V 0.1UF
2

c0402

GND GND
A A
GND

DDR2 DIMM SOCKET and SCHEMATC


is the same as A6V.
Title : DDR2 SO-DIMM_1
ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
Custom Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 13 of 57
5 4 3 2 1
5 4 3 2 1

D D

+0.9VS

R685 1 2 56Ohm SCKE0


R686 1 2 56Ohm SCKE1
R687 1 2 56Ohm SCKE2
R688 1 2 56Ohm SCKE3

R689 1 2 56Ohm ODT0


R690 1 2 56Ohm ODT1
R691 1 2 56Ohm ODT2
R692 1 2 56Ohm ODT3
M_A_A[0..13] <9,13>
R693 1 2 56Ohm M_A_A13
R694 1 2 56Ohm M_A_BS#1
R1.1-S28 M_A_BS#[0..2] <9,13>

M_B_A[0..13] <9,12>
R696 1 2 56Ohm M_B_A12
R697 1 2 56Ohm M_A_RAS#
M_B_BS#[0..2] <9,12> M_A_RAS# <9,13>

SCKE[0:3] <8,12,13>
C R699 1 2 56Ohm M_B_BS#2 C
R700 1 2 56Ohm M_B_A10
ODT[0:3] <8,12,13>
R701 1 2 56Ohm M_B_A3

R702 1 2 56Ohm M_B_CAS#


M_B_CAS# <9,12>
R703 1 2 56Ohm M_B_A5
R704 1 2 56Ohm M_B_WE#
M_B_WE# <9,12>

+0.9VS R705 1 2 56Ohm SCS0#


SCS0# <8,13>
R706 1 2 56Ohm SCS1#
SCS1# <8,13>
R707 1 2 56Ohm SCS2#
SCS2# <8,12>
R708 1 2 56Ohm SCS3#
SCS3# <8,12>
1

1
C692 C693 C694 C695 C696 C697 C698 C699 C700 C701 C702 C703 C704
1 56Ohm 16 RN56A
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 2 56Ohm 15 RN56B
2

2
3 56Ohm 14 RN56C M_A_CAS#
M_A_CAS# <9,13>
4 56Ohm 13 RN56D M_A_BS#0
5 56Ohm 12 RN56E M_A_WE#
M_A_WE# <9,13>
6 56Ohm 11 RN56F M_B_BS#0
7 56Ohm 10 RN56G M_A_A10
8 56Ohm 9 RN56H M_A_A1

Layout note: Place one cap close to every 2 pullup resistors terminated to +0.9VS 1 16 RN57A M_B_A13
56Ohm
2 56Ohm 15 RN57B M_B_RAS#
+0.9VS M_B_RAS# <9,12>
3 56Ohm 14 RN57C M_B_BS#1
4 56Ohm 13 RN57D M_B_A0
5 56Ohm 12 RN57E M_B_A2
6 56Ohm 11 RN57F M_B_A6
7 56Ohm 10 RN57G M_A_A8
8 56Ohm 9 RN57H M_B_A11
1

1
C705 C706 C707 C708 C709 C710 C711 C712 C713 C714 C715 C716 C717
B B
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
2

2
1 56Ohm 16 RN58A M_A_A0
2 56Ohm 15 RN58B M_A_A2
3 56Ohm 14 RN58C M_A_A4
4 56Ohm 13 RN58D M_A_A6
5 56Ohm 12 RN58E M_A_A7
6 56Ohm 11 RN58F M_A_A11
7 56Ohm 10 RN58G M_B_A4
8 56Ohm 9 RN58H M_B_A7

1 56Ohm 16 RN59A M_B_A1


2 56Ohm 15 RN59B M_A_A5
3 56Ohm 14 RN59C M_A_A3
4 56Ohm 13 RN59D M_A_A9
5 56Ohm 12 RN59E M_B_A8
6 56Ohm 11 RN59F M_B_A9
7 56Ohm 10 RN59G M_A_A12
8 56Ohm 9 RN59H M_A_BS#2

A A

Title : DDR2 TERMINATION


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 14 of 57
5 4 3 2 1
5 4 3 2 1

TO SUPPORT SPWG PANEL(EDID)


+2.5VS
PID_0

PID_1

3 3
D D
Q146 Q147
1 1
D 2N7002 D
G G
2 S 2N7002 2 S /* C800
/* 1 2
<8> DDCDATA_GM +3VS
0.1UF
<8> DDCCLK_GM
L21 L22 CON2
1KOhm/100MHz +LCD_VCC 1 2 CON Part Number Modify as M3N
1
<24> PID_0 2 1 2
<24> PID_1 2 1 120Ohm/100Mhz
3
4

C27
L23 LVDS_CLKBM_GM
<8> LVDS_CLKBM_GM 5
1KOhm/100MHz LVDS_CLKBP_GM 35
<8> LVDS_CLKBP_GM 6 hold_gnd2

1
LVDS_YB1M_GM 7
<8> LVDS_YB1M_GM 8

2
2

C25
LVDS_YB1P_GM Panel Size Resolution Pixels Aspect Ratio
<8> LVDS_YB1P_GM

2
R25 R37 9
10 14.1” XGA 1024 x 768 4:3

1
1000PF
10KOhm 10KOhm LVDS_YB2P_GM
<8> LVDS_YB2P_GM 11
LVDS_YB2M_GM 14.1” SXGA+ 1400 x 10504:3
<8> LVDS_YB2M_GM 12

1
1

2
LVDS_YB0P_GM 13 14.1” UXGA 1600 x 12004:3
<8> LVDS_YB0P_GM 14 31

1000PF
LVDS_YB0M_GM
<8> LVDS_YB0M_GM 15 32
LVDS_CLKAM_GM 16 33
<8> LVDS_CLKAM_GM 17 34
LVDS_CLKAP_GM
<8> LVDS_CLKAP_GM 18
+3VS 19
LVDS_YA2P_GM
<8> LVDS_YA2P_GM 20
LVDS_YA2M_GM
<8> LVDS_YA2M_GM 21
LVDS_YA1P_GM 22
<8> LVDS_YA1P_GM 23 LVDS default Cable is 08-20C28012N.(None EDID function)
LVDS_YA1M_GM
<8> LVDS_YA1M_GM 24 It default PID setting is PID_0 = 1 and PID_1 = 0 on cable.
A theoretical maximum limit is calculated at 1.923 Gbit/s LVDS_YA0M_GM 25 hold_gnd1 36
<8> LVDS_YA0M_GM 26
LVDS_YA0P_GM To support EDID function that need new cable.
<8> LVDS_YA0P_GM 27
28 Panel ID is LCD vendor apply to system
29
C C
30
WtoB_2P
LVDS
CNT
S 2

Q4 RN2A
D

1 100Ohm 2
3

2N7002 RN2B
G

3 100Ohm 4
1

+VCC_INVERTOR
L8

AC_BAT_SYS 2 1
+3VSUS +12VS L91

1
1KOhm/100MHz 80Ohm/100Mhz C11 CON Part Number Modify as M3N
<8> ADJ_BL_GM 2 1 INVERTOR
/* 0.1UF/25V
CNT

2
2

B B
R41 L17
R24 1MOhm
To support PWM inverter. 2 1 1A CON1
<27> ADJ_BL
10KOhm 1
1KOhm/100MHz VCC1
2 VCC2 8 8
3
1

+3VS GND1
4 GND2
D5 R858 L14
5 VREF 9 9
1 2 1 0Ohm 2LCDVCC_ON +LCD_VCC 2 1 2 1 6 BKEN
R21 100KOhm 7 PWM
3
2
1

1
RB751V_40 1KOhm/100MHz C15 C20
G

3 Q2
D WTOB_CON_7P
D

Q6 0.1UF 0.1UF

2
R47
2 1 1 D3
S

G 2N7002 SI3456DV 1
<40,43> LID_SW#
4
5
6

470KOhm 2 S 3
2
1

C51
3 RB717F
<8> LCD_VDD_EN_GM D
1

0.01UF L24
2

Q3 C64 1 2 +LCD_VCC
1

1
2

G 2N7002 0.01UF 80Ohm/100Mhz R340


2 S
2

+3V
R46 1KOhm
2
1

10KOhm C31 C30 C42


14

C41 U42A
1

0.1UF 0.1UF 1UF/10V VCC


10UF/10V 1 BACK_OFF# <17,20>
2

3
2 LCD_BACKEN_GM <8>
GND
LV08A
7

R342
1 2

A 10KOhm A

Title : LVDS & INVERTER CONN.


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 15 of 57
5 4 3 2 1
5 4 3 2 1

CON Part Number Modify as M3N

CON10
RED 1 9
RED VCC
D D

DAC_R_CRT 1 2 RED
L1 0.068UH
DAC_G_CRT 1 2 GREEN
L2 0.068UH
DAC_B_CRT 1 2 BLUE
L3 0.068UH
DDC2BD_5 L6 1 2 120Ohm/100Mhz DDC2BD

HSYNC_CRT L7 1 2 120Ohm/100Mhz HSYNC


NC1 4
+12VS VSYNC_CRT L4 1 2 120Ohm/100Mhz VSYNC 11
NC2

2
R319 R321 DDC2BC_5 L5 1 2 120Ohm/100Mhz DDC2BC

GREEN 2 GREEN

1
1% 1% C349 C351 C348 C3 C7
+3VS R318 150Ohm 150Ohm C346 1.2PF/50V C6 C2

1
0Ohm 8.2PF/50V 8.2PF/50V 1.2PF/50V /* 8.2PF/50V 8.2PF/50V 47pF/50V 47pF/50V

2
/* /* /*

1
U40 R320 C350
2

1
1 B VCC 5 C347 C4
8.2PF/50V 1.2PF/50V C5 C8

2
<8> DAC_VSYNC_GM 2 A Q53A UM6K1N 1% /* /* 8.2PF/50V 47pF/50V 47pF/50V

2
2

150Ohm

1
3 GND 4
Y 1 6 1 2 VSYNC_CRT
U39 74LVC1G32GV +3VS R317 39Ohm
1 B VCC 5
5

<8> DAC_HSYNC_GM 2 A Q53BUM6K1N

3 GND 4 4 3 2 1 HSYNC_Q Intel Recommend


Y R325 0Ohm BLUE 3
74LVC1G32GV C = 10pF / 22pF / 10pF BLUE

DAC_IO_P
Bead = 47 ohm /100Mhz
C C
15
D25
1
DAC_R_CRT 3
R326

CRT
2
+12VS 1 2 PIN
BAV99 +5VS_CRT
10KOhm Q59 2N7002

1
G
D26

2 S

3
1 +5VS

D
DAC_B_CRT 3
2 1
+5VS_CRT
BAV99 HSYNC 13 HSYNC

D27
1
2

DAC_IO_P DAC_G_CRT 3
RN27A RN27B 2
2.2KOhm 2.2KOhm
BAV99
+2.5VS
1

VSYNC 14
DDC2BD_5 VSYNC
6

RN27C RN27D DDC2BC_5


2.2KOhm 2.2KOhm 3 3
D D
Q55 Q54
1 1
5

G G 2N7002 +5V
2 S 2N7002 2 S
U10
B B
PR_IN# 1 16
<26> PR_IN# IN VCC
DAC_R_PB 2 15
DAC_R_CRT S1A EN# HSYNC_PBS DDC2BD
3 S2A S1D 14 12 DATA
DAC_R 4 13 HSYNC_CRTS 1 2 HSYNC_CRT
<8> DDC2BD_GM DA S2D
DAC_G_PB 5 12 HSYNC_Q R38 39Ohm
<8> DDC2BC_GM S1B DD
DAC_G_CRT 6 11 DAC_B_PB
DAC_G S2B S1C DAC_B_CRT
7 DB S2C 10
8 9 DAC_B
GND DC

PI5V330W16
IN : 0 = S1 16
: 1 = S2 SIDE_G16
SIDE_G17 17
DAC_R
<8> DAC_R_GM
DAC_G DDC2BC 15
<8> DAC_G_GM DCLK

GND5
GND4
GND3
GND2
GND1
DAC_B
<8> DAC_B_GM
7846S_15G2T
Zo= 50 ohm
DAC_R_PB
<26> DAC_R_PB

10
8
7
6
5
DAC_G_PB
<26> DAC_G_PB
DAC_B_PB
<26> DAC_B_PB
DDC2BD_5
<26> DDC2BD_5
DDC2BC_5
<26> DDC2BC_5
HSYNC_PB 1 2 HSYNC_PBS
<26> HSYNC_PB
R343 39Ohm
VSYNC_CRT
<26> VSYNC_PB

To PortBar III

A A

Title : CRT
ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 16 of 57
5 4 3 2 1
5 4 3 2 1

Azalia_BCLK_R 1 2 Azalia_BCLK_AUD <37>


RA8 39Ohm
Azalia_SYNC
U15 Original P/N is 02-010002500(ICH6-M-None MP Version) 1
RA3
2
39Ohm
Azalia_SYNC_AUD <37>

U15 (SB) need to change to 02-010004402(ICH6-M-MP B2 Version) Azalia_RST# 1


RA6
2
39Ohm
Azalia_RST#_AUD <37,38>
R1.1 has changed it in symbol. Azalia_SDOUT 1 2 Azalia_SDOUT_AUD <37>
RA2 39Ohm
1 2 Azalia_BCLK_MDC <39>
RA7 39Ohm
1 2 Azalia_SYNC_MDC <39>
RA4 39Ohm
R1.1-S22 1 2 Azalia_RST#_MDC <39>
RA5 39Ohm
SATA_ICH_TXN0 2 1 1 2
SATA_BRIDGE_RXN0 <22> Azalia_SDOUT_MDC <39>
C763 3900PF/50V RA1 39Ohm
SATA_ICH_TXP0 2 1 SATA_BRIDGE_RXP0 <22>
C764 3900PF/50V R421
D D
Unused SATA pin 2 1 +3VS
PLACE CLOSELY TOGETHER
- Connect RX, RBIAS, CLK to GND 8.2KOhm +3VS
U15C - Leave TX, LED# as NC U15D

<22> IDE_PDD[0..15] BMBUSY#/GPI6 AD19 PM_BMBUSY# <8>

1
IDE_PDD15 AD13 AE3 SATA_ICH_RXN0 BATSEL_2P P4 AE19
DD_15 SATA_0RXN SATA_ICH_RXN0 <22> <20> BATSEL_2P LDRQ_1#/GPIO41 GPI7 GPI7 <20>
IDE_PDD14 AG15 AD3 SATA_ICH_RXP0 R1
DD_14 SATA_0RXP SATA_ICH_RXP0 <22> GPI8 EXTSMI#_3A <27>
IDE_PDD13 AE15 AG2 SATA_ICH_TXN0 W6 R786
DD_13 SATA_0TXN SMBALERT#/GPIO11 LID_ICH#_3A <20,43>
IDE_PDD12 AC13 AF2 SATA_ICH_TXP0 R72 1 2 0Ohm P2 M2 8.2KOhm
DD_12 SATA_0TXP <24,27,33,36> LPC_AD0 LAD_0/FWH0 GPI12 KBDSCI_3 <27>
IDE_PDD11 AB13 AC5 R68 1 2 0Ohm N3 R6 BAT1_LLOW#_ICH6 /*
<24,27,33,36> LPC_AD1 BAT1_LLOW#_ICH6 <20>

2
IDE_PDD10 DD_11 SATA_1RXN LAD_1/FWH1 GPI13
AB12 DD_10 SATA_1RXP AD5 1 0Ohm 2 RN61A <24,27,33,36> LPC_AD2
R63 1 2 0Ohm N5 LAD_2/FWH2 STP_PCI#/GPO18 AC21 STP_PCI# <21>
IDE_PDD9 AF13 AF4 R64 1 2 0Ohm N4 AB21 SB_GPIO19 1
DD_9 SATA_1TXN <24,27,33,36> LPC_AD3 LAD_3/FWH3 GPIO19
IDE_PDD8 T350
IDE_PDD7
AE13
AB11
DD_8 SATA_1TXP AG4
AD7
R1.1-S35 N6
STP_CPU#/GPO20 AD22
AD20
STP_CPU# <21,44>
DD_7 SATA_2RXN <20,24> LPC_DRQ#0 LDRQ_0# GPIO21 BACK_OFF# <15,20>
IDE_PDD6 AD11 AC7 3 4 RN61B R74 1 2 0Ohm P3 AD21
DD_6 SATA_2RXP 0Ohm <24,27,33,36> LPC_FRAME# LFRAME#/FWH4 GPIO23 FWH_WP# <20,36> CHECK_MODE <40>
IDE_PDD5 AC11 AF6 2 1 V3
DD_5 SATA_2TXN GPIO24 CB_SD# <20,32>
IDE_PDD4 C22 10PF /*
IDE_PDD3
AE14
AD12
DD_4 SATA_2TXP AG6
AC9 Azalia_BCLK_R 1 2 C10
GPIO25 P5
R3
ICH6_1HZ <40> R2.0-S09
DD_3 SATA_3RXN ACZ_BIT_CLK GPIO27 PCB_VID0 <20>
IDE_PDD2 AF14 AD9 5 6 RN61C Azalia_RST# R32 1 2 0Ohm A10 T3
DD_2 SATA_3RXP 0Ohm ACZ_RST# GPIO28 PCB_VID1 <20>
IDE_PDD1 AF15 AF8 R31 0Ohm F11 AF19
DD_1 SATA_3TXN <37> Azalia_SDIN0 ACZ_SDIN_0 CLKRUN#/GPIO32 PM_CLKRUN# <20,24,27,31,32>
IDE_PDD0 AD14 AG8 7 8 RN61D F10 AF20 XIDE_EN#_3
DD_0 SATA_3TXP 0Ohm <39> Azalia_SDIN1 ACZ_SDIN_1 GPIO33 XIDE_EN#_3 <22>
B10 ACZ_SDIN_2 GPIO34 AC18 OP_SD# <20,38>
<20> Azalia_SDOUT 1 2 C9 ACZ_SDOUT CPUPWRGD/GPIO49 AG25 H_PWRGD <4>
R29 2 0Ohm
SATA_CLKN AC2
AC1
CLK_PCIE_SATA# <21> <20> Azalia_SYNC
R30
1
0Ohm
B9
E10
ACZ_SYNC R1.1-S22
SATA_CLKP CLK_PCIE_SATA <21> <21> CLK_ICH14 CLK14

<22> IDE_PDDACK# AB15 DDACK#


AB14 AG11 R122
<22> IDE_PDDREQ DDREQ SATARBIAS#
<22> IDE_PDIOR# AE16 DIOR# SATARBIAS AF11 1 2 1 D12 EE_CS
AC14 T219 F13
<22> IDE_PDIOW# DIOW# EE_DIN
AF16 24.9Ohm D11
<22> IDE_PIORDY IORDY <20> EEP_DOUT EE_DOUT
1% B12 EE_SHCLK

R1.1-S22 EE_DOUT: Internal weak pull up AG21


MCH_SYNC# MCH_SYNC# <20>
<22> IDE_PDA0 AC16 DA0 EE_CS: Internal weak pull down F12 LAN_CLK PWRBTN# U1 PM_PWRBTN# <43>
<22> IDE_PDA1 AB17 DA1 B11 LAN_RSTSYNC RI# T2 PM_RI# <20>
C
<22> IDE_PDA2 AC17 DA2 E12 LAN_RXD_0
C
E11 LAN_RXD_1
C13 LAN_RXD_2
SMBCLK Y4 SCL_3A <20,28> C12 LAN_TXD_0
<22> IDE_PDCS1# AD16 DCS1# SMBDATA W5 SDA_3A <20,28> C11 LAN_TXD_1 SLP_S3# T4 PM_SUSB# <4,21,29,32,37,40,43,48,52>
<22> IDE_PDCS3# AE17 DCS3# E13 LAN_TXD_2 SLP_S4# T5 PM_SUSC# <43,52>
SLP_S5# T6 1
H_CPUSLP# R94 : B STEP NO STUFF T229

H_DPRSTP# R95 : A STEP NO STUFF


<20,22> INT_IRQ14 AB16 IDEIRQ SATA[x]GP pins if unused require PM_SUS_STAT# <20,24>
8.2-k to 10-k pull-up to Vcc3_3. <27> HA20GATE AF22 A20GATE
<4> H_A20M# AF23 A20M#
R197 1 /* 2 0Ohm AE27 1 T230
<4,7> H_CPUSLP# CPUSLP#
<44> PM_DPRSLPVR AE20 DPRSLPVR/TP_1 SUS_STAT#/LPCPD# W3 AUXPWROK <43>
Y5 R420 1 /* 2 0Ohm AE24
LINKALERT# LINKALERT# <20> <4> H_DPRSTP# DPRSLP#/TP_2
W4 AD27 V6 SUSCLK 1 2
SMLINK_0 SM_LINK0 <20,28> <4> H_DPSLP# DPSTP# SUSCLK +3VSUS
U6 AG26 10KOhm R78
SMLINK_1 SM_LINK1 <20,28> +3VS <4> H_IGNNE# IGNNE#
56Ohm AE22 U2 1 /* 2
<36> FWH_INIT# INIT3_3V# SYS_RESET# H_DBRESET# <4,6>
R1.1-S22 R4231 2 <4> H_INIT# AF27 0Ohm R81
+3VS +VCCP INIT# LAN_RST#
SATALED# AC19 SATALED# <22> <4> H_INTR AG24 INTR LAN_RST# V5 1 2 BUF_PLT_RST# <6,8,18,22,24,27,36>
SATA_0GP/GPI26 AF17 R123 1 2 8.2KOhm <4> H_FERR#
R422 1 2 56Ohm AF24 FERR#
R87 0Ohm
SATA_1GP/GPI29 AE18 PCB_VID2 <20> <4> H_NMI AF25 NMI BATLOW# V2 PM_BATLOW# <20>
SATA_2GP/GPI30 AF18 R124 1 2 <27> KBDCPURST AD23 RCIN#
AG18 8.2KOhm AB20 U3
SATA_3GP/GPI31 ACIN_OC_3 <27> <20,24,27,32> INT_SERIRQ SERIRQ TP_3 TP3 <20>
AA3 R111 2 1 1MOhm AG27
INTRUDER# +VCC_RTC <4> H_SMI# SMI#
<4> H_STPCLK# AE26 STPCLK# 2 1 BAT_LLOW#_OC <51>
2 1 AE23 R84 /* 0Ohm R2.0-S07
<6> H_THRMTRIP# THRMTRIP#
Y3 R126
RSMRST# PM_RSMRST# <43>
56Ohm R85 1 2 10KOhm

Y1 RTC_X1
RTCX1 ICH6_PWROK
VRMPWRGD AF21

THRM# AC20 PM_THRM# <20,35>


Y2 RTC_X2
RTCX2
B +VCC_RTC B

R1.1 _ NO17
1

AA2 RTC_RST#
RTCRST# R106
1 2 +3VSUS
AA5 R391 10KOhm
INTVRMEN 20KOhm
1 2
2

R390 0Ohm
/* R75
SPKR F8 ICH_SPKR <20,37>
U5 1KOhm 2 1
WAKE# +3VSUS
1

C141
1

AA1 ICH6_PWROK
PWROK ICH6_PWROK <8,43>
JRST1 1UF/10V
R1.1-S34
1

ICH6_M SGL_JUMP X7R


2

02-010004402 /*
2

R86
10MOhm
1 2 RTC CMOS CLEAR ICH6_M
02-010004402
(RTC_CLR)
RTC_X1 RTC_X2
1

Y1
1

2
1

C131
15P C130 BATSEL_2P
SIDE

15P
2

3
D
32.768KHZ CITIZEN 12.5PF/20PPM
<48,51> BAT1_LLOW# 2 1 BAT1_LLOW#_ICH6
3

07-010303271 +3VALWAYS +VCC_RTC Q9


D7 T35 1
D10 <49,50> BATSEL_2P# 2N7002
RB751V_40 G
A U36 2 2 S /* A
1

R130
NC1 3 3
1 RTC_BAT 2 1 1
SPKL-
R2.0-S03 GND SPKL+ 2
4 C340 1KOhm RB715F
NC2
1

WtoB_2P C147
0.1UF
2

/* 1UF/10V

CON Part Number Modify as ME Title : ICH6M--SATA/LPC/IDE/PM (1)


Engineer: Sam Wang
RTC BAT ASUSTECH CO.,LTD.
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 17 of 57
5 4 3 2 1
5 4 3 2 1

D D

U15A
PCI_AD[0..31] <29,31,32> U15B
E1 E2 PCI_AD0
<29,31,32> PCI_PAR PAR AD_0
C3 E5 PCI_AD1 T25 C21
<20,29,31,32> PCI_DEVSEL# DEVSEL# AD_1 <8> DMI_RXN0 DMI_0RXN USBP_0N USB_PN0 <23>
G6 C2 PCI_AD2 T24 D21
<21> CLK_ICHPCI PCICLK AD_2 <8> DMI_RXP0 DMI_0RXP USBP_0P USB_PP0 <23>
PCI_RST#_ICH R2 F5 PCI_AD3 R27 A20
PCIRST# AD_3 <8> DMI_TXN0 DMI_0TXN USBP_1N USB_PN1 <23>
PLT_RST#_SB R5 F3 PCI_AD4 R26 B20
PLTRST# AD_4 <8> DMI_TXP0 DMI_0TXP USBP_1P USB_PP1 <23>
A3 E9 PCI_AD5 V25 D19
<20,29,31,32> PCI_IRDY# IRDY# AD_5 <8> DMI_RXN1 DMI_1RXN USBP_2N USB_PN2 <26>
P6 F2 PCI_AD6 V24 C19
<20,29> PME_SB# PME# AD_6 <8> DMI_RXP1 DMI_1RXP USBP_2P USB_PP2 <26>
G5 D6 PCI_AD7 U27 A18
<20,29,31,32> PCI_SERR# SERR# AD_7 <8> DMI_TXN1 DMI_1TXN USBP_3N USB_PN3 <23>
J1 E6 PCI_AD8 U26 B18
<20,29,31,32> PCI_STOP# STOP# AD_8 <8> DMI_TXP1 DMI_1TXP USBP_3P USB_PP3 <23>
C5 D3 PCI_AD9 Y25 E17
<20> PCI_LOCK# PLOCK# AD_9 <8> DMI_RXN2 DMI_2RXN USBP_4N USB_PN4 <23>
J2 A2 PCI_AD10 Y24 D17
<20,29,31,32> PCI_TRDY# TRDY# AD_10 <8> DMI_RXP2 DMI_2RXP USBP_4P USB_PP4 <23>
E3 D2 PCI_AD11 W27 B16
<20,29,31,32> PCI_PERR# PERR# AD_11 <8> DMI_TXN2 DMI_2TXN USBP_5N USB_PN5 <31>
J3 D5 PCI_AD12 W26 A16
<20,29,31,32> PCI_FRAME# FRAME# AD_12 <8> DMI_TXP2 DMI_2TXP USBP_5P USB_PP5 <31>
H3 PCI_AD13 AB24 C15
AD_13 <8> DMI_RXN3 DMI_3RXN USBP_6N
B4 PCI_AD14 AB23 D15
AD_14 <8> DMI_RXP3 DMI_3RXP USBP_6P
J5 PCI_AD15 AA27 A14
AD_15 <8> DMI_TXN3 DMI_3TXN USBP_7N
K2 PCI_AD16 AA26 B14
AD_16 <8> DMI_TXP3 DMI_3TXP USBP_7P
C1 K5 PCI_AD17
<29> PCI_GNT#0 GNT_0# AD_17
B6 D4 PCI_AD18
<32> PCI_GNT#1 GNT_1# AD_18
1PCI_GNT#2 F1 GNT_2# AD_19 L6 PCI_AD19
OC_0# C27
T222 C8 G3 PCI_AD20 B27
<31> PCI_GNT#3 GNT_3# AD_20 OC_1# USB_OC#01 <23>
1 E7 H4 PCI_AD21 B26
T221 GNT_4#/GPIO48 AD_21 PCI_AD22 OC_2#
<20> GPIO17 F6 GNT_5#/GPIO17 AD_22 H2 OC_3# C26 USB_OC#23 <23>
D8 H5 PCI_AD23 C23
<20> GPIO16 GNT_6#/GPIO16 AD_23 OC_4#/GPIO9 USB_OC#4 <20>
B3 PCI_AD24 D23
AD_24 OC_5#/GPIO10 USB_OC#5 <20>
M6 PCI_AD25 H25 C25 BAT2_LLOW#_ICH6
AD_25 HSIN_0 OC_6#/GPIO14 BAT2_LLOW#_ICH6 <20>
B2 PCI_AD26 H24 C24
AD_26 HSIP_0 OC_7#/GPIO15 GPIO15 <20>
K6 PCI_AD27 1 G27
AD_27 PCI_AD28 T23 HSON_0
<20,29> PCI_REQ#0 L5 REQ_0# AD_28 K3 1 G26 HSOP_0
B5 A5 PCI_AD29 T21 K25
<20,32> PCI_REQ#1 REQ_1# AD_29 HSIN_1
M5 L1 PCI_AD30 K24 B22 USBRBIAS R26
<20> PCI_REQ#2 REQ_2# AD_30 HSIP_1 USBRBIAS
B8 K4 PCI_AD31 1 J27 A22 1 2
<20,31> PCI_REQ#3 REQ_3# AD_31 HSON_1 USBRBIAS#
C F7 T24 1 J26 C
<20> PCB_VID3 REQ_4#/GPIO40 HSOP_1
E8 T225 M25 22.6Ohm
<20,27> KBDDT1 REQ_5#/GPIO1 HSIN_2
B7 M24 1%
<20,27> KBDDT0 REQ_6#/GPIO0 HSIP_2
1 L27 HSON_2
T227 1 L26
T226 HSOP_2
P24 HSIN_3 PLACE within
<20,32> PCI_INTA# N2 P23
L2
PIRQA#
1 N27
HSIP_3 500 mils of
<20,31,32> PCI_INTB# PIRQB# HSON_3
M1 T32 1 N26 ICH.
<20,29,32> PCI_INTC# PIRQC# HSOP_3
L3 T29
<20,31> PCI_INTD# PIRQD#
<20> PCI_INTE# D9 PIRQE#/GPIO2
C7 +1.5VS
<20> PCI_INTF# PIRQF#/GPIO3
C6 R360 F24 A27
<20> PCI_INTG# PIRQG#/GPIO4 DMI_ZCOMP CLK48 CLK_USB48 <21>
<20> PCI_INTH# M3 PIRQH#/GPIO5 C_BE_3# G2 PCI_C/BE#3 <29,31,32> 1 2 F23 DMI_IRCOMP
C_BE_2# G4 PCI_C/BE#2 <29,31,32>
H6 24.9Ohm
C_BE_1# PCI_C/BE#1 <29,31,32>
C_BE_0# J6 PCI_C/BE#0 <29,31,32>

PLACE within 500 mils of ICH.

+3V

2
<21> CLK_PCIE_ICH# AD25 DMI_CLKN
U42B C375
14

<21> CLK_PCIE_ICH AC25 DMI_CLKP

1
VCC 4 0.1UF
U42C

14
6 ICH6_M
5 02-010004402
GND VCC 9 PCI_RST#_ICH ICH6_M
LV08A 8 02-010004402
<22,29,31,32> PCI_RST#
7

B
10 B
GND
LV08A

+3V 7

+3V
+3V
1

C443
0.1UF U42D
14
2

VCC 12 PLT_RST#_SB
<6,8,17,22,24,27,36> BUF_PLT_RST# 11
13 Can be issue SCI or SMI List: GPIO0~GPIO15
U45 GND Resume Power Well GPIO List: GPIO8,11,13,14,15,24,25,27,28
PCI_RST# 1 B 5 LV08A
7

VCC
1

<27> SET_PCIRSTNS# 1 2 2 A C376 Only GPI Pin: GPI0~8,11~15,26,29,30,31,40(5V),41


R435 10KOhm
Only GPO Pin: GPIO16~17,19,21,23,48
2

3 GND 4 0.01UF
PCI_RSTNS# <27>
1

C445 Y /* Can be GPIO: GPIO24,25,27,28,33,34


R434 74LVC1G32GV
2

47KOhm 0.01UF Resume Power Input Pin List:


BATLOW#,AC_SDIN[0:1],LAN_RST#,
2

OC[7:0]#,PME#,PWRBTN#,RI#,SMBALERT#,SYS_RESET#,USBRBIAS#

A A
D32

<48,51> BAT2_LLOW# 2 1 BAT2_LLOW#_ICH6

RB751V_40

Title : ICH6M--PCI/DMIUSB/PCIE (2)


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 18 of 57
5 4 3 2 1
5 4 3 2 1

ICH6_CORE U15E
V5REF U15F
+1.5VS AA19 VCC1_5_21 V5REF1 A8
AA20 VCC1_5_22 V5REF2 AA18 A1 VSS1 VSS87 G21

1
Place 0.01uF C408 C369 C403 C374 C399 AA21 A12 G7
VCC1_5_23 VSS2 VSS88
L11 AB18 +2.5VS_PCI_IDE A15 G9
within 100mils 0.01UF 0.1UF 0.1UF 0.1UF 0.1UF L12
VCC1_5_24 VCC2_5_1
P7 A19
VSS3 VSS89
H23
+2.5VS

2
VCC1_5_25 VCC2_5_2 VSS4 VSS90
D of ICH near pin L14 VCC1_5_26 A21 VSS5 VSS91 H26 D
L16 A23 H27
AA19 VCC1_5_27 VSS6 VSS92

1
Place 4X0.1uF L17 C411 A26 J23
VCC1_5_28 V5REF_SUS VSS7 VSS93
M11 F21 A4 J24
Distribute near M17
VCC1_5_29 V5REF_SUS 0.1UF A7
VSS8 VSS94
J25

2
VCC1_5_30 VSS9 VSS95
pin ICH6 P11 VCC1_5_31 A9 VSS10 VSS96 J4
P17 AA11 K1
Package edge T11
VCC1_5_32
AA13
VSS11 VSS97
K23
VCC1_5_33 VSS12 VSS98
T17 VCC1_5_34 AA16 VSS13 VSS99 K26
U11 VCC1_5_35 AA4 VSS14 VSS100 K27
U12 VCC1_5_36 AB1 VSS15 VSS101 K7
U14 VCC1_5_37 AB10 VSS16 VSS102 L13
Place BOTH U16 VCC1_5_38 AB19 VSS17 VSS103 L15
U17 AB2 L23
within 100mils of G8
VCC1_5_39
AB7
VSS18 VSS104
L24
VCC1_5_40 VSS19 VSS105
ICH near pin D27 D24 VCC1_5_41 AB9 VSS20 VSS106 L25
D25 VCC1_5_42 AC10 VSS21 VSS107 M12
D26 VCC1_5_43 AC12 VSS22 VSS108 M13
USB_CORE D27 AC22 M14
VCC1_5_44 VSS23 VSS109
E20 VCC1_5_45 AC23 VSS24 VSS110 M15

1
C392 C386 E21 L32 AC24 M16
VCC1_5_46 VCCDPLL VSS25 VSS111
E22 VCC1_5_47 1 2 +1.5VS AC26 VSS26 VSS112 M23
0.1UF 0.1UF E23 AC3 M26

2
VCC1_5_48 120Ohm/100Mhz VSS27 VSS113
E24 VCC1_5_49 AC6 VSS28 VSS114 M27

1
F20 C133 AD1 M4
VCC1_5_50 C126 VSS29 VSS115
G20 VCC1_5_51 AD10 VSS30 VSS116 N1
F9 0.01UF 10UF/10V AD15 N11

2
VCC1_5_52 VSS31 VSS117
AD18 VSS32 VSS118 N12
AD2 VSS33 VSS119 N13
AB22 +1.5VS AD24 N14
+VCCP V_CPU_IO_1 VSS34 VSS120
AD26 AC27 AD6 N15

1
C423 V_CPU_IO_2 VCCDMIPLL VSS35 VSS121
AG23 V_CPU_IO_3 AE10 VSS36 VSS122 N16
Place 0.1uF within 100mils AE1 +1.5VS_SATAPLL AE11 N17
0.1UF VCCSATAPLL VSS37 VSS123

2
AE12 N7
of ICH near pin AG23 A25 +1.5VS_USBPLL AE2
VSS38 VSS124
P12
VCCUSBPLL VSS39 VSS125
AE21 VSS40 VSS126 P13
+3VS AA22 AE25 P14
VCCDMIPWR1 +1.5VS VSS41 VSS127
PCI_IDE_CORE VCCDMIPWR2 AA23 AE6 VSS42 VSS128 P15
C AA12 VCC3_3_1 VCCDMIPWR3 AA24 AE7 VSS43 VSS129 P16 C

1
AA14 VCC3_3_2 VCCDMIPWR4 AA25 + AF1 VSS44 VSS130 P22

1
C393 C159 C54 AA15 AB25 CE7 C157 C156 C415 AF12 R11
C158 0.1UF VCC3_3_3 VCCDMIPWR5 VSS45 VSS131
AA17 VCC3_3_4 VCCDMIPWR6 AB26 AF26 VSS46 VSS132 R12
10UF/10V 0.1UF 0.1UF AC15 AB27 150U/4.0V 0.1UF 0.1UF 0.1UF AF3 R13

2
VCC3_3_5 VCCDMIPWR7 VSS47 VSS133
Place 0.1uFx1 near AG10 AD17 VCC3_3_6 VCCDMIPWR8 F25 AF7 VSS48 VSS134 R14
AG13 F26 AG1 R15
Place 0.1uFx1 near E26, E27 AG16
VCC3_3_7 VCCDMIPWR9
F27 /*
Place 150uF, 3 X 0.1uF AG12
VSS49 VSS135
R16
VCC3_3_8 VCCDMIPWR10 VSS50 VSS136
Place 0.1uFx2 near AG13, AG16 AG19 VCC3_3_9 VCCDMIPWR11 G22
within 100mils of ICH near
AG14 VSS51 VSS137 R17
A6 G23 AG17 R23
Place 0.1uFx3 near A2~A6, D1~H1 B1
VCC3_3_10 VCCDMIPWR12
G24 pin F27, P27, AB27 AG20
VSS52 VSS138
R24
VCC3_3_11 VCCDMIPWR13 VSS53 VSS139
E4 VCC3_3_12 VCCDMIPWR14 G25 AG22 VSS54 VSS140 R25
+5VS +3VS H1 H21 AG3 R4
VCC3_3_13 VCCDMIPWR15 VSS55 VSS141
1

1
C426 C381 C416 C412 H7 H22 AG7 T1
VCC3_3_14 VCCDMIPWR16 VSS56 VSS142
J7 VCC3_3_15 VCCDMIPWR17 J21 B13 VSS57 VSS143 T12
2

D2 0.1UF 0.1UF 0.1UF 0.1UF L4 J22 B15 T13


2

2
R28 VCC3_3_16 VCCDMIPWR18 VSS58 VSS144
L7 VCC3_3_17 VCCDMIPWR19 K21 B19 VSS59 VSS145 T14
M7 VCC3_3_18 VCCDMIPWR20 K22 B21 VSS60 VSS146 T15
100Ohm F01J4L P1 L21 B23 T16
VCC3_3_19 VCCDMIPWR21 VSS61 VSS147
+3.3VS_LAN E26 L22 B25 T23
1

VCC3_3_20 VCCDMIPWR22 VSS62 VSS148


+3VS 1 2 AA10 VCC3_3_21 VCCDMIPWR23 M21 C14 VSS63 VSS149 T26
V5REF R34 0Ohm AG10 M22 C18 T27
VCC3_3_22 VCCDMIPWR24 VSS64 VSS150
1

N21 C20 T7
1

C372 C36 VCCDMIPWR25 VSS65 VSS151


Place near PIN A13 VCCDMIPWR26 N22 C22 VSS66 VSS152 U13
1

C38 C34 0.1UF 0.1UF A13 N23 C4 U15


2

VCCSUS3_3_1 VCCDMIPWR27 VSS67 VSS153


2

F14 VCCSUS3_3_2 VCCDMIPWR28 N24 D1 VSS68 VSS154 U23


1UF/10V 0.1UF G13 N25 D10 U24
2

VCCSUS3_3_3 VCCDMIPWR29 VSS69 VSS155


G14 VCCSUS3_3_4 VCCDMIPWR30 P21 D13 VSS70 VSS156 U25
Place near PIN A8 1 2 +VCCPSUS A11 P25 R27 D14 V23
+3VSUS VCCSUS3_3_5 VCCDMIPWR31 VSS71 VSS157
R33 0Ohm U4 P26 +1.5VS_USBPLL 1 2 D18 V26
1

C35 VCCSUS3_3_6 VCCDMIPWR32 +1.5VS VSS72 VSS158


V1 VCCSUS3_3_7 VCCDMIPWR33 P27 D20 VSS73 VSS159 V27
Place near PIN V7 V7 R21 0Ohm D22 V4
0.1UF VCCSUS3_3_8 VCCDMIPWR34 VSS74 VSS160

1
C37
2

W2 VCCSUS3_3_9 VCCDMIPWR35 R22 D7 VSS75 VSS161 W1


Y7 VCCSUS3_3_10 VCCDMIPWR36 T21 E14 VSS76 VSS162 W23
A17 T22 0.01UF E15 W25

2
+3.3VA_ICH VCCSUS3_3_11 VCCDMIPWR37 VSS77 VSS164
+3VSUS 1 2 B17 VCCSUS3_3_12 VCCDMIPWR38 U21 E18 VSS78 VSS165 W7
R35 0Ohm C16 U22 E19 Y23
1

C373 VCCSUS3_3_13 VCCDMIPWR39 VSS79 VSS166


1

B
C17 VCCSUS3_3_14 VCCDMIPWR40 V21 E25 VSS80 VSS167 Y26 B
+5VSUS +3VSUS C40
Place BOTH within 100mils of 0.1UF D16 VCCSUS3_3_15 VCCDMIPWR41 V22 F17 VSS81 VSS168 Y27
0.1UF
2

E16 W21 F19 Y6


2

ICH near pin A17 F15


VCCSUS3_3_16 VCCDMIPWR42
W22 F22
VSS82 VSS169
W24
VCCSUS3_3_17 VCCDMIPWR43 VSS83 VSS170
2

D1 F16 Y21 F4 E27


R36 VCCSUS3_3_18 VCCDMIPWR44 VSS84 VSS171
F18 VCCSUS3_3_19 VCCDMIPWR45 Y22 G1 VSS85 VSS172 B24
+3.3VA_ICH G15 +1.5VS_SATA G12 AF10
10Ohm F01J4L VCCSUS3_3_20 VSS86 VSS173
G16 AA6
1

+VCC_RTC C366 VCCSUS3_3_21 VCC1_5_1 +1.5VS


G17 AB4
1

ICH6_M
1

C413 VCCSUS3_3_22 VCC1_5_2


1

0.1UF G18 VCCSUS3_3_23 VCC1_5_3 AB5

1
V5REF_SUS C414 C391
2

0.1UF A24 VCCSUS3_3_24 VCC1_5_4 AB6


0.1UF Place within 1.5VS: 2.355A Power Seq.
2

AC4
2

VCC1_5_5 0.1UF
AD4 2.5VS: 15mA +1.8V rise time < 2ms

2
VCC1_5_6 100mils of ICH
1

C32 C370 AB3 AE4


VCCRTC VCC1_5_7 3VS: 243mA +1.5VS --> +VCCP
VCC1_5_8 AE5 near pin AG5
1UF/10V 0.1UF R7 AG5 3VSUS: 23mA +5VS --> +3VS --> +2.5VS
2

VCCSUS1_5_A VCC1_5_9
AF5
R1.1-S28
1

C401 VCC1_5_10 1.5VSUS: 170mA +5VSUS --> +3VSUS --> +1.5VSUS


1

C404 U7 AA7
VCCSUS1_5_B VCC1_5_11
0.1UF VCC1_5_12 AA8 5VSUS: 10mA
Place near PIN A8 0.1UF +1.5VA_USB G19 VCCRTC --> RTCRST# > 5ms
2

AA9 VCCP: 14mA


2

VCCSUS1_5_C VCC1_5_13
VCC1_5_14 AB8 Place within +3VALWAYS --> RSMRST# > 5ms

1
G10 AC8 C400 RTC: 5uA
R365 VCCSUS1_5_D VCC1_5_15
AD8 100mils of ICH +3VALWAYS --> LAN_RST# > 10ms
+1.5VS_LAN VCC1_5_16 0.1UF
+1.5VS 1 2 G11 AE8 near pin AG9 +3VS(LAN) --> LAN_RST# > 10ms

2
VCCSUS1_5_E VCC1_5_17
AE9
0Ohm 2 1
VCC1_5_18
AF9
+3VS,+1.5VS --> PWROK,PM_VATE > 99ms
/* C377 0.1UF VCC1_5_19
VCC1_5_20 AG9
ICH6_M
02-010004402

A A

Title : ICH6M--PWR/GND(3)
ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 19 of 57
5 4 3 2 1
5 4 3 2 1

D +3VS D

1 RP1A +3VS
<18,29,31,32> PCI_FRAME# 8.2KOhm5
10 INTERNAL PULL-DOWN
2 RP1B PULL-UP : PCI Express +3VS
<18,29,31,32> PCI_IRDY# 8.2KOhm5
10 Port config bit 1
3 RP1C
<18,29,31,32> PCI_TRDY# 8.2KOhm5
10 R22 2 1 10KOhm R408 2 1 10KOhm
Azalia_SDOUT <17> <15,17> BACK_OFF#
4 RP1D /* /*
<18,29,31,32> PCI_STOP# 8.2KOhm5
10
6 RP1E
<18,29,31,32> PCI_SERR# 8.2KOhm5

1
10 +3VS R394 2 1 4.7KOhm
<17,24> PM_SUS_STAT#
7 RP1F C76 INTERNAL PULL-DOWN /*
<18,29,31,32> PCI_DEVSEL# 8.2KOhm5
10 PULL-UP : PCI Express

2
RP1G 0.1UF
<18,29,31,32> PCI_PERR# 8 8.2KOhm5 Port config bit 0
10 <17,24> LPC_DRQ#0 2 1 8.2KOhm
9 RP1H R15 10KOhm R371 /*
<18> PCI_LOCK# 8.2KOhm5 2 1 Azalia_SYNC <17>
10 /*
1 RP7A
<17,24,27,32> INT_SERIRQ 8.2KOhm5
10
2 RP7B
<17,35> PM_THRM# 8.2KOhm5
10
3 RP7C R393 2 10KOhm
<18,29> PCI_REQ#0 8.2KOhm5 1 TP3 <17>
10 /*
4 RP7D INTERNAL PULL-UP
<18,32> PCI_REQ#1 8.2KOhm5
10 PULL-DOWN : PCI 2 1
<17,36> FWH_WP#
6 RP7E Express Port chain R415 100KOhm
<18> PCI_REQ#2 8.2KOhm5
10 test <17,38> OP_SD# 2 1
7 RP7F R416 10KOhm
<18,31> PCI_REQ#3 8.2KOhm5
10
8 RP7G
<17> GPI7 8.2KOhm5
10
9 RP7H +3VS
8.2KOhm5
10
1 RP2A INTERNAL PULL-DOWN
<18,31> PCI_INTD# 8.2KOhm5
10 PULL-UP : NO REBOOT
2 RP2B
<18,29,32> PCI_INTC# 8.2KOhm5 R368
C 10 C
3 RP2C
<18,32> PCI_INTA# 8.2KOhm5 2 1 ICH_SPKR <17,37>
10
4 RP2D 1KOhm /*
<18,31,32> PCI_INTB# 8.2KOhm5
10
6 RP2E
8.2KOhm5 R356
10
7 RP2F
8.2KOhm5 2 1 EEP_DOUT <17>
10
8 RP2G 1KOhm /*
<17> MCH_SYNC# 8.2KOhm5
10
9 RP2H INTERNAL PULL-UP
<17> BATSEL_2P 8.2KOhm5
10 PULL-DOWN :
RESERVED
+3VSUS
R359 R1.1-S21 +3VSUS +3VSUS
2 1 GPIO17 <18>
1 RP6A 1KOhm /*
10KOhm5
10

1
2 RP6B INTERNAL PULL-UP R59 R66 R120 R787
<17> PM_RI# 10KOhm5
10 PULL-DOWN : Boot BIOS
3 RP6C destination select
<18> GPIO15 10KOhm5
10 100KOhm 100KOhm 100KOhm 100KOhm
RP6D R347 /*
<17,43> LID_ICH#_3A 4 10KOhm5

2
10 2 1 PCB_VID0
GPIO16 <18> <17> PCB_VID0
6 RP6E PCB_VID1 Z61Ae
<18> USB_OC#4 10KOhm5 <17> PCB_VID1
10 1KOhm /* PCB_VID2
<17> PCB_VID2
7 RP6F PCB_VID3
<18> USB_OC#5 10KOhm5 <18> PCB_VID3
10 INTERNAL PULL-UP
8 RP6G PULL-DOWN
<17> BAT1_LLOW#_ICH6 10KOhm5

1
10 :TOP-BLOCK SWAP
9 RP6H R60 R65 R121 R361
<18> BAT2_LLOW#_ICH6 10KOhm5
10 10KOhm 10KOhm 10KOhm 10KOhm
PCB_VID 2 1 0 /* /*
+3VSUS Z61A

2
B
MB V1.0 0 0 0 B
MB V1.1 0 0 1 /*
INTERNAL PULL-DOWN SIGNALS : MB V1.2 0 1 0
<17> LINKALERT# 2 1 MB V2.0 0 1 1 (V)
R402 10KOhm PCB_VID3 : PROJECT CODE
<17,28> SCL_3A 2 1 AC_BITCLK, AC_RST# , AC_SDIN[2:0] , 1 = Z61Ae (V)
R400 2.2KOhm
AC_SDOUT , AC_SYNC , DPSLPVR , 0 = Z61A
2 1
LAN_CLK , PDD[7] , PDDREQ , SPKR ,
<17,28> SDA_3A
USB[7:0][P,N]
R401 2.2KOhm

1 2 RN4A
<17,28> SM_LINK0 10KOhm
3 4 RN4B INTERNAL PULL-UP SIGNALS :
<17,28> SM_LINK1 10KOhm
5 6 RN4C
<17> PM_BATLOW# 10KOhm
7 8 RN4D EE_DIN , EE_DOUT , EE_CS ,
<17,32> CB_SD# 10KOhm
GPIO[17:16] , LAD[3:0]# ,
LDRQ[0:1] , LAN_RXD[2:0] ,
<18,29> PME_SB# 2 1 PME# , PWRBTN# , TP3 ,
R378 10KOhm SATALED# ,
/* GNT[4:0]

+3VS

RP5A 1
<18,27> KBDDT0 8.2KOhm5
10
RP5B 2
<18,27> KBDDT1 8.2KOhm5
10
RP5C 3
<18> PCI_INTE# 8.2KOhm5
10
RP5D 4
<18> PCI_INTF# 8.2KOhm5
A 10 A
RP5E 6
<18> PCI_INTG# 8.2KOhm5
10
RP5F 7
<18> PCI_INTH# 8.2KOhm5
10
RP5G 8
<17,24,27,31,32> PM_CLKRUN# 8.2KOhm5
10
RP5H 9
<17,22> INT_IRQ14 8.2KOhm5
10

Title : ICH6M--PULL UP/STRAP (4)


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 20 of 57
5 4 3 2 1
5 4 3 2 1

R494 +3VS
R1.1-S32 L82
1 2 CLK_BSEL0 B STEP 120Ohm/100Mhz +3V_CLK PLACE termination close to clock gen.
<4> CPU_BSEL0
R254 1 2 +3V_CLK
1 0Ohm 2 CLK_BSEL1
<4> CPU_BSEL1

1
C557 C538 C533 C549 C548 C515 C517
0Ohm CPU_BSEL0 CPU_BSEL1 HOST CLOCK C543 C530
Install when B STEP CPU 0.1UF 0.1UF 10UF/10V 10UF/10V 0.47U 0.1UF 0.1UF 0.1UF 0.1UF CLK_CPU_BCLK R490 1 2 49.9Ohm

2
1%
0 0 133 CLK_CPU_BCLK# R489 1 2 49.9Ohm
CLK_STP_PCI# R523 1 2 0Ohm 1%
STP_PCI# <17>
CLK_STP_CPU# R500 1 2 0Ohm STP_CPU# <17,44>
1 0 100 CLK_MCH_BCLK R492 1 2 49.9Ohm
CPU1 R509 1 2 33Ohm 1%
CLK_CPU_BCLK <4>
CPU1# R508 1 2 33Ohm CLK_MCH_BCLK# R491 1 2 49.9Ohm
D CLK_CPU_BCLK# <4> D
1%
Because CPU output only 1.05V and NB CPU0 R511 1 2 33Ohm
+3VS +3VS +VCCP +VCCP CLK_MCH_BCLK <7>
CPU0# R510 1 2 33Ohm CLK_ITP_BCLK R488 1 2 49.9Ohm
R1.1-S06
is only input type,if we use 1K ohm CLK_MCH_BCLK# <7>
1% /*
will drop 1.05V to NB.May be not CLK_ITP_BCLK# R487 1 2 49.9Ohm
1

1
enough.Therefore,change to 0 ohm. ITP_BCLK R507 1 2 33Ohm /* 1% /*
CLK_ITP_BCLK <6>
R513 R257 R482 R258 R256 ITP_BCLK# R506 1 2 33Ohm /* R579
CLK_ITP_BCLK# <6>
10KOhm 10KOhm 0Ohm DREFCLK 1 2
1KOhm 1KOhm 1 2 R578
MCH_SEL1 <8>
/* /* DREFCLK# 1 49.9Ohm 2
2

2
CLK_BSEL1
PCIE5 R505 1 2 33Ohm 49.9Ohm
CLK_MCH_3GPLL <8>
CLK_BSEL0 PCIE#5 R504 1 2 33Ohm CLK_PCIE_ICH R575 1 2 49.9Ohm
CLK_MCH_3GPLL# <8>
1%
2

2
1 2 CLK_PCIE_ICH# R574 1 2 49.9Ohm
MCH_SEL0 <8>
R493 R255 0Ohm 1%
R514 +3VS
0Ohm 0Ohm PCIE3 R556 1 2 33Ohm CLK_MCH_3GPLL R486 1 2 49.9Ohm
CLK_PCIE_ICH <18>
/* /* PCIE#3 R555 1 2 33Ohm 1%
CLK_PCIE_ICH# <18>
1

2
CLK_MCH_3GPLL#R485 1 2 49.9Ohm
R580 1%
10KOhm R1.1-S22
SRCCLKT_SATA 1 R788 2 33Ohm CLK_PCIE_SATA R789 1 2 49.9Ohm
CLK_PCIE_SATA <17>
SRCCLKC_SATA 1 R790 2 33Ohm CLK_PCIE_SATA# <17>

1
CLK_PCIE_SATA# R791 1 2 49.9Ohm

R563 1 2 33Ohm USB/FSA R577


<18> CLK_USB48
DREFSSCLK 1 2
R576
DREFSSCLK# 1 49.9Ohm 2
R1.1-S02
49.9Ohm
R566 1 2 8.2Ohm 33PCIF5
<29> CLK_LANPCI
R567 1 2 5.1Ohm
<32> CLK_CBPCI
R568 1 2 33Ohm 33PCIF4
<33> CLK_DBPCI
R553 1 2 5.1Ohm 33PCIF3
<27> CLK_KBCPCI
C R552 1 2 5.1Ohm C
<24> CLK_SIOPCI
R522 1 2 27Ohm 33PCIF2
<31> CLK_MINIPCI
R570 1 2 33Ohm 33PCIF1
<36> CLK_FWHPCI
R565 1 2 33Ohm 33PCIF0
<18> CLK_ICHPCI
ICS ICS954206 FREQUENCY TABLE
+3VS
CPU SRC PCI REF USB DOT
FS_C FS_B FS_A MHz MHz MHz MHz MHz MHz
C554

C559

C560

C561

C545

C551

C508

C556

C558

2
R560
2

R564 R569 DOT96 1 R559 2 0 0 0 266 100 33.33 14.318 48.00 96.00
DREFCLK <8>
10KOhm 10KOhm DOT96# 1 2 DREFCLK# <8> V 0 0 1 133 100 33.33 14.318 48.00 96.00
5PF

5PF

5PF

5PF

5PF

5PF

5PF

5PF

5PF

33Ohm
1

33Ohm 0 1 0 200 100 33.33 14.318 48.00 96.00


1

1
/* /* /* /* /* /* /* /* /* CLK_PWR_GD#
CLK_PWR_GD# <44> 0 1 1 166 100 33.33 14.318 48.00 96.00
10-k pull-up to +3VS 10-k pull-up to +3VS
define pin35 36 as ITP CLK define pin17 18 as 100MHz
R1.1-S02 1 0 0 333 100 33.33 14.318 48.00 96.00
REFO 1 R520 2 22Ohm
10-k pull-down to gnd 10-k pull-down to gnd CLK_ICH14 <17> 1 0 1 100 100 33.33 14.318 48.00 96.00
define pin35 36 as SRC CLK define pin17 18 as 96MHz
1 R519 2 22Ohm
CLK_SIO14 <24> 1 1 0 400 100 33.33 14.318 48.00 96.00
1 1 1

C506

C505
reserved 14.318 48.00 96.00
Clock Gen. P/N:06-011295010 is an error part number.

2
+3VS
L81 And P/N:06-011338110 is right part number.

5PF

5PF
1 2
It is Green Part.(AP-106847 to change it.)

1
2

R1.1-S32 120Ohm/100Mhz
1Ohm
/* /*

R502 U54
+3.3VS_CLKVDD1 1 56 33PCIF2 R1.1-S29
1

VDDPCI0 PCICLK2 CLK_STP_PCI#


2 GND0 PCI/SRC_STOP# 55
1

C540 C550 C541 33PCIF3 3 54 CLK_STP_CPU# R709


PCICLK3 CPU_STOP#
2

33PCIF4 4 53 1 2 CLK_BSEL0 R1.1-S29 +3VALWAYS


0.1UF 0.1UF 0.1UF R571 33PCIF5 PCICLK4 REF1/FSLC/TEST_SEL REFO 10KOhm +3VS
5 52
2

B PCICLK5 REF0 +3VS B


6 GND1 GND3 51
2.2OHM 7 50 XIN_CLKGEN
VDDPCI1 X1

2
33PCIF0 8 49 XOUT_CLKGEN
1

ITP_EN/PCICLK_F0 X2

2
33PCIF1 VDD_REF_CR C518 2 0.1UF +3VSUS R247

10
9 48 1
R1.1-S32 CLK_PWR_GD# 10
11
SEL100_96MHZ#/PCICLK_F1 VDDREF
Vtt_PwrGd#/PD SDATA 47
46
SDA_3S <12,13,28,35>
R244
10KOhm 100KOhm 12
U29B
9

PR
VDD48 SCLK SCL_3S <12,13,28,35> D Q VCCA_1.8_EN <4>

2
USB/FSA 12 45 /*

1
FSLA/USB_48MHz GND4
1

C552 13 44 CPU0 R241 11 8 VCCA_1.8_EN# <4>

1
C555 0.1UF R792 DOT96 GND2 CPUCLKT0 CPU0# CLK_PWR_GD# CK Q#
14 DOTT_96MHz CPUCLKC0 43
0.1UF R1.1-S01 0Ohm DOT96# 15 42 20KOhm /* 3 7 14

CLR
2

CLK_BSEL1 R558 DOTC_96MHz VDDCPU CPU1 3 C Q32 GND VCC


1 2 16 41 D

1
R557 2 FSLB/TEST_MODE CPUCLKT1 CPU1# 1 B
<8> DREFSSCLK 1 17 96MHz_SST/SRCCLKT0 CPUCLKC1 40 PMBS3904
1 2 18 39 IREF R243 Q33 SN74LVC74APWR
<8> DREFSSCLK#

13
96MHz_SSC/SRCCLKC0 IREF

2
+3V_CLK 33Ohm 19 38 1 2 1 /* E
SRCCLKT1 GNDA <44,48> VRM_PWRGD 2N7002 2
R529 33Ohm 20 37 +3V_CLKA G R242
SRCCLKC1 VDDA 2 S
2

+3V_CLKA 2 1 21 36 ITP_BCLK 0Ohm /* /* PM_SUSB#


VDDSRC0 CPUCLKT2_ITP/SRCCLKT7 PM_SUSB# <4,17,29,32,37,40,43,48,52>
22 35 ITP_BCLK# R533 10KOhm
2.2OHM SRCCLKT2 CPUCLKC2_ITP/SRCCLKC7 /*
23 34

1
SRCCLKC2 VDDSRC2
1

2
C516 PCIE3 24 33 475Ohm C268
C511 PCIE#3 SRCCLKT3 SRCCLKT6 1%
25 32
1

0.1UF SRCCLKT_SATA SRCCLKC3 SRCCLKC6 PCIE5 /* 1000PF


10UF/10V R1.1-S22 26 31
2

1
SRCCLKC_SATA SRCCLKT4_SATA SRCCLKT5 PCIE#5 CLK_BSEL0
27 SRCCLKC4_SATA SRCCLKC5 30
28 VDDSRC1 GND5 29
/*
ICS954206
06-011338110
74HC74 TRUTH TABLE
P/N:06-011338110 PRE# CLR# CLK D Q Q'

L H X X H L
H L X X L H
X4
XOUT_CLKGEN 1 2 XIN_CLKGEN L L X X float float
A A
14.318MHZ H H T H H L
CITIZEN 20PF/30PPM
07-010311430 H H T L L H
H H L X Qo Qo'
R1.1-S43
1

C531 C525
33PF/50V 33PF/50V
Title : CLOCK ICS954206
2

ASUSTECH CO.,LTD. Engineer: Sam Wang


Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 21 of 57
5 4 3 2 1
5 4 3 2 1

R810 +3VS

Support Hot
10KOhm
2 /* 1 +3VS +1.8VS HDD CONNECTOR
+3VS +1.8VS
P/N:12-16150044N
SWAP

1
C768 C769 C770 C771 C772 +5VS

T351
T352
T353

T354
T355
T356
T357
+5VS
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF

2
R1.1-S22

1
1
1
1

1
1
1
1

1
C318 C302

IDE_BDCS0#
IDE_BDCS1#

STP_PIN39
STP_PIN38

STP_PIN36
STP_PIN35
STP_PIN34
STP_PIN33
R382 C59 C364 C316
L96 +1.8VS 10KOhm 10UF/10V 0.1UF 0.1UF 10UF/10V

2
120Ohm/100Mhz 0.1UF

ODCS

2
1 2

1
+3VS FOR SIL3811
C773 C774 C775

46
D D
0.1UF 0.1UF 0.1UF

2
IDE_BRST#

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
44 43

P_NC2
U66 IDE_BDD7 44 43 IDE_BDD8
42 42 41 41
+1.8VS IDE_BDD6 40 39 IDE_BDD9

IDE_CS0_b
IDE_CS1_b
VSS4
Reserved1
VDDO_3
Reserved2
VSS3
VDDI_3
Reserved3
Reserved4
Reserved5
ODCS
Reserved6
Reserved7
Reserved8
Reserved9
40 39
1

C776 IDE_BDD5 38 37 IDE_BDD10


IDE_BDD4 38 37 IDE_BDD11 Z61AE Default
36 36 35 35
0.1UF +3VS IDE_BDD3 34 33 IDE_BDD12 CSEL(ASUS) CSEL(Standard)
2

IDE_BDA2 SATA_BRIDGE_TXP0 IDE_BDD2 34 33 IDE_BDD13 H:Master L:Master


49 IDE_DA2 TXP 32 2 1 SATA_ICH_RXP0 <17> 32 32 31 31
IDE_BDA0 50 31 SATA_BRIDGE_TXN0C777 3900PF/50V2 1 IDE_BDD1 30 29 IDE_BDD14 L:Slave H:Slave
IDE_DA0 TXN SATA_ICH_RXN0 <17> 30 29

2
IDE_BDA1 51 30 C778 IDE_BDD0 28 27 IDE_BDD15
IDE_DA1 GNDA2 3900PF/50V 28 27
52 VDDO_1 VDDA2 29 26 26 25 25
IDE_BINTRQ 53 28 R744 IDE_BDMARQ 24 23
IDE_INTRQ RXN SATA_BRIDGE_RXN0 <17> 24 23
IDE_BDMACK# 54 27 4.7KOhm IDE_BDIOW# 22 21 PCSEL : Pull-Down, HDD as Master
IDE_DMACK_b RXP SATA_BRIDGE_RXP0 <17> 22 21
IDE_BIORDY 55 26 R811 1 2 1KOhm IDE_BDIOR# 20 19

1
IDE_IORDY REXT 1% IDE_BIORDY 20 19 IDE_BCSEL
56 VDDI_1 GNDA1 25 18 18 17 17
57 24 IDE_BDMACK# 16 15
IDE_BDIOR# VSS1 VDDA1 XO_STP IDE_BINTRQ 16 15 T348
58 IDE_DIOR_b XTALO 23 14 14 13 13

1
IDE_BDIOW# 59 22 XI_STP IDE_BDA1 12 11 IDE_BDIAG 1 R389
IDE_BDMARQ IDE_DIOW_b XTALI/CLKI STP_DISABLE# IDE_BDA0 12 11 IDE_BDA2
60 IDE_DMARQ_b DD_DISABLE_b 21 10 10 9 9
IDE_BDD15 61 20 IOINSEL1 IDE_BDCS0# 8 7 IDE_BDCS1#
IDE_BDD0 IDE_DD15 IOINSEL1 IOINPIN IDE_BDASP# 8 7
62 19 6 5

P_NC1
IDE_BDD14 IDE_DD00 IOINPIN IOINSEL0 6 5 470Ohm
63 18 4 3

2
IDE_BDD1 IDE_DD14 IOINSEL0 IDERST#_5 4 3
64 IDE_DD01 SYS_RESET_b 17 2 2 1 1
65 GND

IDE_RESET_b

45
R839 CON14
IDE_DD13
IDE_DD02
IDE_DD12

IDE_DD03
IDE_DD11
IDE_DD04

IDE_DD10
IDE_DD05
IDE_DD09
IDE_DD06
IDE_DD08
IDE_DD07 HDD_CON_2X22P
2 1
VDDO_2

VDDI_2
VSS2

10MOhm

X6
SII3811CNU 25MHZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

+3VS +1.8VS XO_STP 1 4


X1 GND2
2 3 XI_STP
GND1 x2

1
IDE_BDD13

IDE_BDD12

IDE_BDD11

IDE_BDD10

07-010732500
IDE_BDD2

IDE_BDD3

IDE_BDD4

IDE_BDD5
IDE_BDD9
IDE_BDD6
IDE_BDD8
IDE_BDD7

C779 C780
27P 27P +5VDOCK

2
11-033027000 11-033027000
C +5VDOCK +5VDOCK C

1
GND C312 C365
R2.0-S04

2
C371 C317
IDE_BRST# 1 2 10UF/10V 0.1UF 10UF/10V 0.1UF R285

2
R812 22Ohm X6 Main Source is 07-010732500 (Fujicom) 1KOhm
Second source is 07-010212500 (TXC) +3VS /*
ODD CONNECTOR

1
Symbol is changed to 07-010732500. R284

2
R383 XIDE_EN_12VS
1 2 IDE_PCSEL CON Part Number as M3N
2 /* IDERST#_5 4.7KOhm
470Ohm
P/N:12-182006000

21

16
25
23
29
31
<18,29,31,32> PCI_RST#
1 CON9
R813 0Ohm

1
1

G
27

21

16
25
23
29
31
IDE_PIORDY IDE_PIORDY_X 27
1 2 7

S 2
<6,8,17,18,24,27,36> BUF_PLT_RST# <17> IDE_PIORDY 7
R814 0Ohm

D
Q161
2N7002

1
/* Q162
POWER

G
+5VS 2N7002 IDERST#_5S 55 18

S 2
<17,20> INT_IRQ14 55 18
/* IDE_PDASP#

D
19 19
IDE_IRQ14 9
+12VS 3 IDE_PDIOR# 9
+3VS 1 2 D <17> IDE_PDIOR# 4 4
R815 10KOhm IDE_PDIOW# 5
<17> IDE_PDIOW# 5
Q164 IDE_PDDREQ 2
<17> IDE_PDDREQ 2
2

1 6 BAY_RST 1 2N7002 IDE_PDDACK# 6 35


<27> BAY_RST +5VS <17> IDE_PDDACK# 6 35
R816 2 D 5 G 1 IDE_PDIAG 8
S 4 2 S 8
3
100KOhm G C781 0.1UF
+3VS Q165 1 2 T349
1

SI3456DV
XIDE_EN_12VS U67 37
37
2

1 A 5 IDE_PIORDY 1 2 IDE_PIORDY_X
VCC IDE_PDD[15:0]
R817 R859 0Ohm
<17> IDE_PDD[15:0]
Q166 Q167 +5VDOCK 2 1 BAY_RST# 2 B
10KOhm 3 2N7002 3 2N7002 R818 10KOhm
D D
1

3 GND 4 INT_IRQ14 1 2 IDE_IRQ14


1

C782 R819 C783 C784 C785 Y R860 0Ohm 39


1 1 NC7SZ08P5X IDE_PDD0 39
3 3

2
G G 0.1UF 100KOhm 0.1UF 0.1UF 100PF IDE_PDD1 1 41
2

B R821 100KOhm 2 S 2 S IDE_PDD2 1 41 B


R2.0-S05 43 40
2

3 R820 IDE_PDD3 43 40
2 1 45 36

CDROM
D 45 36
22Ohm IDE_PDD4 47 32
Q168 IDE_PDD5 47 32
49 28

1
1 2N7002 IDE_PDD6 49 28
<17> XIDE_EN#_3 1 2 51 14

FDD
G IDERST#_5S IDE_PDD7 51 14
53 53 24 24
D69 2 S IDE_PDD8 56 26
56 26
1

RB751V_40 C786 R822 100KOhm IDE_PDD9 54 22


3 IDE_PDD10 54 22
2 1 D 52 52
0.47U IDE_PDD11 50
2

Q169 IDE_PDD12 50
48 48
1 2 1 2N7002 IDE_PDD13 46
G IDE_PDD14 46
44 44
2 S
1

D70 C787 IDE_PDD15 42


RB751V_40 42
BAYDOCK_IN# 0.47U 34 BAYDOCK_IN#
BAYDOCK_IN# <27>
2

IDE_PDA0 34
<17> IDE_PDA0 15 15
IDE_PDA1 13
<17> IDE_PDA1 13
IDE_PDA2
+3VS <17> IDE_PDA2 10 10 1
IDE_PDCS1# 17
<17> IDE_PDCS1# 17
IDE_PDCS3# 12
<17> IDE_PDCS3# 12

FPC
2
4
6
8
CD-L_A 59
<37> CD-L_A 59
1 10KOhm
3 10KOhm
5 10KOhm
7 10KOhm
20 BAY_IN0
20 BAY_IN0 <24>

CD_GND_A 57
60
<37> CD_GND_A 57
RN26A
RN26B
RN26C
RN26D

58 58
IDE_BDMARQ R823 1 2 5.6KOhm +3VS
+3VS CD-R_A
<37> CD-R_A
IDE_BDD7 R824 1 2 10KOhm 2 1

R826 1 2 8.2KOhm
/*
IDE_BINTRQ R827 1 2 10KOhm
R825 100KOhm

CD-L_A
GND
1 2 2 1 60 60
R828 1KOhm BAY_IN0 R652 10KOhm 30 BAY_IN1

11
33
38
61
62
3 30 BAY_IN1 <24>
A D A
BAY_IN1 CD-R_A 1 2 CD_GND_A

11
33
38
61
62
+3VS +3VS Q170 D71 1 2 RB751V_40 IDE_PDASP# R653 10KOhm ZIF_CON_60P
Q171 1 BAYDOCK_IN#
+3VS +3VS 2N7002 G 1 2
S 2
1

2N7002 R829 0Ohm


1

R830 R831 /* C307 C320 C329


G
3

S 2

<40> HDD_LED_5S#
1

10KOhm 10KOhm IDE_BDASP# 0.1UF 0.1UF 0.1UF


D

1 2
2

/* R832 R833 D72 RB751V_40


2

IOINPIN STP_DISABLE#
10KOhm 10KOhm
1

/* /*
2

R834 R835
SATALED# Title : HDD & ODD CONN & HOT SWAP
<17> SATALED#
10KOhm 10KOhm
/* /* IOINSEL0 IOINSEL1 ASUSTECH CO.,LTD. Engineer: Sam Wang
OPEN DRAIN.
2

Size Project Name Rev


A2 Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 22 of 57
5 4 3 2 1
5 4 3 2 1

RESERVE 0402 PAD for USB ESD diode.


USBP4-_3 USBP1+_3
USBP4+_3 USBP1-_3
USBP3-_3 USBP0+_3
USBP3+_3 USBP0-_3

1
C801 C802 C803 C804 C805 C806 C807 C808
CON Part Number Modify as ME
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF

2
/* /* /* /* /* /* /* /*
D D

10
CON12
GND4
8 GND2
USBP4+_3 7
L63 USBP4-_3 0P+
6
90OHM/370mA
09G092090200
+5VUSB2 5
0P-
VCC2 USB
USBP4-_3 4
<18> USB_PN4 GND1

1
USBP4+_3 USBP3+_3 3
<18> USB_PP4 1P+
USBP3-_3 2
+5VUSB3 1P-
1 VCC1

4
GND3
USB_CON_2X4P
9
USBP3-_3
<18> USB_PN3

1
USBP3+_3
<18> USB_PP3

4
L64
90OHM/370mA
09G092090200

CON Part Number Modify as ME

C C

10
L15 CON13
90OHM/370mA
GND4
09G092090200 8
USBP0+_3 GND2
7 0P+
2

1
USBP0-_3 6
<18>
<18>
USB_PP1
USB_PN1
USBP1+_3
+5VUSB0 5
0P-
VCC2 USB
USBP1-_3 4
2 3

1 4 USBP0+_3 USBP1+_3 GND1


3 1P+
USBP0-_3 USBP1-_3 2
<18> USB_PP0 1P-
+5VUSB1 1
<18> USB_PN0 VCC1
GND3
3

USB_CON_2X4P
9
L16
90OHM/370mA
09G092090200

B B

R2.0-S25 +3VSUS
+3VSUS

2
2

R353 L66
R354 L19 1 2 +5VUSB2
100KOhm
R2.0-S25 1 2 +5VUSB0
SUSC_PWR <52>
100KOhm

1
+5V SUSC_PWR 80Ohm/100Mhz C355

1
1

80Ohm/100Mhz C17 +5V


1

U6

2
U7 SUSC_PWR 0.1UF/25V
4 5 2 1 USB_OC#23 <18>
2

0.1UF/25V EN#/EN FLG R878 0Ohm


4 EN#/EN FLG 5 2 1 USB_OC#01 <18> 3 IN_2 OUT_3 6
3 6 R879 0Ohm 2 7 L65
IN_2 OUT_3 L20 IN_1 OUT_2 +5VUSB_23 +5VUSB3
2 IN_1 OUT_2 7 1 GND OUT_1 8 1 2
1 8 +5VUSB_01 1 2 +5VUSB1
GND OUT_1
1

1
80Ohm/100Mhz C356
1

1
80Ohm/100Mhz C19 C39 G528P1U C809
1

C26 G528P1U C810 0.1UF/25V 0.1uF/10V


2

2
1
0.1UF/25V 0.1uF/10V /* + 0.1UF/25V
2

2
1

/* + 0.1UF/25V CE2
2

CE4 47UF/6.3V
47UF/6.3V

2
Vdroop fail if use 150U
2

Vdroop fail if use 150U

A A

Title : USB PORTS


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 23 of 57
5 4 3 2 1
5 4 3 2 1

D D

Super I/O

+3VS

<26> LPT_ACK# LPT_BUSY <26>


<26> LPT_ERR# LPT_PE <26>
<26> LPT_AFD# LPT_SLCT <26>
C C
<26> LPT_STB# LPT_PD7 <26>
LPT_PD6 <26>
LPT_PD5 <26>
DSR1#
LPT_PD4 <26>

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
U1

nSTROBE

nACK
BUSY
PE
nALF

SLCT
nDSR1
TXD1
RXD1

VCC4
PD7
VSS4
PD6
PD5
PD4
nERROR
1 nRTS1 PD3 48 LPT_PD3 <26>
CTS1# 2 47
nCTS1 PD2 LPT_PD2 <26>
3 nDTR1 PD1 46 LPT_PD1 <26>
RI1# 4 45
nRI1 VCC3 +3VS
DCD1# 5 44
nDCD1 PD0 LPT_PD0 <26>
IO_PME# 6 43
IO_PME# VSS3
+3VS 7 VTR nSLCTIN 42 LPT_SLIN# <26>
8 VSS1 nINIT 41 LPT_INIT# <26>
<21> CLK_SIO14 9 CLOCKI GP23 40
<17,27,33,36> LPC_AD0 10 LAD0 IRMODE/IRRX3 39
+3VS 11 VCC1 IRTX2 38
<17,27,33,36> LPC_AD1 12 LAD1 IRRX2 37
13 36 GPI14
<17,27,33,36> LPC_AD2 LAD2 GP14/IRQIN2
14 35 GPI13
<17,27,33,36> LPC_AD3 LAD3 GP13/IRQIN1

PCI_RESET#
15 34 IO_SMI#
<17,27,33,36> LPC_FRAME# LFRAME# GP12/IO_SMI# SYSOPT

CLKRUN#
16 33

SER_IRQ
<17,20> LPC_DRQ#0

PCI_CLK
LDRQ# GP11/SYSOPT

LPCPD#

VCC2
GP40
GP41
GP42

GP43
GP44
GP45
GP46
GP47
GP10
VSS2
LPC47N217

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
802_ON# <40>
<6,8,17,18,22,27,36> BUF_PLT_RST# BAY_IN1 <22>
1 2 LPCPD#
<17,20> PM_SUS_STAT# BAY_IN0 <22>
R3 0Ohm /*
B <17,20,27,31,32> PM_CLKRUN# B
CLK_SIOPCI
<21> CLK_SIOPCI
<17,20,27,32> INT_SERIRQ PID_1 <15>
PID_0 <15>

+3VS

+3VS

2 1 GPI14
R11 2 1 10KOhm /* GPI13
R12 2 1 10KOhm /* IO_SMI# SYSOPT=0 --> 0x002E
R13 2 1 10KOhm /* IO_PME#
R1 2 1 10KOhm /* LPCPD# SYSOPT=1 --> 0x004F
R2 10KOhm

2 1 SYSOPT +3VS
R14 10KOhm +3VS
CLK_SIOPCI
1

1
C12 C352 C21 C1
+3VS C9 C24
0.1UF 10UF/10V 0.1UF 0.1UF 0.1UF
2

2
RN1A /* CTS1# 5PF
1 10KOhm 2 /*
3 10KOhm 4 RN1B /* RI1#
5 10KOhm 6 RN1C /* DSR1#
7 10KOhm 8 RN1D /* DCD1#

A A

Title : SUPER I/O LPC47N217


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 24 of 57
5 4 3 2 1
5 4 3 2 1

FIXED HOLE CPU Need to change part number in BOM


R1.1-S13
H1
1 1
H9
1
H16 to 13-N7510M270.
C111D91 C67D67N c158d138 MDC_NUT R1.1 has changed it in symbol.
H2
H12
1 1 H4
D C111D91 c158d138 1 D
H3 CT197CB87D47
H17 13-N7510M270
H24
1
1
1
c158d138 H6 MDC _NUT
C111D91
H5 C91D91N
H11
1
CT197CB87D47
Type:SMD TOP SIDE
1 1
c158d138
13-N7510M270 Part Number
C111D91
H8 :13-N7510M270
1
C111D91
H13
1
C111D91
H10
1
C111D91
H20
North bridge heatsink nut
1
C111D91
H19
H14
1 1
C217D130
North bridge heatsink nut
C111D91
H18
H15 Type:SMD TOP SIDE
1 1
C217D130
Part Number :13-N9980M100
C111D91

H23
1
C111D91
C C
H21
1
C111D91
H22
1
C111D91

R1.1-S16
EMI request. Need to change part number in BOM
H7 Place Below X1
to 13-N7510M270.
1
H25
R1.1 has changed it in symbol.
C111D91 /*
1
CT197CB87D47
13-N7510M270

AGND_A

B B

For EMI DDR Finger spring.


Need to add part number.
R2.0-S20
1 1
EMI1
EMI_SPRING_PAD
EMI request.
13-NDV50S010

1 EMI2
1 EMI_SPRING_PAD
13-NDV50S010 EMI SPRING
1 EMI3 Type:SMD BOTTOM SIDE
1 EMI_SPRING_PAD
13-NDV50S010 Part Number :13-NDV50S010
/*
1 EMI4
1 EMI_SPRING_PAD
13-NDV50S010
/*
1 EMI5
1 EMI_SPRING_PAD
13-NDV50S010 FOR TOP EMI SPRING.
N/A

A A

Title : Z61Ae
ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 25 of 57
5 4 3 2 1
5 4 3 2 1

D
R1.1-S37 D
+3VSUS +5VSUS

1
R23 R847
10KOhm 10KOhm
/*

2
PR_IN# 1 2
<16> PR_IN#
D4 For EMI (NEAR CONNECTOR)
RB751V_40
R1.1-S04 A/D_DOCK_PR +5VS +5V
A/D_DOCK_PR

A/D_DOCK_IN DOCK_VIN_P

1
C16 C14 C23
L18 4 A(Typ)
0.1UF 0.1UF

2
4532 Q1 0.1UF/25V
680 Ohm/ 100MHz SI3457DV
6 1
5 D 2
4 S 3
G

R20 R19
1 2 1 2 PR_IN#_Q

100KOhm 20KOhm

C C

A/D_DOCK_PR
R1.1-S23
+5VS

1
CN3
D68
34 33 SS0540
34 33
32 32 31 31
30 29

2
30 29
28 28 27 27
26 26 25 25 USB_PP2 <18>
<18> USB_PN2 24 24 23 23
22 22 21 21
20 19 L_TDP 2 1 L_TDP_MB
20 19 <29> L_TDP L_TDP_MB <30>
L_TDP_PR 18 17 L_TDN_PR LPT_SLCT 1 2 L_TDN R18 2 1 0Ohm /* L_TDN_MB
18 17 <29> L_TDN L_TDN_MB <30>
L_RDP_PR 16 15 L_RDN_PR L_RDP R10 2 1 0Ohm /* L_RDP_MB
16 15 <29> L_RDP L_RDP_MB <30>
14 13 R808 L_RDN R9 2 1 0Ohm /* L_RDN_MB
14 13 LPT_STB# <24> <29> L_RDN L_RDN_MB <30>
12 11 2.7KOhm R17 0Ohm /*
<24> LPT_PD0 12 11 LPT_PD1 <24>
<24> LPT_PD2 10 10 9 9 LPT_PD3 <24>
<24> LPT_PD5 8 8 7 7 LPT_PD7 <24>
6 5 PR_IN#_Q RP8A R336
<24> LPT_BUSY 6 5
L11 4 3 LPT_SLIN# 1
<16> VSYNC_PB 4 3 DDC2BD_5 <16> 2.7KOhm5 +5VSUS 2 1
1 2 DAC_G_PB_Q 2 1 10 RP8B
<16> DAC_G_PB 2 1
68 67 LPT_INIT# 2 0Ohm
68 67 2.7KOhm5

1
75Ohm/100Mhz 66 65 10 RP8C C33
66 65 LPT_ERR# R338
64 64 63 63 3 2.7KOhm5
62 61 10 RP8D 2 1 0.1UF
+3VSUS

2
62 61 LPT_AFD#
60 60 59 59 4 2.7KOhm5
58 57 10 RP8E 0Ohm /*
+5VS 58 57 +5VS
56 55 LPT_PE 6
56 55 2.7KOhm5
54 53 10 RP8F U5
54 53 LPT_ACK# PR_IN#
B <24> LPT_PE 52 52 51 51 LPT_ACK# <24> 7 2.7KOhm5 OE S Out 1 S VCC 16 B
50 49 10 RP8G ============ L_TDP_PR 2 15
<24> LPT_PD6 50 49 LPT_PD4 <24> IA0 E#
48 47 LPT_PD6 8 L_TDP_MB L_RDN_PR
<24> LPT_SLIN# 48 47 LPT_INIT# <24> 2.7KOhm5 L L B1 3 IA1 ID0 14
46 45 10 RP8H L_TDP 4 13 L_RDN_MB
<24> LPT_ERR# 46 45 LPT_AFD# <24> YA ID1
+12VS 2 1 44 43 LPT_SLCT <24>
LPT_PD4 9 2.7KOhm5
L H B2 L_TDN_PR 5 12 L_RDN
R7 0Ohm 44 43 L_TDN_MB IB0 YD L_RDP_PR
+5V_PR 42 42 41 41 +5V_PR 10 H X NC 6 IB1 IC0 11
40 39 L9 L_TDN 7 10 L_RDP_MB
40 39 DDC2BC_5 <16> YB IC1
L10 38 37 DAC_B_PB_Q 1 2 8 9 L_RDP
<16> HSYNC_PB 38 37 DAC_B_PB <16> GND YC
1 2 DAC_R_PB_Q 36 35 RP9A
<16> DAC_R_PB 36 35
75Ohm/100Mhz LPT_BUSY 1 PI5C3257
2.7KOhm5
69
70
71
72

75Ohm/100Mhz 10 RP9B
1

C13 LPT_PD5 2 2.7KOhm5


69
70
71
72

DOCKING_68P 10 RP9C
LPT_PD2 3 2.7KOhm5
2

0.1UF/25V 10 RP9D
LPT_PD0 4 2.7KOhm5
10 RP9E
LPT_PD7 6 2.7KOhm5
10 RP9F
LPT_PD3 7 2.7KOhm5
10 RP9G
PORT BAR III LPT_PD1 8 2.7KOhm5
RP9H
10
LPT_STB# 9 2.7KOhm5
10
DAC_G_PB

DAC_R_PB

DAC_B_PB

1
+5V R327 R328 R329
150Ohm 150Ohm 150Ohm
For Port Bar OC

2
+5V_PR
U4
A 1 OUT IN 5 A
R8 2 GND
1

1 2 3 SET ON# 4
C10
1

0.47U 10KOhm AAT4610


2

C28
4.7U
2

Title : PORT BAR 3


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 26 of 57
5 4 3 2 1
5 4 3 2 1

+3VS

4 RN51A
6 RN51B
8 RN51C
RN51D
+5VS

2
10KOhm
10KOhm
10KOhm
10KOhm
D
P2.1 Low : Power Button Override disable D

Input Event only at P54, P55, P60 - P67

1
3
5
7
Q97

1
G
P50, P43, P54, P55 are wake-up event KBC_GA20

S 2
HA20GATE <17>

D
inputs when KBC in standby mode
2N7002 Q100

1
+3V

G
KBCPURST_3Q

S 2
KBDCPURST <17>

D
2N7002 Q92

10

10

10

10

10

10

10

10

1
5

G
2 KBSCI_3Q

S 2
KBDSCI_3 <17>

10KOhm

10KOhm

10KOhm

10KOhm

10KOhm

10KOhm

10KOhm

10KOhm
R266

D
2
R267
470KOhm C280 47KOhm +3V 2N7002 Q104

1
1

9
/*

G
EC should set
1

1
5PF

RP4G
RP4A

RP4B

RP4E
RP4C

RP4D

RP4H
RP4F
2 1 ACIN_OC

S 2
OP_SD low in S3, /* ACIN_OC_3 <17>

D
keep from leakage.

4 RN54A
6 RN54B
C283 0.1UF

8 RN54C
RN54D
LID_ICH#_3 1 2 2N7002
+3V
INTERNET#
BAT2_IN#_OC 1 2

2
DISTP# U31
MARATHON# 63 C284
<17,20,24,32> INT_SERIRQ

10KOhm
10KOhm
10KOhm
10KOhm
ACIN_OC P87/SERIRQ 0.1UF
<21> CLK_KBCPCI 64 P86/LCLK
<6,8,17,18,22,24,36> BUF_PLT_RST# 65 P85/LRESET# VCC 71
<17,24,33,36> LPC_FRAME# 66 P84/LFRAME#
<17,24,33,36> LPC_AD3 67

1
3
5
7
P83/LAD3
<17,24,33,36> LPC_AD2 68 P82/LAD2 VREF 72 Follow M3N
<17,24,33,36> LPC_AD1 69 P81/LAD1
<17,24,33,36> LPC_AD0 70 P80/LAD0
31 SCROLLOCK#
P27 SCROLLOCK# <40>
NUM_LED#
P23 35
P54,P55,P43,P50 are P26 32
33 CAP_LED#
NUM_LED# <40>
CAP_LED# <40>
C
<50> BAT_LEARN
BAT_LEARN 36
P23
P22 wake-up event P25
P24 34 SET_PCIRSTNS#
SET_PCIRSTNS# <18> +3VSUS
C
BAT_SEL
KBCRSM
37
38
P21 inputs when KBC in
<43> KBCRSM P20
standby mode P17/KSO15 39 KSO15

1
40 KSO14
WATCHDOG P16/KOS14 KSO13 R536
<35> WATCHDOG 23 P42/INT0 P15/KSO13 41
<48> CHG_FULL_OC 22 42 KSO12
C718 2 KBCPURST_3Q P43/INT1* P14/KSO12 KSO11
1 0.1UF 21 P44/RXD P13/KSO11 43 10KOhm
KBC_GA20 20 44 KSO10

2
KBSCI_3Q P45/TXD P12/KSO10 KSO9
19 P46/SCLK1 P11/KSO9 45
PM_CLKRUN# KSO8 C285
<17,20,24,31,32> PM_CLKRUN# 18 P47/SRDY1#/CLKRUN# P10/KSO8 46 EXTSMI#_3A <17>
47 KSO7 X1_KBC 1 2
BAT_LOW#_KBC P07/KSO7 KSO6 3
<40> BAT_LOW#_KBC 17 P50/INT5* P06/KSO6 48 D

2
T358 1 KBC_P51 16 P51/INT20 P05/KSO5 49 KSO5 X2
R1.1-S22 BAY_RST 15 50 KSO4 R262 3 5PF Q101
<22> BAY_RST P52/INT30/1-WIRE1 P04/KSO4 KBC_EXTSMI 1
BT_ON 14 51 KSO3
<31> BT_ON BAYDOCK_IN# P53/INT40/1-WIRE2 P03/KSO3 KSO2 1MOhm 2N7002
R1.1-S22 <22> BAYDOCK_IN# 13 52 G
BAT1_IN#_OC 12
P54/CNTR0* P02/KSO2
53 KSO1 /* 8MHZ C279 2 S
<53> BAT1_IN#_OC

1
P55/CNTR1* P01/KSO1

1
T359 1 KBC_P56 11 P56/DA1/PWM01 P00/KSO0 54 KSO0 X2_KBC 1 2
ADJ_BL 10 R535
<15> ADJ_BL P57/DA2/PWM11 KSI7
P37/KSI8 55
BAT2_IN#_OC 74 56 KSI6 5PF
<53> BAT2_IN#_OC P67/AN7 P36/KSI7
DISTP# 75 57 KSI5 10KOhm
<40> DISTP#

2
MARATHON_# P66/AN6 P35/KSI6 KSI4
<40> MARATHON# 76 P65/AN5 P34/KSI5 58
ACIN_OC 77 59 KSI3
<53> ACIN_OC P64/AN4 P33/KSI4
LID_ICH#_3 78 60 KSI2
<43> LID_ICH#_3 P63/AN3 P32/KSI3
79 61 KSI1
<31,40> 802_ON P62/AN2 P31/PWM10/KSI2
INTERNET_# 80 62 KSI0
<40> INTERNET# P61/AN1 P30/PWM00/KSI0
EMAIL_# 1
<40> EMAIL# P60/AN0
28 X1_KBC
XIN X2_KBC
XOUT 29
KBDCLK_5S 4
MOUSECLK_5S P75/INT41 KBC_EXTSMI
5 P74/INT31 P40/XCOUT 27
INTCLK_5S 6 26 EMAIL_LED#
<41> INTCLK_5S P73/INT21 P41/XCIN EMAIL_LED# <40>
KBDDATA_5S 7
MOUSEDATA_5S P72
8 P71
INTDATA_5S 9 25 PCI_RSTNS#
<41> INTDATA_5S P70 RESET# PCI_RSTNS# <18>
B
SMC_BAT
For Audio DJ, Must be Removed B
2 P77/SCL CNVSS 24
SMD_BAT 3 30 +3V
P76/SDA VSS +3V
AVSS 73

KSI0 1
M38857 10KOhm5
80mA 2 RN53A 110KOhm BAT_LOW#_KBC RP3A 10
4 RN53B 3 10KOhm KBSCI_3Q KSI1 2 10KOhm5
6 RN53C 510KOhm BAT1_IN#_OC RP3B 10
8 RN53D 7 10KOhm R1.1-S19 KSI2 3 10KOhm5

KEYBOARD CONN
RP3C 10
6 RN23C 54.7KOhm EMAIL_# KSI3 4 10KOhm5
2 RN25A 1 4.7KOhm SMC_BAT RP3D 10
6 RN25C 54.7KOhm SMDATA_BAT1 KSI4 6 10KOhm5
8 RN25D 7 4.7KOhm SMD_BAT RP3E 10
CON Part Number Modify as M3N KSI5 7 10KOhm5
2 RN24A 110KOhm KBCPURST_3Q RP3F 10
4 RN24B 3 10KOhm KBC_GA20 KSI6 8 10KOhm5
CON6 +5VS 6 RN24C 510KOhm INTDATA_5S RP3G 10
8 RN24D 7 10KOhm INTCLK_5S KSI7 9 10KOhm5
KSI0 5 RP3H 10
KSI1 KSI0
6 KSI1
KSI2 8
KSI3 KSI2 BAT_SEL
9 KSI3
KSI4 10
KSI5 KSI4 P2.1 Need Pull Low +5VS
11 KSI5

2
KSI6 14 R270
KSI7 KSI6
BAT_SEL=0 --> BAT2 15 KSI7
25
+5V NC0
BAT_SEL=1 --> BAT1 KBDDT0

4 RN22A
6 RN22B
10KOhm

8 RN22C
RN22D
NC1 26 KBDDT0 <18,20>
KSO0 1 27

1
U32 KSO1 KSO0 NC2 KBDDT1
2 KSO1 NC3 28 KBDDT1 <18,20>
BAT_SEL 1 16 KSO2 3
S VCC KSO2

2
SMCLK_BAT2 2 15 KSO3 4
SMCLK_BAT1 IA0 E# KSO4 KSO3 +3V
3 14 7

1 10KOhm
3 10KOhm
5 10KOhm
7 10KOhm
SMC_BAT IA1 ID0 KSO5 KSO4
4 YA ID1 13 12 KSO5
1

SMDATA_BAT2 5 IB0 YD 12 C294 KSO6 13 KSO6 2 RN23A 14.7KOhm SMCLK_BAT1


SMDATA_BAT1 6 IB1 IC0 11 KSO7 16 KSO7 4 RN23B 3 4.7KOhm
A SMD_BAT 7 10 0.1UF KSO8 17 8 RN23D 74.7KOhm SMCLK_BAT2 A
2

YB IC1 KSO9 KSO8 SMDATA_BAT2


8 GND YC 9 18 KSO9 4 RN25B 3 4.7KOhm
KSO10 19
PI5C3257 KSO11 KSO10 MOUSEDATA_5S
20 KSO11
KSO12 21 SMCLK_BAT1 MOUSECLK_5S
KSO12 <49> SMCLK_BAT1
KSO13 22 SMDATA_BAT1 KBDDATA_5S
KSO13 <49> SMDATA_BAT1
KSO14 23 SMCLK_BAT2 KBDCLK_5S
KSO14 <49> SMCLK_BAT2
KSO15 24 SMDATA_BAT2
KSO15 <49> SMDATA_BAT2

FPC_CON_28P
KBDDT1 KBDDT0 Matrix Title : KBC 38857
1 1 US
1 0 UK ASUSTECH CO.,LTD. Engineer: Sam Wang
0 0 JP Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 27 of 57
5 4 3 2 1
5 4 3 2 1

D D

Connect SMLINK and SMBUS


<17,20> SM_LINK0 for SMBus 2.0 compliance.
ICH6-M
<17,20> SM_LINK1
+3VS +3VS

3
+5VS Q77A Q77B

2
2 5
UM6K1N UM6K1N +5VS R442 R441

4
/* /*
4.7KOhm 4.7KOhm

1
Q81

1
G
3

S 2
<17,20> SCL_3A SCL_3S <12,13,21,35>

D
Termal Sensor,
2N7002
ICH6-M Clock Generator
Q80 DDR2 SO-DIMM

1
G
TPM

S 2
<17,20> SDA_3A SDA_3S <12,13,21,35>

D
C C

2N7002

+3VALWAYS +3VALWAYS <17,21,33,40,43,45,46,52>

+3VSUS +3VSUS <15,17,19,20,21,23,26,27,29,43,52>

+5VALWAYS +5VALWAYS <46,48>

+5VSUS +5VSUS <19,26,52>

+3V +3V <15,18,27,29,31,32,33,34,38,39,40,42,43,47,52>

+5V +5V <4,8,16,23,26,27,33,37,40,41,42,43,52,53>

+12V +12V <34,38,42,52>

+3VS +3VS <4,10,12,13,15,16,17,19,20,21,22,24,27,31,32,35,36,37,42,43,44,47,48,52>

+5VS +5VS <16,19,22,26,27,29,31,35,38,40,42,52>

+12VS +12VS <15,16,22,26,35,42,46,52>

+VCORE +VCORE <5,6,35,44>

+VCCP +VCCP <4,5,6,7,10,17,19,21,47>

B B

+2.5VS +2.5VS <6,8,10,11,15,16,19,42,46>

+1.8VS +1.8VS <22,42,52>

+0.9VS +0.9VS <14,47>

+1.5VS +1.5VS <10,18,19,42,46>

+VCC_RTC +VCC_RTC <17,19>

+1.8V +1.8V <8,10,11,12,13,32,42,46,47>

+VCC_GMCH_CORE +VCC_GMCH_CORE <10,11,47,48>

+VCCCB +VCCCB <32,33>

+VPPCB +VPPCB <33>

VTT_REF VTT_REF <8,12,13>

A/D_DOCK_IN A/D_DOCK_IN <26,50,53>

A A

Title : SM BUS & POWER PORT


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 28 of 57
5 4 3 2 1
5 4 3 2 1

GND

R1.1-S14
PCI_AD[31:0] <18,31,32>

2
C765 C766
10UF/10V 10UF/10V C120
0.1uF/10V

1
L29
1 2 +2.5VSUS_LAN

R1.1-S33 R403
D
4.99KOhm 120Ohm/100Mhz D

GND 1 2

AVDDL
GND
L_TDP PME_SB#
<26> L_TDP PME_SB# <18,20>
L_TDN
<26> L_TDN

XTAL1
XTAL2
L_RDP

EEDO
EECS
EESK
<26> L_RDP

EEDI/AUX
L_RDN
<26> L_RDN
2 /* 1 ISOLATEB
<4,17,21,32,37,40,43,48,52> PM_SUSB#
R861 0Ohm
R862
+5VS 2 1KOhm 1

2 R863

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND 1
15KOhm U13
1%

ISOLATEB

TXD+

RXIN+

LWAKE

PMEB

EECS
EESK
EEDI

ROMCS/OEB
RTSET
GND_7

RTT3
GND_5
X1
X2
AVDD_1

EEDO
AVDD

TXD-
AVDD_2
NC

RXIN-
GND_6

AVDD25_1

VCTRL
76 LED2 CLKRUNB 50
77 LED1 VDD_4 49
78 LED0 VDD25_1 48 +2.5VSUS_LAN
79 47 PCI_AD0
INTBB AD0 PCI_AD1
<18,20,32> PCI_INTC# 80 INTAB AD1 46
81 45 PCI_AD2
<18,22,31,32> PCI_RST# RTSB AD2
<18> PCI_GNT#0 82 GNTB GND_4 44
83 43 PCI_AD3
<18,20> PCI_REQ#0 REQB AD3
84 42 PCI_AD4
<18,31,32> PCI_C/BE#3 CBE3B AD4
PCI_AD31 85 41 PCI_AD5
GND PCI_AD30 AD31 AD5 PCI_AD6
86 AD30 AD6 40
PCI_AD29 87 39 PCI_AD7
AD29 AD7
88 GND_8 CBE0B 38 PCI_C/BE#0 <18,31,32>
PCI_AD28 89 37
AD28 VDD_3 PCI_AD8
90 VDD_5 AD8 36
PCI_AD27 91 35 PCI_AD9
PCI_AD26 AD27 AD9 PCI_AD10
92 AD26 AD10 34
PCI_AD25 93 33 PCI_AD11
+2.5VSUS_LAN AD25 AD11 PCI_AD12
94 VDD25_2 AD12 32
C 95 VDD_6 GND_3 31 C
PCI_AD24 96 30 PCI_AD13
AD24 AD13 PCI_AD14
<21> CLK_LANPCI 97 PCICLK AD14 29

AC_DOUT
PCI_AD16 1 PCI_AD15

AC_SYNC
AC_RSTB

DEVSELB
2 98 28

FRAMEB
IDSEL AD15
1

AC_BCK
AC_DIN
C65 99 27

PERRB
TRDYB

STOPB
GND_1

GND_2
CBE2B
VDD_1

VDD_2
PCI_C/BE#1 <18,31,32>

IRDYB
/* R355 GPIO1 CBE1B

AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
100 26

PAR
GPIO0 SERRB PCI_SERR# <18,20,31,32>
10PF 33Ohm
2

RTL8101L

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND

PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
+3VSUS_LAN

PCI_STOP# <18,20,31,32>
PCI_PERR# <18,20,31,32>
PCI_PAR <18,31,32>
PCI_TRDY# <18,20,31,32>
PCI_IRDY# <18,20,31,32>
PCI_FRAME# <18,20,31,32>
PCI_DEVSEL# <18,20,31,32>
PCI_C/BE#2 <18,31,32>

B B

+3VSUS_LAN

1
R405
5.6K
+3V +3V

2
+3VSUS_LAN
+3VSUS +3VSUS_LAN R1.1-S14
U18
Close to R1.1-S14 EECS 1 8
pull up to
CS VCC

3
AVDDL EESK 2 7
RTL8100CL SK DC VccSus3_3

1
+3VSUS_LAN C767 EEDI/AUX C73 RN48A RN48B
L69 10UF/10V
30 mil EEDO
3 DI ORG 6
20 mil 4 DO GND 5
0.1uF/10V 10KOhm 10KOhm by internal
1 2

2
AT93C46
pull-up
1

120Ohm/100Mhz

4
1

C407 C121 C52 C44 C56 C89 C79 C78


0.1uF/10V 10UF/10V 0.1uF/10V 0.1uF/10V 0.1uF/10V 0.1uF/10V GND GND resistor
2

0.1uF/10V 0.1uF/10V
2

The Crystal should be placed

1
far away from I/O ports,

G
GND GND GND GND GND GND GND GND GND
important or high frequency PME_SB#

2 S

3
<31,32> PCI_PME#

D
signal traces (Tx, Rx,power),
magnetics or board edges.
Q87
2N7002

C124 2 1 0.1uF/10V 2 1 L_TDP


R1.1-S32 R869
10MOhm /*
R83 2 1 49.9Ohm L_TDN 2 1
R82 49.9Ohm
A C123 2 1 0.1uF/10V 2 1 L_RDP +2.5VSUS_LAN A
R80 2 1 49.9Ohm L_RDN X1
R79 49.9Ohm 25MHZ
XTAL1 1 4
X1 GND2
X1 Main Source is 07-010732500 (Fujicom)
GND 2 3 XTAL2
GND1 x2 Second source is 07-010212500 (TXC)
1

Symbol is changed to 07-010732500.


1

C86 C55 C127 07-010732500 C128


15P 15P
2

0.1uF/10V 0.1uF/10V
Title : LAN-RTL8101L
2

GND GND R2.0-S09 GND ASUSTECH CO.,LTD. Engineer: Sam Wang


Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 29 of 57
5 4 3 2 1
5 4 3 2 1

TO MDC CONN. RJ11 CONNECTOR D

P/N:12-170000021 P/N:12-142111060

CON Part Number Modify as ME CON Part Number Modify as ME

U2 L61 J3
3 1KOhm/100MHz 5 3
NC1 RJ11_TIP_CON RJ11_TIP
SPKL- 1 1 2 1
2 RJ11_RING_CON 1 2 RJ11_RING 2
SPKL+
NC2 4 6 4
1KOhm/100MHz
WtoB_2P L62 RJ11

1
C795 C796

2
1000PF/3KV 1000PF/3KV

C C

The 10/100M magnetics U3701 should be placed as


close as possible to the J3701 connector.

<26> L_RDP_MB 1 RD+


U8

RX+ 16 LAN_RDP
LAN RJ45 CONNECTOR
2 15 LAN_RDN
<26> L_RDN_MB RD- RX- RXCT
3 RDCT RXCT 14
P/N:12-140111080
6 11 TXCT
PTCT/TDCTTXCT LAN_TDP
<26> L_TDP_MB 7 TD+ TX+ 10
8 9 LAN_TDN
<26> L_TDN_MB TD- TX-
4 NC1 NC3 12
5 NC2 NC4 13

LF8423 CON Part Number Modify as ME


1

C63 C797
0.1uF/10V 0.1uF/10V
B B
2

To improve symmetry.

R842 75Ohm CON11


1 2 8 8 P_GND2 10
7 7 NP_NC2 12
R843 75Ohm LAN_RXN 6 6
1 2 5 5
4 4
FOR EMI R844 75Ohm LAN_RXP 3
RXCT LAN_TXN 3
1 2 2 2 NP_NC1 11
R845 75Ohm LAN_TXP 1 9
TXCT 1 P_GND1
1 2
1

1
C792 C358 RJ45
0.1uF/10V 0.1uF/10V
R793 1 2
2

2
0Ohm

1
R2.0-S08 C788 C789 C790 C791
LAN_TDN LAN_TXN 5PF 5PF 5PF 5PF

2
1

/* /* /* /*
180Ohm/330mA
/* L12
LAN_TDP LAN_TXP
4

R794 1 2
0Ohm

A R795 1 2 A
0Ohm

LAN_RDN LAN_RXN
1

180Ohm/330mA
/* L13
LAN_RDP LAN_RXP
4

R796 1 2
0Ohm Title : RJ45 / RJ11
ASUSTECH CO.,LTD. Engineer: Sam Wang
R1.1-S14 Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 30 of 57
5 4 3 2 1
5 4 3 2 1

MINIPCI CONNECTOR
MINIPCI Connector (P/N:12-023511240) need to add
+3VS

PCI_AD[31:0]
12-023521243 into second source.
<18,29,32> PCI_AD[31:0]

CON Part Number Modify as M3N

125
126
CON4

1 2

SIDE1
SIDE2
TIP RING
3 LAN_RESERV1 LAN_RESERV2 4
D 802_ACTLED (Internal Pull-High) 5 LAN_RESERV3 LAN_RESERV5 6 802_ACTLED (Internal Pull-High) D
7 LAN_RESERV4 LAN_RESERV7 8
R49 9 10 +3VS
802_ACTLED /* 2 0Ohm LAN_RESERV6 LAN_RESERV10 802_ACTLED
<40> 802_ACTLED 1 11 LAN_RESERV8 LAN_RESERV12 12 1 2
1 2 13 14 R71 0Ohm
<27,40> 802_ON LAN_RESERV9 LAN_RESERV13
R712 0Ohm 15 16 /*
LAN_RESERV11 LAN_RESERV14
<18,20> PCI_INTD# 17 INTB# 5V_1 18 +5VS

1
19 20 C93 C92 C69 C94 C95 C62
3.3V_7 INTA# PCI_INTB# <18,20,32>
21 22 C61
RESERVED9 RESERVED3 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
23 24 +3V 10UF/10V

2
GROUND15 3.3VAUX1
<21> CLK_MINIPCI 25 CLK RST# 26 PCI_RST# <18,22,29,32>
27 GROUND4 3.3V_3 28
<18,20> PCI_REQ#3 29 REQ# GNT# 30 PCI_GNT#3 <18>
31 3.3V_4 GROUND7 32
2 1 PCI_AD31 33 34 PCI_PME#
AD[31] PME# BT_PRIOITY PCI_PME# <29,32>
PCI_AD29 35 36
AD[29] RESERVED6 PCI_AD30
5PF C66 37 GROUND8 AD[30] 38
/* PCI_AD27 39 40
PCI_AD25 AD[27] 3.3V_5 PCI_AD28
41 AD[25] AD[28] 42
CH_SATA 43 44 PCI_AD26
RESERVED8 AD[26] PCI_AD24
<18,29,32> PCI_C/BE#3 45 C/BE[3]# AD[24] 46
PCI_AD23 47 48 2 1 PCI_AD18
AD[23] IDSEL R70 100Ohm
49 GROUND11 GROUND9 50
PCI_AD21 51 52 PCI_AD22 +3V
PCI_AD19 AD[21] AD[22] PCI_AD20
53 AD[19] AD[20] 54
55 GROUND13 PAR 56 PCI_PAR <18,29,32>
PCI_AD17 57 58 PCI_AD18
AD[17] AD[18] PCI_AD16
<18,29,32> PCI_C/BE#2 59 C/BE[2]# AD[16] 60

1
61 62 C91
<18,20,29,32> PCI_IRDY# IRDY# GROUND10 C58
63 3.3V_8 FRAME# 64 PCI_FRAME# <18,20,29,32>
65 66 10UF/10V 0.1UF
<17,20,24,27,32> PM_CLKRUN# PCI_TRDY# <18,20,29,32>

2
CLKRUN# TRDY#
<18,20,29,32> PCI_SERR# 67 SERR# STOP# 68 PCI_STOP# <18,20,29,32>
69 GROUND14 3.3V_6 70
<18,20,29,32> PCI_PERR# 71 PERR# DEVSEL# 72 PCI_DEVSEL# <18,20,29,32>
<18,29,32> PCI_C/BE#1 73 C/BE[1]# GROUND12 74
PCI_AD14 75 76 PCI_AD15
AD[14] AD[15] PCI_AD13
77 GROUND16 AD[13] 78
PCI_AD12 79 80 PCI_AD11
PCI_AD10 AD[12] AD[11]
C 81 AD[10] GROUND1 82 C
83 84 PCI_AD9
PCI_AD8 GROUND2 AD[09] +5VS
85 AD[08] C/BE[0]# 86 PCI_C/BE#0 <18,29,32>
PCI_AD7 87 88
AD[07] 3.3V_1 PCI_AD6
89 3.3V_2 AD[06] 90
PCI_AD5 91 92 PCI_AD4
AD[05] AD[04] PCI_AD2
93 RESERVED4 AD[02] 94

1
PCI_AD3 95 96 PCI_AD0 C68 C90
AD[03] AD[00] C60
+5VS 97 5V_2 RESERVED1 98
PCI_AD1 99 100 10UF/10V 0.1UF 0.1UF

2
AD[01] RESERVED2
101 GROUND6 GROUND3 102
103 AC_SYNC M66EN 104
105 AC_SDATA_IN AC_SDATA_OUT 106
107 AC_BIT_CLK AC_CODEC_ID0# 108
109 AC_CODEC_ID1# AC_RESET# 110
111 MOD_AUDIO_MON RESERVED5 112
113 AUDIO_GND2 GROUND5 114
115 S_AUDIO_OUT S_AUDIO_IN 116
117 S_AUDIO_OGND S_AUDIO_I GND 118
119 120
POST1
POST2

AUDIO_GND1 AUDIO_GND
121 RESERVED7 MCPIACT# 122
123 VCC5A 3.3VAUX2 124 +3V
127
128

MINI_PCI
12-023511240

B
Bluetooth Conn. B
R2.0-S03

CON20 +3V_BT
12 6 BT_PRIOITY
SIDE2 6 BT_HW_DIS#
1 2 11 SIDE1 5 5
R716 0Ohm 10 4 CH_SATA
BT_USB_PP5 10 4
<18> USB_PP5 9 9 3 3
2

BT_USB_PN5 8 2 BT_LED
8 2 BT_LED <40>
L92 7 1
200Ohm 7 1
/*
<18> USB_PN5
3

WTOB_10P

1 2
R715 0Ohm

BT_HW_DIS#
2

R717
0Ohm
R1.1-S38 /*
1

+3V
+3V Q149
R846

+3V_BT
1

SI2305DS
R719
A 0Ohm 2 3 L93 2 1 A
S

3 D
10KOhm

1 /* BT_ON#
2

2
2

80Ohm/100Mhz
G
2

3 C719 R718 C720 l0805


11

D
Q150 0.1UF 100KOhm 0.1UF
2

BT_ON 1 2N7002
<27> BT_ON
1

G
2 S

Title : MINIPCI & BLUETOOTH Conn.


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 31 of 57
5 4 3 2 1
5 4 3 2 1

+3VS

U59A
2mA

1
D +3V D
C624 C619
C628 C621 R648
10UF/10V 0.1UF 0.1UF VCC_RIN_CB 2 1 J18 AD19/A25 <33>

2
0.01UF CADR25
CADR24 J15 AD17/A24 <33>
+1.8V 0Ohm C1 K16
NC2 CADR23 CFRAME#/A23 <33>
VCC_RIN_CB
37mA CADR22 L16 CTRDY#/A22 <33>
58mA 1 2 CADR21 L18 CDEVSEL#/A21 <33>
R649 0Ohm D1 M16
NC3 CADR20 CSTOP#/A20 <33>

1
/* C623 C620 C570 C600 C604 N19
+3V CADR19 CBLOCK#/A19 <33>
C629 U59B C608 N16
CADR18 RFU/A18 <33>
10UF/10V 0.1UF 0.1UF 10UF/10V 0.1UF 1000PF 1000PF E1 P16 R619
AD16/A17 <33>

2
NC4 CADR17
W3 VCC_PCI3V_1 VCC_3V_1 F5 CADR16 L19 1 2 CCLK/A16 <33>
R11 J19 K15 22Ohm
VCC_PCI3V_2 VCC_3V_3 CADR15 CIRDY#/A15 <33>
1 2 VCC_ROUT_CB R12 K19 C2 N18 SHIELD GND
VCC_PCI3V_3 VCC_3V_4 NC5 CADR14 CPERR#/A14 <33>
1

1
R615 0Ohm C606 C593 N15 C612
CADR13 CPAR/A13 <33>
/* K18 L.C.A
0.1UF 0.1UF CADR12 CBE2#/A12 <33> 5PF
R6 G5 1 2 D2 R18 AD12/A11 <33>
2

2
VCC_RIN_1 VCC_3V_2 NC6 CADR11

1
E13 +3V C601 R286 0Ohm U19
VCC_RIN_2 CADR10 AD9/A10 <33>
1 2 L1 VCC_ROUT_1 CADR9 R19 AD14/A9 <33>
R647 0Ohm /* E14 A4 0.1UF E2 P15

2
VCC_ROUT_2 VCC_MD3V NC7 CADR8 CBE1#/A8 <33>
2 1 R7 REGEN# CADR7 J16 AD18/A7 <33>

1
R646 100KOhm C579 H15
CADR6 AD20/A6 <33>
J1 C564 E4 H18
<18,29,31> PCI_AD[31:0] GND1 NC8 CADR5 AD21/A5 <33>
J5 10UF/10V 1000PF G15 AD22/A4 <33>

2
PCI_AD31 GND2 CADR4
M2 AD31 GND3 K5 CADR3 G18 AD23/A3 <33>
PCI_AD30 M1 E9 F15
AD30 GND4 CADR2 AD24/A2 <33>
PCI_AD29 N5 R10 F18
AD29 GND5 CADR1 AD25/A1 <33>
PCI_AD28 N4 T10 E16
AD28 GND6 CADR0 AD26/A0 <33>
VCC_ROUT_CB PCI_AD27 N2 V10
PCI_AD26 AD27 GND7
N1 AD26 GND8 W10 CDATA15 U18 AD8/D15 <33>
1

C587 C609 PCI_AD25 P5 L15 W18


AD25 GND9 CDATA14 RFU/D14 <33>
PCI_AD24 P4 M19 V17
AD24 GND10 CDATA13 AD6/D13 <33>
0.47U 0.47U PCI_AD23 R4 A9 V16 AD4/D12 <33>
2

PCI_AD22 AD23 AGND_1 CDATA12


R2 AD22 AGND_2 B9 CDATA11 V15 AD2/D11 <33>
PCI_AD21 R1 D9 B19
PCI_AD20 AD21 AGND_3 CDATA10 AD31/D10 <33>
T2 AD20 AGND_4 D14 CDATA9 C18 AD30/D9 <33>
PCI_AD19 T1 A15 D18
AD19 AGND_5 +3V CDATA8 AD28/D8 <33>
C PCI_AD18 U2 B15 W17 C
AD18 AGND_6 CDATA7 AD7/D7 <33>
PCI_AD17 U1 W16
AD17 CDATA6 AD5/D6 <33>
PCI_AD16 V1 F4 W15
AD16 TEST CDATA5 AD3/D5 <33>

2
PCI_AD15 T7 R599 T15
AD15 CDATA4 AD1/D4 <33>
PCI_AD14 V7 R14
AD14 CDATA3 AD0/D3 <33>
PCI_AD13 W7 C19
AD13 CDATA2 RFU/D2 <33>
PCI_AD12 R8 10KOhm D19
AD12 CDATA1 AD29/D1 <33>
PCI_AD11 T8 E19 AD27/D0 <33>

1
PCI_AD10 AD11 CB_HWSUSP# CDATA0
V8 AD10 HWSPND# F2
Open Drain: PCI_AD9 W8
PCI_AD8 AD9
PME#, R9 AD8 SPKROUT F1 SPKRCB <37> E8 MDIO19 OE# T19 AD11/OE# <33>
PCI_AD7 V9 M15
SERR#, AD7 WE# CGNT#/WE# <33>
PCI_AD6 W9 2 1 D8 T18 C595 0.01UF
AD6 MDIO18 CE2# AD10/CE2# <33>
INTn# PCI_AD5 T11 R603 100KOhm V19 1 2
PCI_AD4 AD5 CE1# CBE0#/CE1# <33>
V11 AD4 REG# F16 CBE3#/REG# <33>
PCI_AD3 W11 SPKRCB PULL DOWN : USE SROM B8 H19
AD3 MDIO17 RESET CRST#/RESET <33>
PCI_AD2 T12 A8 G16
AD2 MDIO16 WAIT# CSERR#/WAIT# <33>
PCI_AD1 V12 G1 1 E7 A18
AD1 UDIO5 MDIO15 WP/IOIS16# CCLKRUN#/IOIS16# <33>
PCI_AD0 W12 T305 D7 M18
AD0 MDIO14 RDY/IREQ# CINT#/IREQ# <33>
<18,29,31> PCI_PAR V6 PAR UDIO4 H5 1394_SDA <34> <34> SD/MSDAT3 B7 MDIO13 BVD2 F19 CAUDIO/SPKR_IN#/BVD2 <33>
PCI_C/BE#3 P2 A7 E18
C/BE3# <34> SD/MSDAT2 MDIO12 BVD1 CSTSCHG/STSCHG#/BVD1 <33>
PCI_C/BE#2 W2 H4 E6 H16
C/BE2# UDIO3 1394_SCL <34> <34> SD/MSDAT1 MDIO11 VS2# CVS2 <33>
PCI_C/BE#1 W6 D6 R16
C/BE1# <34> SD/MSDAT0 MDIO10 VS1# CVS1 <33>
PCI_C/BE#0 T9 H2 1 SHIELD GND L.C.A D15
C/BE0# UDIO2 CD2# CCD2# <33>
CB_IDSEL_J P1 T310 2 1 B6 T14
IDSEL <34> SD/MSCLK MDIO09 CD1# CCD1# <33>
H1 1 R595 0Ohm G19
<18,29,31> PCI_C/BE#[3:0] UDIO1 INPACK# CREQ#/INPACK# <33>
M4 T307 A6
<18,20> PCI_REQ#1 REQ# <34> SDCMD_MSBS MDIO08
<18> PCI_GNT#1 M5 GNT# UDIO0/SRIRQ# J4 INT_SERIRQ <17,20,24,27>
V3 SHIELD GND D5 P18
<18,20,29,31> PCI_FRAME# FRAME# MDIO07 IORD# AD13/IORD# <33>
<18,20,29,31> PCI_IRDY# V4 IRDY# IOWR# P19 AD15/IOWR# <33>
<18,20,29,31> PCI_TRDY# W4 TRDY# B5 MDIO06
<18,20,29,31> PCI_DEVSEL# T5 DEVSEL# 90 ohm
<18,20,29,31> PCI_STOP# V5 STOP# INTA# J2 PCI_INTB# <18,20,31> A5 MDIO05 USBDP V14
<18,20,29,31> PCI_PERR# W5 PERR# USBDM W14
<18,20,29,31> PCI_SERR# T6 SERR# INTB# K4 PCI_INTA# <18,20> <34> SD/MSPWR B4 MDIO04
CB_GBRST# G2 K2 B3
GBRST# INTC# PCI_INTC# <18,20,29> <34> SDWP# MDIO03
B <18,22,29,31> PCI_RST# L4 PCIRST# 1 2 B
K1 L2 A3 R637 100KOhm +VCCCB
<21> CLK_CBPCI PCICLK NC1 MDIO02

<17,20,24,27,31> PM_CLKRUN# L5 CLKRUN# <34> MSCD# A2 MDIO01 VPPEN1 W13 AVPP1 <33>

2
<29,31> PCI_PME# G4 RI_OUT#/PME# VPPEN0 V13 AVPP0 <33>
B1 T13 R634
<34> SDCD# MDIO00 VCC3EN# AVCC3# <33>
VCC5EN# R13 AVCC5# <33> 100KOhm
/*
1

C603 C611 MDIO00--> SD Card Detect

1
/* MDIO01--> MS Card Detect CCLKRUN#/IOIS16#
L.C.A 5PF 5PF MDIO02--> XD Card Enable
2

L.C.A MDIO03--> SD Write Protect XD Card Ready/Busy#


R1.1-S01 MDIO04--> SD/MS/XD Card Power0 Control
VCC_3V POWER : MDIO05--> XD Card Write Protect R5C841 R1.1-S10
PME#, SPKROUT, RI_OUT# MDIO06--> SD/MSXD LED
MDIO07--> SD/MS External Clock
HWSUSP#, GBRST#, IRQn MDIO08--> SD Command/MS Bus State /XD Card Write Enable GBRST# POWER SEQ
CCD1#, CCD2#, VS1# , VS2# MDIO09--> SD/MS Clock /XD Card Read Enable +3V ==> (GBRST#/CB_HWSUSP#) ==>PCIRST#
TEST, VCC5EN#, VCC3EN# R5C841 MDIO10--> SD/MS/XD Data 0
VPPEN0, VPPEN1, SD/MS I/F MDIO11--> SD/MS/XD Data 1
MDIO12--> SD/MS/XD Data 2 H/W SUSPEND# POWER SEQ :
MDIO13--> SD/MS/XD Data 3 SUSPEND : CB_HWSUSP# LO=> PCIRST# LO=> +3VS OFF
VCCPCI POWER : MDIO14--> XD Data 4 RESUME : +3VS ON => PCIRST# HI=> CB_HWSUSP# HI
PCI BUS PCI_AD17 2 1 CB_IDSEL_J MDIO15--> XD Data 5
R616 100Ohm MDIO16--> XD Data 6 UDIO03 H : Enable SD
MDIO17--> XD Data 7 1 2 PM_SUSB# <4,17,21,29,37,40,43,48,52>
VCC_SLOT POWER : CB_GBRST# 2 1 +3V ==> CB_GBRST# MDIO18--> XD Card Command Latch D50 RB751V_40 UDIO04H : Enable MS
+3V
CARD_BUS, R604 100KOhm 1ms < T < 100ms MDIO19--> XD Card Address Latch /* VPPEN0 L : Disable XD
CAUDIO , CSTSCHG 1 2 CB_HWSUSP# 1 2 CB_SD# <17,20>
D46 RB751V_40
C598 0.22UF

R2.0-S13

A A

Title : PCI CARDBUS R5C841


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 32 of 57
5 4 3 2 1
5 4 3 2 1

AVCC_PHYCB:Must not be off on the suspend


mode because of the power supply for Cable
interface block
L85 37mA AVCC_PHY_CB
R1.1-S32 +VCCCB +5V
+3V 1 2

1
120Ohm/100Mhz C575 C578 C576 C569
C565

1
10UF/10V 0.1UF 1000PF 0.1UF 1000PF C539

2
C547
U52 10UF/10V 0.1UF CON Part Number Modify as M3N

2
VCC5_EN 1 16
D
VCC3_EN VCC5_EN GND D
2 VCC3_EN VCC5IN2 15
3 14 /*
<32> AVPP0 EN0 VCCOUT3 +3V
<32> AVPP1 4 EN1 VCC5IN1 13
5 12 +VPPCB +VCCCB
FLG VCCOUT2
6 NC1 VCC3IN 11
7 NC2 NC3 10

1
+3V 8 9 C537
+VPPCB VPPOUT VCCOUT1

1
U59C C546 C303 C296
R5531V002 10UF/10V 0.1UF C304 C291

2
1
C523 10UF/10V 0.1UF 0.1UF 10UF/10V

2
1

1
C536 C528
0.1UF /*

2
0.1UF 0.1UF

2
CPS D11 E10 AVCC_PHY_CB
CPS AVCC_PHY_1 CON8
AVCC_PHY_2 E11
AVCC_PHY_3 A17
AVCC_PHY_4 B17 1 GND_01 12-160400683
<32> AD0/D3 2 AD0/D3
<32> AD1/D4 3 AD1/D4
<32> AD3/D5 4
TPBIAS0 D12 TPBIAS0
TPBIAS0 <34> FOR PCMCIA DEBUG CARD <32>
<32>
<32>
AD5/D6
AD7/D7
CBE0#/CE1#
5
6
7
AD3/D5
AD5/D6
AD7/D7
CBE0#/CE1#
8
X2_1394 A16 XI If delete debug card function,R876 <32>
<32>
<32>
AD9/A10
AD11/OE#
AD12/A11
9
10
AD9/A10
AD11/OE#
AD12/A11

A13 TPB0-_1
and R628 mount 0 ohm. <32>
<32>
<32>
AD14/A9
CBE1#/A8
CPAR/A13
11
12
13
AD14/A9
CBE1#/A8
TPBN0 TPB0-_1 <34> +3V PAR/A13
<32> CPERR#/A14 14 PERR#/A14
X1_1394 B16 B13 TPB0+_1 15
XO TPBP0 TPB0+_1 <34> <32> CGNT#/WE# GNT#/WE#
<32> CINT#/IREQ# 16 INT#/IREQ#/READY

1
CBDEBUGEN# 17
R503 VCC1
1 2 Layout: SHIELD GND 18 VPP1
C573 0.01UF 19
TPA0-_1 Q99 10KOhm <32> CCLK/A16 CCLK/A16
TPAN0 A12 TPA0-_1 <34> <32> CIRDY#/A15 20 IRDY#/A15
2N7002

1
<32> CBE2#/A12 21

2
CBE2#/A12

G
C 1394_FIL A14 B12 TPA0+_1 22 C
FIL0 TPAP0 TPA0+_1 <34> <32> AD18/A7 AD18/A7
VCC5_EN

2 S

3
<32> AVCC5# <32> AD20/A6 23 AD20/A6

D
<32> AD21/A5 24 AD21/A5
<32> AD22/A4 25 AD22/A4
1 2 B14 REXT <32> AD23/A3 26 AD23/A3
R592 10KOhm R876 1 2 0Ohm 27
<32> AD24/A2 AD24/A2
1% CINT#/IREQ# 1 T315 /* 28
<32> AD25/A1 AD25/A1
CSERR#/WAIT# 1 T158 29
<32> AD26/A0 AD26/A0
1394_REF D13 CREQ#/INPACK# 1 T184 R628 30
VREF <32> AD27/D0 AD27/D0
CAUDIO/SPKR_IN#/BVD2 1 T159 2 1 VCC3_EN 31
<32> AVCC3# <32> AD29/D1 AD29/D1
1 2 <32> RFU/D2 32 RFU/D2
C581 0.01UF CSTOP#/A20 1 T172 10KOhm <32> CCLKRUN#/IOIS16# 33
CDEVSEL#/A21 T313 CCLKRUN#/IOIS16#/WP
E12 NC9 1 34 GND_02
CTRDY#/A22 1 T308 35
CIRDY#/A15 T303 CBDEBUGEN# CCD1# GND_03
1 2 1 36 CCD1#/CD1#
<32> AD2/D11 37 AD2/D11

1
CSTSCHG/STSCHG#/BVD1 1 T147 D39 RB751V_40 C281 38
<32> AD4/D12 AD4/D12
CBLOCK#/A19 1 T149 39
<32> AD6/D13 AD6/D13
CPERR#/A14 1 T162 270PF/50V 40
<32> RFU/D14

2
CCLKRUN#/IOIS16# T157 RFU/D14
1 <32> AD8/D15 41 AD8/D15
<32> AD10/CE2# 42 AD10/CE2#
<32> CVS1 43 CVS1/VS1#
U30 44
<32> AD13/IORD# AD13/IORD#
D10 3 2 CCLKRUN#/IOIS16# 45
TPBIAS1 <21> CLK_DBPCI A0 C0 <32> AD15/IOWR# AD15/IOWR#
7 6 CAUDIO/SPKR_IN#/BVD2 46
<17,24,27,36> LPC_FRAME# A1 C1 <32> AD16/A17 AD16/A17
11 10 CPERR#/A14 47
<17,24,27,36> LPC_AD0 A2 C2 <32> RFU/A18 RFU/A18
17 16 RFU/D2 48
<17,24,27,36> LPC_AD1 A3 C3 <32> CBLOCK#/A19 CBLOCK#/A19
21 20 RFU/D14 49
<17,24,27,36> LPC_AD2 A4 C4 <32> CSTOP#/A20 STOP#/A20
<32> CDEVSEL#/A21 50 DEVSEL#/A21
4 5 RFU/A18 51
<17,24,27,36> LPC_AD3 B0 D0 VCC2
A11 TPB1-_1 8 9 CSERR#/WAIT# 52
TPBN1 <36> DIS_FWH B1 D1 VPP2
1 14 15 CBLOCK#/A19 53
B2 D2 <32> CTRDY#/A22 TRDY#/A22
B11 TPB1+_1 T148 18 19 54
TPBP1 B3 D3 <32> CFRAME#/A23 FRAME#/A23
22 B4 D4 23 <32> AD17/A24 55 AD17/A24
+5V 56
<32> AD19/A25 AD19/A25
<32> CVS2 57 CVS2/VS2#
CBDEBUGEN# 1 24 58
BE# VCC <32> CRST#/RESET RST#/RESET
B TPAN1 A10 13 BX GND 12 <32> CSERR#/WAIT# 59 SERR#/WAIT# B
<32> CREQ#/INPACK# 60 REQ#/INPACK#
TPAP1 B10 74CBT3383 <32> CBE3#/REG# 61 CBE3#/REG#
<32> CAUDIO/SPKR_IN#/BVD2 62 CAUDIO/SPKR#
PCMCIA DEBUG CARD MUX <32> CSTSCHG/STSCHG#/BVD1 63 CSTSCHG/STSCHG#
<32> AD28/D8 64 AD28/D8
<32> AD30/D9 65 AD30/D9
<32> AD31/D10 66 AD31/D10
<32> CCD2# 67 CCD2#/CD2#
68 GND_04 NP_NC1 73
+3V 69 74
HC1 NP_NC2

1
1 2 C335 70
+3V HC2
R259 100KOhm 71
3 HC3
D Q31
14

72

2
U51A 270PF/50V HC4
1 VCC +3VALWAYS
<32> CCD1# 1
3 TX25-80P-6ST-H1
CSTSCHG/STSCHG#/BVD1 2 G
GND LV08A 2 S 2N7002

2
7

U29A C273
2

R483 0.1UF

1
1
R5C841 3 6 CCD1# CCD2#

CLR
1MOhm CK Q#
CBDEBUGEN#
L L 16bit
2 5
PCMCIA
1

D Q OTHER 32bit
R260 C274
7 GND VCC 14 CL
PR

+3V 2 1 1 2

100KOhm 0.1UF
4

X5 Main Source is 07-010222450 (TXC) SN74LVC74APWR


Second source is 07-010722451 (Fujicom)
X5
X2_1394 1 2 X1_1394

24.576MHZ
A TXC 16PF/30PPM 8*4.5*1.6mm A
07-010222450
2

C563 C562
22PF 22PF
1

R2.0-S09

Title : PCI PCMCIA SOCKET A


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 33 of 57
5 4 3 2 1
5 4 3 2 1

CON Part Number Modify as M3N

D D

2 1 1 2
1394A R590 56Ohm
1%
C567 0.01UF

2 1 1 2
6

U23 CO-LAYOUT R591 56Ohm C574 0.33U


1 LTPB0- 1%
6

1
7 7 TPBIAS0 <33>

TPA0-_1 <33> +3V


8 8 LTPA0- R196 2 1 0Ohm
LTPA0+ R195 2 TPA0+_1 <33>
1 0Ohm
2 LTPB0+ LTPB0- R193 2 1 0Ohm
2 LTPB0+ R194 2 TPB0-_1 <33>
1 0Ohm

1
C544
TPB0+_1 <33>

2
LTPA0- TPA0-_1

3
0.1UF R550 R551

2
L35 U57
200Ohm 2 1 2 1 1 8 10KOhm 10KOhm
LTPA0+ /* TPA0+_1 R589 56Ohm R582 5.11KOhm A0 VCC
2 7

1
1% A1 WP
3 A2 SCL 6 1394_SCL <32>
3 LTPA0- LTPB0+ TPB0+_1 2 1 1 2 4 5
3 GND SDA 1394_SDA <32>

3
R588 56Ohm C566 270PF/50V
L34 1% AT24C02N
200Ohm
LTPB0- /* TPB0-_1

2
1.CLOSE TO R5C592
4 LTPA0+ 2.The area is as compact as possible,length < 10 mm
4
CO-LAYOUT 3.TPA Pair and TPB pair mismatch < 2.5mm
IEEE1394_CON4P
4.No via recommend , maxmium is one.
5.Total length < 50 mm
C C
6.Differential impedance is 110+/- 6 ohm
7.TPA Pair trace or TPB pair trace mismatch < 1.25mm

B B

Solve MS Duo Adaptor


short problem
2N7002
<32> SDCMD_MSBS CON Part Number Modify as ME SD/MSDAT1 SD_DAT1

2 S
D
<32> SD/MSDAT1

3
<32> SD/MSDAT0

G
<32> SD/MSDAT2
Q106 2N7002

1
<32> MSCD#
<32> SD/MSDAT3 +3V SD/MSDAT2 SD_DAT2

2 S
D
<32> SD/MSCLK

G
Q105

1
2

+MC_VCC
R659

2
2
R1.1-S27 10KOhm
S
Q139
R1.1-S32 +12V 2 1 SD_CD
1

SI2301DS
11 R543 10KOhm
G
3 D
1

+MC_VCC
3
D 3
R809 3
D
150KOhm Q138 Q107
19
18
17
16
15
14
13
12
11
10

CON18 1
<32> SD/MSPWR
2

G 2N7002 SDCD# 1 2N7002


19
18
17
16
15
14
13
12
11
10

2 S
1

1
21 C602 C627 G
21 SDCD# <32> 2 S
Place as close to
24 25 +MC_VCC 0.1UF 0.1UF card reader socket
SDWP# <32>
2

2
NP_NC1 NP_NC2
22 22 as possible
2

23 8 SD_DAT1 R631
SD_DAT2 GND 8 SD/MSDAT0
A 9 9 7 7 10KOhm A
SD/MSDAT3 1 6 3
D
SDCMD_MSBS 1 6 SD/MSCLK
2 5
1

2 5 Q131
3 3
4 20 1
4 20 G SI2304DS
CARD_READER_19P 2 S

Title : PCI IEEE1394A & 3 IN1 CON


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 34 of 57
5 4 3 2 1
5 4 3 2 1

R1.1-S12
+VCORE

C221
2 1 +3VS

2
1 2 FAN1_PWM
0.1UF R172 R160 150KOhm
D +5VS D
1 2 FAN1_DC +5VS_FB1
0Ohm

2
U22 +5VS R156 150KOhm

2
SDA_3S 1 24 FAN1_PWM R157
<12,13,21,28> SDA_3S

1
SDA PWM1/XTO

1
SCL_3S 2 23 C200 C187 R152
<12,13,21,28> SCL_3S SCL Vccp 10KOhm
3 22 OD SMB_ALERT#

1
GND 2.5V/SMBALERT# 1UF/10V 1UF/10V

G
4 21

2
VCC 12V/VID5 5V/THERM# PM_THRM# 10MOhm
5 20

S 2
PM_THRM# <17,20>

1
VID0 5V/THERM#

2
C209 ADD_SEL /*

D
6 VID1 VID4 19
7 18 Q19
VID2 D1+ H_THERMDA <4>
0.1UF 8 17 /* 2N7002
H_THERMDC <4>

1
VID3 D1-

2
9 TACH3 D2+ 16
10 15 R154
FAN1_TACH PWM2/SMBALERT# D2- ADD_SEL
11 TACH1 TACH4/ADDRESS_SELECT/THERM# 14 5V/THERM# <43>
12 13 10KOhm +5VS
TACH2 PWM3/ADDRESS_ENABLE# /*

1
ADT7463 +3VS
Salve address 2 1 FAN1_PWM
ADD_SEL L= 0x2C R162 10KOhm
C201 1000PF GND 2 1 FAN1_TACH
ADD_SEL H= H_THERMDC 1 2 H_THERMDA R159 10KOhm
0x2D
PM_THRM# function select one 5/10/10 mil
BIOS setting: 2 1 SMB_ALERT#

105 degree will down CPU frequence. 1. Fan full speed R174 10KOhm
/* R1.1-S12
110 degree will shutdown system. 2. Fan full speed & Throttling function
3. Fan full speed & Critical Shutdown

C C

CON Part Number Modify as M3N


Q86 SI2301DS

2 3 +5VS_FAN1 FAN1_TACH

3 D
+12VS +5VS

2
2

4
R446 CON16

1
C467 1 HOLD1

11
C174
2
2 1 1KOhm 0.1UF 3

2
B B
/* HOLD2

1
0.1UF 2 1 WtoB_8P

5
R447 1KOhm
U21 OK
FAN1_ON# +5VS_FAN1 3 A+ + VCC 8
1 FAN1_ON_R# 1 2 FAN1_ON#
3 +5VS +5VS_FB1 2 A- - AO R448 1KOhm
D
Q85 5 B+ +
1 BO 7
G 2N7002 6 B- - GND 4
2 S +5VS_FAN1
LM358DR
R151 C179

1
+5VS_FB1 1 2 2 1 FAN1_ON_R# + + C456
CE16
<27> WATCHDOG
100KOhm 0.1UF /* 22uF/6.3V
1

/* 47UF/6.3V

2
C446
1UF/10V CO-LAYOUT
2

/*

A A

Title : FAN CONTROL


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 35 of 57
5 4 3 2 1
5 4 3 2 1

D D

FWH BIOS SOCKET


+3VS
C493 C485
0.1UF 0.1UF

1
C486
10uF/10V

2
R469
100Ohm
1 2 BUF_PCI_RST#
<6,8,17,18,22,24,27> BUF_PLT_RST# CLK_FWHPCI <21>

FWH_FGPI2
FWH_FGPI3

FWH_FGPI4

1
+3VS C484

2.7KOhm
5PF

2
2

32
31
30
4
3
2
1
R477
R475

VPP

R/C#/CLK
A8
A9
RST#

VCC2

A10
C FWH_FGPI1 5 29 2 1 C

1
FWH_FGPI0 A7 IC
6 A6 GNDA 28
7 A5 VCCA 27 2.7KOhm
<17,20> FWH_WP# 8 A4/TBL# GND2 26
9 A3 VCC1 25
10 24 FWHHINIT#
A2 INIT#/OE# FWH_INIT# <17>
11 23 LPC_FRAME#
A1 WE# LPC_FRAME# <17,24,27,33>
<33> DIS_FWH 12 A0 RY/BY# 22
13 DQ0 DQ7 21

GND1
DQ1
DQ2

DQ3
DQ4
DQ5
DQ6
U50

14
15
16
17
18
19
20
WHUB
05-001017122
LPC_AD0
<17,24,27,33> LPC_AD0
LPC_AD1
<17,24,27,33> LPC_AD1
LPC_AD2
<17,24,27,33> LPC_AD2
LPC_AD3
<17,24,27,33> LPC_AD3

FWH SOCKET(S/R and E/R use it.)


Part Number :12-043000321
FWH IC (P/R use it.)
SST 49LF004A-33-4C-N
Part Number :05-001017122

B B

R2.0 has changed WHUB socket symbol


to BIOS IC 05-001017122.
AMI BIOS LABEL P/N:15-135001010.
It need to add in P/R 59-MID BOM by ME.

A A

Title : FWH BIOS


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 36 of 57
5 4 3 2 1
A B C D E

SPDIF_A <38>

1 R_41_A C397 2 1 1UF/10V /* 1

+3VS +3VS_AUD R1.1-S09 L_39_A C402 2 1 1UF/10V /*

2
L31
1 2 R797 +5V_AUD R58
10Ohm 20KOhm 1%

1
80Ohm/100Mhz C132 1 2
C115 C82

1
10uF/10V 0.1UF 0.1UF /*

2
AGND_A
/*
1 /* 2

U16 R798
ALC880_H 39.2KOhm 1% +5V

48
47
46
45
44
43
42
41
40
39
38
37
02-611000413

LFE_OUT
CEN_OUT
SPDIFO

AVDD2
SPDIFI/EPAD

SURRBACK_OUT_L

AVSS2

SURR_OUT_L

LINE1_VREFO_R
SURRBACK_OUT_R

SURR_OUT_R
JDREF/NC

1
AGND_A
R799
10KOhm
+3VS_AUD R1.1-S07
/*

2
R1.1-S08 R864 2 1 0Ohm OUTR_A <38>
1 36 R_36_A
DEL_POP DVDD1 FRONT_OUT_R L_35_A R865 2 0Ohm
<38> DEL_POP 2 GPIO0 FRONT_OUT_L 35 1 OUTL_A <38>
3 GPIO1 Sense_B 34
4 DVSS1 DCVOL 33
<17> Azalia_SDOUT_AUD 5 SDATA_OUT MIC1_VREFO_R 32
R67 1 2 0Ohm Azalia_BCLK_D 6 31
2 <17> Azalia_BCLK_AUD
R73 7
BITCLK LINE2_VREFO
30 R1.1-S08 2
DVSS2 MIC2_VREFO
<17> Azalia_SDIN0 1 2 8 SDATA_IN LINE1_VREFO_L 29
C380 9 28
0.1UF D33 33Ohm DVDD2 MIC1_VREFO_L VREFOUT_A <39>
C410 <17> Azalia_SYNC_AUD 10 SYNC VREF 27
2 1 R374 1KOhm 2 11 26
<32> SPKRCB <17,38> Azalia_RST#_AUD RESET# AVSS1
3 2 1 MONO_CODEC_A 12 25
PCBEEP AVDD1
1

CD_GND
LINE2_R

LINE1_R
Sense_A
LINE2_L

LINE1_L
MIC2_R

MIC1_R
MIC2_L

MIC1_L
0.1UF

1
CD_R
R372 1KOhm C88

CD_L
2 1 C99
<17,20> ICH_SPKR

1
DAN202K C85 10PF +5V_AUD C129 C103
C379 10PF /* 10uF/10V 0.1UF 1UF/10V

2
0.1UF /* /*

13
14
15
16
17
18
19
20
21
22
23
24
1

AGND_A
R373 R375 R395
10KOhm C138 R1.1-S14
10KOhm 1UF/10V AGND_A
10KOhm R88 2 1
2

<38> SE/BTL#_A 1 2
R1.1-S26 40.2KOhm 2 1 MIC_A <39>

/* C137
1UF/10V
C134 R397
<38> HEADPHONE_L
2 1 1 2 CD-L_A <22>

2
1UF/10V 47KOhm
<38> HEADPHONE_R
R410
R1.1-S06 47KOhm
3 3

1
C135 R398
HeadPhone use Pin14 and Pin15.When HeadPhone AGND_A
2 1 1 2 CD_GND_A <22>
plug-in then H/W will disable internal

2
47KOhm
speaker. 1UF/10V
R411
Internal and External Microphone use Pin21 and 47KOhm

Pin22.When external MIC plug-in then H/W will

1
disable internal Microphone.
C136 R399
AGND_A
2 1 1 2 CD-R_A <22>

2
1UF/10V 47KOhm
R412
47KOhm

1
AGND_A

4 4

Vout=1.250*(1+A/B)=4.842
06-007191010 IS G913C +5V_AUD R433 1 2 0Ohm
<4,17,21,29,32,40,43,48,52> PM_SUSB#
U12
+5V
>30 mil or shape 1 5 2 1 R388 1 2 0Ohm
L28 SHDN# SET C390 2200P
2 GND
1 2 3 IN OUT 4 2 1
R370 100KOhm
2

80Ohm/100Mhz R425 1 2 0Ohm


A
1

G913C R377 C80


1

DIGITAL C74 34.8KOhm C81 C139


C70 B 10uF/10V 0.1UF 0.1UF
2

0.1UF
AGND_A
2

R369 1 2 0Ohm
5 10uF/10V /* 5
34K/1% for MAX8863
34.8K/1% for G913C
AGND_A

Title : AUDIO CODEC ALC880-H


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 37 of 57
A B C D E
A B C D E

+5VAMP +5VAMP

+5VS +5PVDD
L33

1
1 2

1
R117

1
80Ohm/100Mhz C146 C152 C148 CON Part Number Modify as ME
10KOhm

2
10uF/10V 1UF/10V
R2.0-S12

2
+5VAMP 0.1UF SE/BTL#_A Close to OP
AGND_A

2
1 1
AGND_A
R429 R848 U37
10KOhm SPKR+_MB_A L51 1 2 220Ohm/100Mhz SPKR+_MB_CON_A 5
10KOhm GAIN0 GAIN1 SE/BTL# AV (V/V) NC1
1 1
0 0 0 -2(DEFAULT) SPKR-_MB_A L49 1 2 220Ohm/100Mhz SPKR-_MB_CON_A 2

1
+5VAMP +5PVDD 0 1 0 -6 2
3 3
1 0 0 -12 SPKL+_MB_A L48 1 2 220Ohm/100Mhz SPKL+_MB_CON_A 4
/* /* +5PVDD R431 1 1 0 -24 4
NC2 6

2
1 2 X X 1 -1 SPKL-_MB_A L50 1 2 220Ohm/100Mhz SPKL-_MB_CON_A

2
R430 R849 R432 WtoB_CON_4P
0Ohm 0Ohm 1 0OHM 2
U17
1 24 0OHM

1
GND1 GND4
2 23

1
GAIN0 RLINEIN

2
4
6
8
3 GAIN1 SHUTDOWN# 22 OP_SD# <17,20>
SPKL+_MB_A 4 21 SPKR+_MB_A CN2A
CN2B
CN2C
CN2D
LOUT+ ROUT+
AGND_A 5 LLINEIN RHPIN 20 1 2 1 2 OUTR_A <37> 150PF
150PF
150PF
150PF
1 2 1 2 6 19 R105
<37> OUTL_A LHPIN VDD
R104 C145 7 18 C144 0Ohm

1
3
5
7
PVDD1 PVDD2

2
0Ohm 1UF/10V 8 17 1UF/10V
RIN HP/LINE#

2
SPKL-_MB_A 9 16 SPKR-_MB_A R91
R103 LOUT- ROUT- SE/BTL#_A
10 15
AUDIO 39KOhm
/*
11
12
LIN
BYPASS
SE/BTL#
PC-BEEP 14
13
39KOhm
/*

1
GND2 GND3

1
OUT

2
C151 C155 C161 /* /* /* /*
TPA0212 TSSOP 24
R2.0-S12 0.47U 0.47U 0.47U AGND_A
AGND_A R2.0-S12

1
AGND_A AGND_A

2
AMP 2

AGND_A

+5VAMP
CON Part Number Modify as ME
+5VS

2
U44
+5VAMP 1 A 5 R404 R406
<37> SPDIF_A VCC
2 3 OPTIC_VCC_A 2 B 10KOhm 10KOhm 5 J1
S

3 D
2

1
1

3 GND 4 SPDIF_O_A 2
G

1
Q75 SI2301DS Y
11

3
NC7SZ08M5 OPTIC_HP_A 1 2 1

1
2 1 R380 C398 L71 1KOhm/100MHz
2

R409 100KOhm 100KOhm 1UF/10V C420


2

3 Digital 100PF/50V
D

2
Q76
11
OPTIC_HP_A 1 2_AJK_R_A 1 2 HP_JACK_R_A 12
G 2_AJK_L_A L72 1 21KOhm/100MHz HP_JACK_L_A
2 S 2N7002 L75 1KOhm/100MHz
HP_IN_A# C427 HP_IN_A# 1 2

1
100PF/50V
C422 L70
R800 R801 100PF/50V 1KOhm/100MHz

2
HEADPHONE_R 1 0Ohm 2 1 0Ohm 2 SPKR+_MB_A
<37> HEADPHONE_R
/* OPTIC_VCC_A 1 2 1 2 8
3 SPDIF_O_A D8 RB751V_40 L74 1 2 1KOhm/100MHz 7 3
R1.1-S06 L73 1KOhm/100MHz

1
12-140101080

10
6
9
1

1
C424 C425
C417
HP_R_MOS_S

100PF/50V

2
0.1UF 100PF/50V

2
+3V +12V
22UF instead of 47UF for space AGND_A R2.0-S03 modify 0106
2

CE5
2

J1 Original P/N is 12-140001088


+

R426 R427 1 2 AOUTR_C_A 1 2 2_AJK_R_A


100KOhm 1MOhm HP_L_MOS_D R112 100Ohm need to change to 12-140101080 in BOM.
1

22UF/10V
MUTE_EN R1.1 has changed it in symbol.
1

R870
CE6
4

22KOhm Q13
4

Q12 SI1902DL 1 2 AOUTL_C_A 1 2 2_AJK_L_A


S2

G2

D1

SI1902DL R116 100Ohm


S2

G2

D1
1

1
Q11 3 22UF/10V CN1
D
1

2N7002 R110 R90 5


R802 R803 1KOhm 1KOhm L68 4 7
MUTE 1 1KOhm/100MHz
G1
D2

3 8
S1

2
G 1KOhm 1KOhm INT_MIC_JACK_A 1_AJK_A
G1
D2

1 2 6 9
S1

2 S
1

3 1 2 MIC_JACKIN 2 10
D <39> MIC_IN_A
3

C149 1 L
3

4 Q10 2.2UF/16V L67 AUDIO JACK 4


MIC
2

DEPOP# 1 2N7002 /* /* AGND_A


1KOhm/100MHz
G C394 PHONE_5P
2 S
AGND_A AGND_A

1
100PF/50V

WtoB_2P L25

2
HP_R_MOS_D 120Ohm/100Mhz JPA1
NC2 4
MIC_AGND_A
CON Part Number Modify as M3N
SPKL+ 2 1 2 1 2
AGND_A 1 INT_MIC_A 1 2 INT_MIC_JACK_A
SPKL-
HP_L_MOS_S

3 SHORTPIN
NC1 L26 /*

1
U9 1KOhm/100MHz
R1.1-S25 C67
MGND

R1.1-S06 100PF/50V

2
R804 R805
HEADPHONE_L 1 0Ohm 2 1 0Ohm 2 SPKL+_MB_A
<37> HEADPHONE_L
/* CON Part Number Modify as ME MGND

+3V

R428 1 2 0OHM
2

R56
100KOhm SE/BTL#_A
SE/BTL#_A <37>
D9 RB751V_40 R376 1 2 0OHM
2 1 3
D
1

D6
1 Q15
<17,37> Azalia_RST#_AUD 1
AGND_A
3 DEPOP# 1 2 2N7002
5 OP_SD# 2 G R880 1 2 0Ohm 5
R115 2.2MOhm 2 S /*
1

DAP202K C162
R881 1 2 0Ohm
R1.1-S08 0.47U /*
2

2 1 3 Q14
<37> DEL_POP D
D75
RB751V_40
AGND_A
1 HP_IN_A#
Title : AUDIO_AMP_MB (TPA0212)
/*
S 2
G ASUSTECH CO.,LTD. Engineer: Sam Wang
2N7002 Size Project Name Rev
C Z61Ae 2.0
AGND_A Date: Thursday, June 09, 2005 Sheet 38 of 57
A B C D E
A B C D E

Azalia MDC MODEM


E E

CON Part Number Modify as A4S

13
15
17
19
CON5 +3V

GND1
GND3
GND5
NP_NC2 NP_NC1
1 1 2 2
<17> Azalia_SDOUT_MDC 3 3 4 4
5 5 6 6
<17> Azalia_SYNC_MDC 7 7 8 8
<17> Azalia_SDIN1 9 9 10 10

GND2
GND4
GND6
<17> Azalia_RST#_MDC 11 11 12 12 Azalia_BCLK_MDC <17>

BTOB_CON_12P

14
16
18
20

1
C419 C418
C421
D 0.1UF/25V 0.1UF/25V 10PF D

2
/*
R1.1-S05

C C

R2.0-S10

2 1
R54 100KOhm MIC AMP
1 2
R55 100KOhm +5V_AUD

AGND_A
U14 L30
Bias voltage for MIC1 jack 4490_POS 3 A+ + VCC 8 +5VMIC 1 2
1 2 1 2 1 MIC_A
2.5V/3.75Vreference voltage

1
C116 39P 4490_NEG 2 A- - AO 0Ohm 120Ohm/100Mhz
R57 /* C98
<37> VREFOUT_A 2 1 5 B+ + 0.1UF

2
R392 270KOhm BO 7
1

6 B- - GND 4
B R384 B
AGND_A
1

NJM2100M
C140 C406 10KOhm
10uF/10V 1UF/10V
2

1 2
2

R385
C395 AGND_A
2.2KOhm
2

1UF/10V R69
1

AGND_A AGND_A
200KOhm
AGND_A 1 2

C396 R379
MIC_IN_A 2 1 2 1 1 2
<38> MIC_IN_A MIC_A <37>
C84 39P
10KOhm
1UF/10V

high-pass filter cutoff frequency Gain=-R788/R468=-10


fC=1/(2*3.14*C696*R468)=159 Hz

R807
1 0Ohm 2 MIC_A

/*
R1.1-S13
A A

Title : MIC AMP & MDC Conn.


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 39 of 57
A B C D E
A B C D E

+5V
ZIF_FPC_20P |

1
+5VLCM
PWRLED#
802BTLED#
24
20
18
16
14
SIDE4 SIDE3
20
18
16
14
19
17
15
13
23
19
17
15
13
CHGLED#
EMAILLED#

INTERNET#
+5V
LED BOARD

1
R43
2
BLUE LED
|
EMAILLED#
INSTANT 1
HDDLED# 12 11 NUMLED#

KEY
12 11 MARATHON# 680Ohm
+5VS 10 10 9 9
SCROLLOCK#_R 8 7 E-MAIL
8 7 EMAIL# 3
R1.1-S31 +3VALWAYS
CAPLED#
6 6 5 5
DISTP# LED(BLUE) D
4 4 3 3
PWR_SW# 2 1 LID_SW# Q148 +3V
<43> PWR_SW# 2 1 LID_SW# <15,43> 1
22 SIDE2 SIDE1 21 BT_LED <31>
2N7002 G
S 2
CON3 R52
<27> EMAIL_LED# 1 2

6
0Ohm /*

5 10KOhm
R2.0-S04

RN21C
EMAIL# <27>
+5VLCM

2
| LED BOARD
CHARGE C47
ORANGE LED 1UF/10V

1
LED(ORANGE)
|
CHGLED#
+3V

2
2 1 2 SCROLLOCK#_R R334 2
<27> SCROLLOCK#
680Ohm
R345 560Ohm

8
3 1

7 10KOhm
D28
RB717F

RN21D
1

2
+5VS <48,50> CHG_EN# 3 Q60
INTERNET# <27>
NUM D
2N7002
|

2
LED(GREEN)
LED LED BOARD GREEN LED G
1 ICH6_1HZ C45
1UF/10V
V2.0

1
S 2
| BAT_LOW#
1 2 NUMLED#
<27> NUM_LED#
R344 560Ohm
+5VS +3V

|
GREEN LED LED BOARD

2
+5VS
|

1 10KOhm
3
CAP | HDDLED# 3
1 2 HDD_LED_5S# <22>
LED(GREEN) LED BOARD GREEN LED R357 560Ohm

RN3A
|
1 2 CAPLED#
<27> CAP_LED# MARATHON# <27>
R346 560Ohm

2
+5V C46
| 1UF/10V

1
BLUE LED BOARD
LED
| +3V

4 3 10KOhm
802BTLED# 2 R341 1 WLAN_LED#
+5V 680Ohm

RN3B
|
LED BOARD +3V
GREEN
4 LED DISTP# <27> 4
2

2
PWRLED# R339
POWER 10KOhm C48
Q64 3 3 Q65 1UF/10V
D D

1
2

LED(GREEN) Power LED current limit resistor,if 2N7002 2N7002


1

R335 330 ohm-->get 3.7mA R720


220Ohm 150 ohm-->get 9.7mA 1 0Ohm 2 802_ON_EN 1 1
220 ohm-->get 6.4mA <27,31> 802_ON 802_ACTLED <31>
G G
2 S S 2
1

3
D
Q206 R721
Q61 3 3 Q62 /* D74
D D 390Ohm
2N7002 2N7002 1 802_ON# RB751V_40
802_ON# <24> /*
2N7002 G 2 1 CHECK_MODE
CHECK_MODE <17>
1

1 1 S 2
/*
<17> ICH6_1HZ PM_SUSB# <4,17,21,29,32,37,43,48,52>
G G
2 S S 2 +3V D73
R2.0-S04 RB751V_40
2 1 PM_SUSB
For ASUS WLAN Card. For Intel WLAN PM_SUSB <42,43>
R2.0-S09

2
Card.(Default) R484

1
R2.0-S09

47K
+3V Q30

R-1
<46,52> SUSC#_PWR
Q163
2N7002 U51B

1
1MOhm
14

R-2
47K
1

VCC
G

4 BAT_LOW#_LED <51>
5 BAT_LOW# BAT_LOW#_MOS 5

3
C

2
6
3

S 2

DTC144EK
D

5
GND
LV08A
BAT_LOW#_KBC <27>
7

R1.1-S11
Title : LED BOARD
ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 40 of 57
A B C D E
5 4 3 2 1

D D

SUSB#_PWR_ON <52>
C C
T151
+5V
TPC28t Q34 CON Part Number Modify as M3N

1
1

G
+5VS_TP

2 S

3
+5VS_TP

D
4.86V

1
2N7002 C282
C278
0.1UF
TOUCH PAD CNT

2
0.1UF

+5VS_TP_A

CON7
1 1 11 11
2 2 12 12
INTDATA_5S_A 3 13
+5VS_TP +5VS_TP_A INTCLK_5S_A 3 13
1 2 4 4 14 14
L45 80Ohm/100Mhz 5 15
INTDATA_5S_A 5 15
<27> INTDATA_5S 1 2 6 6 16 16
L46 1 2 1KOhm/100MHz INTCLK_5S_A 7 17
<27> INTCLK_5S 7 17
L47 1KOhm/100MHz 8 18
8 18

1
C275 C277 9 19
9 19
10 10 20 20
100PF

2
1
0.1UF C276 FPC_CON_20P

100PF

2
B B

A A

Title : TouchPad CONN


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 41 of 57
5 4 3 2 1
5 4 3 2 1

POWER DISCHARGE CIRCUIT


D D

+3VS

2
RN70A +5VS
220Ohm
/*

4
+1.5VS +3V
RN70B
220Ohm
+5V
/*

2
Q200A

6
UM6K1N RN71A
PM_SUSB /* 2 RN70C +2.5VS
<40,43> PM_SUSB 220Ohm +12V
220Ohm
1
/*
/*

4
1
3
Q200B RN71B

5
UM6K1N
220Ohm

8
C /* 5 C
RN70D /*
4

6
220Ohm Q202A

2
UM6K1N
/*

6
Q201A PM_SUSC /* 2 RN72A
<43> PM_SUSC +1.8V
UM6K1N

1
/* 220Ohm
2 /*

4
1
RN72B

3
Q202B
220Ohm

2
Q201B UM6K1N
UM6K1N /* /* R871 R872
5
/* 5

3
+1.8VS 330Ohm 330Ohm

4
/* /*

1
2

6
Q203A
R873 UM6K1N
/* 2
330Ohm

1
/* +12VS
1

3
D

3
Q203B
Q204 UM6K1N
1 5
2

G 2N7002

4
2 S /* R874 R875
330Ohm 330Ohm /*
/* /*
1

B B

3
D
Q205
1
G 2N7002
2 S /*

A A

Title : DISCHARGE MOS/EMI


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 42 of 57
5 4 3 2 1
5 4 3 2 1

+3VALWAYS
R2.0-S05 C793
1 R850 2 1 2
1MOhm

1
C615 /* 0.047U
D D
/*

4
0.1UF

2
+3VSUS +3VSUS R623

PR
+3VSUS RST_BTN# 7 14
RST_BTN# <48> GND VCC 3
100KOhm D
2 5 SUSC#_FALL_Q Q172

1
D Q
1

2
R866

CLR
2N7002

1
C357 R324 R322 PWR_ON 2 0Ohm 1 3 6 1
U41A T233 C354 3 /* CK Q# G /*
SW Part Number Modify as M3N D R2.0-S01
2

0.1UF 2 S

2
47KOhm 3 U60A
14

1
100KOhm 1UF/10V Q56 Q133 SN74LVC74APWR R711
1

1
VCC RESET 1 39KOhm

1
RESET PM_RSMRST# R323 G 2N7002 PM_SUSC# 1
1 2 PM_RSMRST# <17>
2 1 3 2 S /* G
D

1
GND 2 S 2N7002
SW1
1

74LVC14APW_T R330 100Ohm Q57 D55


7

1
C359 1 2 1 2 1 R622 1 2 10KOhm
1 2 2N7002 +3VSUS
C798 G
2

10KOhm 1UF/10V
3 4 2 S RB751V_40 R851 2 /* 1 1MOhm +3VALWAYS

2
0.1UF 3 4

2
R2.0-S06
2

/*

1
50mA/12V C353 R626 R877 1 2 330KOhm
0.22UF C617 /* +3VALWAYS

2
0.01UF 100KOhm C616

1
PM_SUSC 1000PF S 2 3 U68
D

1
G
PWR_ON Q173 5 1
1 VCC INB
2N7002 INA 2
1 4 3
+3VALWAYS /* G OUTY GND
If use another power 3
D
S 2
RN55A
2 100KOhm 1
switch method.C616 Q174 74LVC1G08GW

1
mount 0.1uF/0402 2N7002 /*

1
+3VSUS R852 /*
+3VSUS 150KOhm 1MOhm
R607 /*
2

R332

2
1
+3VS R351 +3VALWAYS 51KOhm D76
2 1 AUXPWROK <17>

2
2
150KOhm 0.1UF PWR_ON# 1
14

C 2 1 2 C
100KOhm 74LVC14APW_T 0Ohm /*

1
VCC R610 C582 R605 RB751V_40 C794

B 1
1

1
1

R546 3 4 /* 0.47U
ICH6_PWROK <8,17>

2
10KOhm /*

2
2

100KOhm 4

100KOhm 6
GND <48> VSUS_OFF# VSUS_OFF# 1 2 +3VALWAYS
3 U41B R333 R2.0-S05

E
2
C
D
7

1MOhm Q68 R611 PMBS3906 +5VLCM


2

10KOhm Q122
VR_PWRGD_DLY 1
<51> VR_PWRGD_DLY
1

G +3VALWAYS

10
3

5
S

1
2N7002 2

RN55B
U60B R606

RN55C
1

12 9 1 2 R618

PR
D Q VSUS_ON# <45>
C367
0.22UF +3VSUS PWR_ON 11 8 10KOhm
2

CK Q# 10KOhm

2
2
3 7 14 C589 /*
D

CLR
GND VCC
2

Q121
R337 1000PF D54

1
+3VS SW_SW# 1 SN74LVC74APWR 1
<6,48> OTP_RESET#

13
10KOhm G 3 VSUS_OFF#
S
2N7002 2 2
<51> SHUT_DOWN#
1
2

PM_SUSB <40,42> +3VALWAYS


R352 RB717F

2
D29 100KOhm 3
14

D 8 100KOhm 7
1 Q69 74LVC14APW_T RN55D /* R617
1

3 VCC +3VALWAYS 470KOhm


<4,17,21,29,32,37,40,48,52> PM_SUSB#
2 1 5 6 CPU_VRON <44,46>
If use another power

1
G +3VSUS
S switch method.D30
2

DAN202K 2N7002 2 GND 3


D

2
C363 U41C Q120
unmount.
7

2
R349
1

1000PF R331 1
/* 100KOhm <53> ACIN#
U41E 1MOhm Q67 G
14

14

S
U41D D30 2N7002 2N7002 2

1
VCC VCC RB751V_40 R853 +3V

1
PWR_ON# SW_SW# SUSC#_FALL_Q 2 0Ohm SUSC#_FALL

2 S
8 9 10 11 1 2 1

D
B <17> PM_PWRBTN# PWR_SW# <40> B

3
1
GND 74LVC14APW_T GND 74LVC14APW_T R854

2
C360 PM_SUSC 2 0Ohm 2 /*

1
R2.0-S01 1 1
7

0.22UF C361 R609 R855


2
S 2

Q66 /* +3VSUS 1MOhm 3 Q175


D

<35> 5V/THERM# 0.1UF D

2
100KOhm
3

/* Q123 3 2N7002
2N7002 R2.0-S01 R856 D
/* /*
G

1
/*
1

2 0Ohm 1 2 1 SUSC#_FALL 1
1

P/R need to /* G 1
+3VS unmount for J2
R2.0-S05 D52 2 S G Q176
1

ATS power S 2 3
RB751V_40 2N7002 D 2N7002
1MM_OPEN_5MIL LID_ICH#_3A <17,20>
2

test in /* 3 /*
/* D

1
+5V factory. Q125 C590
2

1 PM_SUSC#
R1.1-S24

2
PM_SUSC# 1 4.7UF/6.3V G

2
+3VSUS +3VALWAYS S 2
/* R362 G /* R2.0-S05
S
0Ohm 2N7002 2
U41F 3 /*
14

14

D
U38A Q58 R363

1
VCC 1 VCC 1 2
2N7002 LID_ICH#_3 <27>
2

PM_SUSC# 13 12 PM_SUSC 3 1
<17,52> PM_SUSC# PM_SUSC <42>

1
1 2 2 G R350 0Ohm
GND +3V GND 2 S
R316 10KOhm 74ACT08DR
7

74LVC14APW_T 1MOhm D31


1

RB751V_40
<27> KBCRSM 74HC74 TRUTH TABLE

2
LID_SW# <15,40>
1

C345 PRE# CLR# CLK D Q Q'


0.1UF 1
2

3 C362 L H X X H L
D
Q70
2

0.1UF
PM_SUSC# 1 2N7002 H L X X L H
G
2 S
L L X X float float
A At boot, KBCRSM need to be set low H H T H H L A
for normal operation
H H T L L H
H H L X Qo Qo'

Title : POWER-ON SEQUENCE


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 43 of 57
5 4 3 2 1
A B C D E

+5VO

VR_VID0 1 2
R163 47KOhm
VR_VID1 1 /* 2
R164 47KOhm
VR_VID2 1 /* 2 VID 0 1 2 3 4 5
R165 47KOhm
VR_VID3 1 /* 2 1.308V 1 0 0 1 1 0
1 R167 47KOhm 1
VR_VID4 1 /* 2 0.956V 1 1 1 1 0 1 AC_BAT_SYS
R168 47KOhm
VR_VID5 1 /* 2 AC_BAT_SYS
R171 47KOhm
/*
/* /* /* /* /* /* 05/02/23

C0805
0Ohm

0Ohm

0Ohm

0Ohm

0Ohm

0Ohm
TPC32t

1
T105 STPCPU# + +

5.6UF/25V

5.6UF/25V
1
05/06/01

1
R178

R179

R180

R166

R169

R170

C455
TPC32t C177

C173

C176 1U
T89 1 DPRSLPVR
1

5
6
7
8
TPC32t +5VO 1000PF

2
T78 PSI# R230 10Ohm Q20

D
1
2 1 +5VO
SI4392DY

G
05/06/01

S
1

1
GND C254 C210

4
3
2
1
GND

2
4.7u 4.7u
GND
GND R867

TPC32t

TPC32t
1 2

T44

T261
+VCORE
2 2.2Ohm T76 T244 T249 2
R186 100KOhm TPC32t TPC32t TPC32t
1 2 L77 R463
+3VS

1
1 2 1 2
T102
T101

T94

T98

T91

T93

T114

T104

T75
TPC32t
TPC32t

TPC32t

TPC32t

TPC32t

TPC32t

TPC32t

TPC32t

TPC32t
R188 100KOhm
U25 0.56UH 3mOhm
+3VS 1 2

2
12 VCC VDD 36
05/06/01

5
6
7
8

1
C222 + +
D
R181 0.1UF C468 C477
42
05/06/01
1
1

1
V+

2
1 2 MCH_OK 22 Q22
<8,48> VCC_MCH_VRPWRGD SYSOK

SOP8
CLK_PWR_GD# 24 32 1 2 4G SI4336DY_T1_E3 D34 470UF/2.5V 470UF/2.5V
<21> CLK_PWR_GD#

2
CLKEN# BSTM
<21,48> VRM_PWRGD 1 0Ohm 2 DELAY_VR_PWRGD_O 23 IMVPOK
R177 2.7Ohm S EC31QS04 /*

TPC32t

TPC32t

TPC32t

TPC32t

TPC32t
R176 0Ohm 34 2
<51> VR_PWRGD

1
2
3
DHM

T319

T31

T40

T304

T262
r0402 VR_VID0 30 3
<4> VR_VID0

1
VR_VID1 D0
<4> VR_VID1 29 D1 LXM 33 1

1
VR_VID2 28 RB717F D13 C183
<4> VR_VID2 D2
VR_VID3
<4> VR_VID3 27 35
05/06/01

1
VR_VID4 D3 DLM 1000PF
<4> VR_VID4 26 GND

2
VR_VID5 D4 /*
<4> VR_VID5 25 D5 PGND 37 GND
13 CMP
GND1
6 S0 GND2 49 GND
7 S1 CMN 46
8 45 T55 T52 T260 T86
S2 CMP TPC32t TPC32t TPC32t TPC32t
3 OAIN+ 20 1 2 3
3 19 R182 511Ohm

1
B0 OAIN- AC_BAT_SYS
4 B1 1 2
R191 511Ohm
GND 5 B2 FB 18
05/02/23

C0805
DPRSLPVR
<17> PM_DPRSLPVR 1 2 43 SUS NEG 16
05/06/01

CSP
1MOhm
R209 0Ohm r0402 STPCPU# 44 DPSLP#

1
PSI# + +

5.6UF/25V

5.6UF/25V
<17,21> STP_CPU# 1 2 21 PSI#

1
1U
C534

C527
R212 0Ohm r0402 17 C513
CCI

5
6
7
8
R187 100KOhm VRON 9 SHDN# Q93 1000PF

D
+5VO 1 2 15

2
POS
2

R206

C521
2 1 2

1
R199 1 /* TON SI4392DY
2 1KOhm

G
05/06/01

S
<4> PM_PSI#
R221 14 48 C234 470PF
1MOhm CCV CSP

4
3
2
1
10 47 R868 T80 T59 T84
1

REF CSN
47P

1 2 TPC32t GND TPC32t TPC32t


1

1
0.47U

R224 100KOhm R226 C235 L79 R467

1
2 1 GND 100KOhm 11 41 1 2 1 2 2.2Ohm 1 2 1 2 +VCORE
+5VO ILIM BSTS
1
C245

/* R219 1% R205 2.7Ohm


2

/*
0.1UF 0.56UH 3mOhm (27A)
<43,46> CPU_VRON 1 2 DHS 39
05/06/01
C258
2

2
1

5
6
7
8
100KOhm TIME

330UF/2V
1 TIME LXS 40

1
D
TPC32t C252 +
4
05/06/01 4
1

TPC32t C487
T95 1 0.01uF/25V 31 38 Q94 C488
2

DD0# DLS

SOP8
75KOhm

C253 4G SI4336DY_T1_E3 D16 0.1UF/25V

2
R231

100P S EC31QS04
2

TPC32t

TPC32t

TPC32t
MAX1987ETM

1
2
3

T50

T215

T240

T288

T290

TPC32t
R192 360Ohm R183 1KOhm
2

1
1 2 1 2 1000PF

1
GND 1% /* C514
R208 R211 R204 1% C238 R190 1KOhm
05/06/01

1
1 2 1 2 1 2 1 2 1 2

2
4.7KOhm GND
GND 100KOhm 1.21KOhm 4700P GND
05/06/01
R215 1%
U26 +5VO 2 1 TIME
6

R213 1 NC VCC 5 15KOhm


DPRSLPVR 1 2 2 A
3 GND Y 4 2 Q28A
0Ohm UM6K1N
1

5 U27 NC7ST04M5 1 2 5
R214 36.5KOhm
3

R237 1 NC VCC 5
1

CLK_PWR_GD# 1 2 2 A

0Ohm
3 GND Y 4 5 Q28B
UM6K1N
R218
121KOhm
Title : Z61Ae
4

ASUSTECH CO.,LTD. Engineer: ADAMS LIN


GND NC7ST04M5
2

GND GND Size Project Name Rev


for C4 fast exit event Custom Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 44 of 57
A B C D E
A B C D E

SIGNAL IN: VSUS_ON#

POWER IN: AC_BAT_SYS

OUT: +3VO
05/02/23 AC_BAT_SYS +5VO

1
1 1 2 AC_BAT_SYS 1
C636 C653

1
1000PF 1UF R670 10Ohm + +

5.6UF/25V

5.6UF/25V
2

C584

C585
C586
0.1UF/25V

2
GND

2
GND

5
6
7
8
Q119

D
3V_5V_PRWGD
SI4800BDY
(7A,OCP=8.4A)

S
RUN_5VO
1
+5VO 3728_INTVCC L87 T328 T202 T332

4
3
2
1

3
C641 T317 +5VO TPC32t TPC32t TPC32t
4700P TPC32t R650

3
2

1
1 2 1 2

1
1 2

100KOhm R632
05/06/01 GND
2

2
107KOhm

180PF/50V

4.8UH 7mOhm

5
6
7
8

2
100KOhm

U62 Q124
1

1
R633

D51 C642

32
31
30
29
28
27
26
25

D
/*
1

1
+ + 1UF/10V

100UF/6.3V

100UF/6.3V
SI4894DY-TI
2 LTC3728LX 2

FS1J4TP
2

CE26

CE27
G
NC_3

SENSE1+

RUN/SS1

TG1
SW1
SENSE1-

NC

PGOOD

S
1

2
R645

C648
2

1
C634

T43 T17 T187 T118


2

4
3
2
1

2
0.1UF/25V TPC32t TPC32t TPC32t TPC32t
1 24

1
VOSENSE1 BOOST1
2 PLLFLTR VIN 23 GND
1

20KOhm

3 22 378_INTVCC D59 GND


PLLIN BG1 +5VO
4
5
FCB
ITH1
EXTVCC
INTVCC
21
20 3728_INTVCC 3
1
05/06/01
6 SGND PGND 19 2
7 18 C647 0.1UF/25V
2

3.3VOUT BG2
R644

RB717F
8 17 1 2
05/02/23
VOSENSE2

ITH2 SENSE2+ BOOST2 T335


RUN/SS2
SENSE2-

TPC32t AC_BAT_SYS
NC_1

NC_2
33 SW2

1
TG2
SIDE1

1
C655
C630 1000PF

1
+ C651

5.6UF/25V
4.7u
9
10
11
12
13
14
15
16

2
C631 1000PF

C649
05/06/01 GND GND 1U

2
1

RUN_3VO

2
220P

0Ohm
2

3 3
1

1
220P C632

0Ohm R640

Q143
GND
1

/*

1 D1_1 G1 8
1

1
C625

C643 2 7
2

D1_2 S1/D2_3
R641
150KOhm

150KOhm

C638
1

5600P 1000PF 3 6
2

G2 S1/D2_2
(5A)
4 5 T334 T192 T326 T323 T327 T318
S2 S1/D2_1
C635 180PF/50V TPC32t +3VO TPC32t TPC32t TPC32t TPC32t TPC32t
R642

R636

2 1 SI4914DY L88 R627


2

1
1 2 1 2
R643 R655
1 2 1 2 +3VO 4.7UH 10mOhm
GND
GND 20KOhm 64.9KOhm DCR=13m ohm

1
+

1
CE25
Vref = 0.8 V 150UF/4V C613
1UF/10V

2
T18 T12 T13
TPC32t TPC32t TPC32t
4
VPLLFLTR=1.2V 400K 4

1
VPLLFLTR=0V 260K
VPLLFLTR>=2.4V 550K +3VALWAYS GND

D57 05/06/01
1

2 RUN_3VO
3
R669 1 RUN_5VO
100KOhm
RB715F
2

3
D
+3VO Q144
1
<43> VSUS_ON# 2N7002
G
2 S
1

GND
R660
100KOhm
2

5 3V_5V_PRWGD 5
<48> 3V_5V_PWRGD

Title : Z61Ae
ASUSTECH CO.,LTD. Engineer: ADAMS LIN
Size Project Name Rev
Custom Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 45 of 57
A B C D E
A B C D E

SIGNAL IN: SUSB#_PWR


SUSC#_PWR
CPU_VRON

POWER IN: AC_BAT_SYS


VREF5 +5VO
T170 05/02/23 OUT: +1.8V
TPC32t ON_1.8 TPC32t AC_BAT_SYS +1.5V
T183 +2.5V

1
1

100KOhm
+VCC_GMCH_CORE

C301 5.6UF/25V

C306 5.6UF/25V
1 1

1
R302
+ + +5VALWAYS

1
SUSC#_PWR +3VALWAYS
C331

2
2

5
6
7
8
0Ohm R294
Q44A JP7 SHORT_PIN
2005 2 1

1
UM6K1N Q42 +1.8VGND

D
1 2
2 C325 +1.5VO 05 31 +1.8VO 0.1UF/25V SI4800BDY
GND TPC32t
2700P T45

S
1

2
3
1 +1.8VO(7A) T286 T282 T287
TPC32t TPC32t TPC32t +1.8V

4
3
2
1

1
JP14

1
5 Q44B L84

1
C315 C326 1 2 +1.8VO 1 2
4
1 2
1

2
C330 UM6K1N 3300P

2
3300pF/50V

5
6
7
8
R293 1.8UH 3MM_OPEN_5MIL

1
0.01uF/25V 8.06K Q41 10UF/6.3V

150UF/2V

150UF/2V
+ +

D
2

CE21

CE22
12.1KOhm
/* D19 T96 T155 T67 (5.6A)
2005 SI4894DY-TI

2
R297
R292 R300 TPC32t TPC32t TPC32t C553

G
GND

S
1

2
FS1J4TP

1
05 31 1 2 D20

2
330Ohm R296

4
3
2
1

1
SUSC#_PWR 12.7KOhm 1SS355
<40,52> SUSC#_PWR GND GND

2
330Ohm

1
R298
2 1

2
2 2 1 +1.8VGND AC_BAT_SYS 2
C332 0.1UF/25V
VREF5 10KOhm R304 /* AC_BAT_SYS
1 2 T306
ON_1.5
100KOhm

R303 2.7Ohm
+12VS

0.01uF/25V
TPC32t
1 2
05/02/23
1

1
10.2KOhm

1
VREF5
R305

R299 10.7KOhm

5.6UF/25V
Q126

C321 0.1UF/25V
GND 2 1

1
C333 0.1UF/25V +
4700PF/50V /* 1 8 TPC32tTPC32t (4A) TPC32t+1.5VS
2

2
2

1
D1_1 G1
Q45A +1.8VGND T297 T299 +1.5VO T36

1
C328
R301 UM6K1N C327 +1.5VGND
2005 2 7

2
JP16
1

D1_2 S1/D2_3

C607
27KOhm 2 C324 L86

1
1
C322 C319 05 31 0.1UF 3 6 1 2 +1.5VO
1 2
1

2
1 2
3

G2 S1/D2_2
D21

48
47
46
45
44
43
42
41
40
39
38
37
1

2200P 5600P

2
Q45B U33 1 2 4 5 3.7UH 3MM_OPEN_5MIL

2
S2 S1/D2_1
5 R295 GND

FLT
INV1

LH1

OUTGND1
TRIP1

TRIP2
OUT1_U
LL1
OUT1_D

VIN_SENSE12

OUTGND2
OUT2_D

1
UM6K1N 1.5KOhm 1SS355 SI4914DY +
4
2

1
10KOhm

VREF5 T16 CE24


R722

R291 JP18 TPC32t 150UF/2V

1
2

1 36 +1.5VGND 1 2

2
R290 1.8KOhm ON_1.8 FB1 LL2
2 SS_STBY1 OUT2_U 35 GND
3 34 SHORT_PIN GND
1

0Ohm INV2 LH2


3 /* 4 FB2 VIN 33 +5VO 3
ON_1.5 5 32 VREF3
1

D17 1SS355 SS_STBY2 VREF3.3 VREF5


GND 6 PWM_SEL VREF5 31
2 /* 1 7 30
CT REG5V_IN
8 GND LDO_IN 29 2 1 C309 0.1UF /* R278 20mOhm
2

47pF/50V

R283 9 28 1 2
REF LDO_CUR +3VO
1

R288 1 2 10 27
STBY_VREF5 LDO_GATE
1

ON_2.5 1 100KOhm2
C308 0.1UF

<47,52> SUSB#_PWR 1 2 0Ohm 11 STBY_VREF3.3 LDO_OUT 26

VIN_SENSE3
R281 12 25

PG_DELAY
2

STBY_LDO INV_LDO
SS_STBY3

OUTGND3
R274 0Ohm 100KOhm

4.7uF/25V

4.7uF/25V
1

2
1

1
OUT3_U

OUT3_D
C310

PGOUT

TRIP3
C298
INV3

5
6
7
8
LH3
FB3

LL3
GND
2

2
0.027U Q40

D
/* AC_BAT_SYS ON_2.5
GND GND GND
13
14
15
16
17
18
19
20
21
22
23
24
SI4800BDY

C311

C314

S
+1.05VGND C305 /*
<48> 1.8_2.5_1.5_1_PWRGD
TPS5130 2 1

4
3
2
1
VREF5 ON_1.05 +2.5VO
D18
R272

ON_1.05 0.1UF T165 T167


1

2 1 TPC32t TPC32t
JP6
1

2
100KOhm

R282 R280 (1A)


<43,44> CPU_VRON

1
R279 C299 1 2 1 2 +2.5VO 1 2
1 2 +2.5VS
R269

100KOhm

4 2 1 1SS355 4
2

6
0Ohm R271

1.8KOhm 10KOhm 19.6KOhm 1MM_OPEN_5MIL


C297 /* 0.1UF/25V

GND
2
1

1
R276

T298 C288
0.1UF/25V 05/02/23
2

1
2 C290 TPC32t AC_BAT_SYS 10UF/6.3V
1
0.01uF/25V

0.1UF/25V
1

2
2200P
3

12.7KOhm

Q39B Q39A +3VO C295 C286


1

2
UM6K1N GND GND
2

0.1UF

5
6
7
8
C300

UM6K1N

5.6UF/25V

5.6UF/25V
5 2005
2

Q118

D
GND
4
1

1
C721 05 31 SI4800BDY + +

S
0.01uF/25V
2

T285 T281 +1.05VO

4
3
2
1

2
C588

C597
GND TPC32t TPC32t
L83

1
T182 1 2 +1.05VO
2

TPC32t +5VALWAYS T186 R273 1.8UH (7A)

5
6
7
8

D48
R275
JP8 680Ohm
1

1
49.9KOhm +

D
TPC32t
1

1 2 R277 T241 T231 CE23


VREF5
1

1 2 11.8KOhm TPC32t TPC32t


G

FS1J4TP
1MM_OPEN_5MIL Q117 330UF/2V
T181 T144

2
1

5 GND 5
2

4
3
2
1

1
TPC32t +3VALWAYS TPC32t C293 GND
1000PF SI4894DY-TI JP17
2

JP9 +1.05VGND 1 2
Title :
1

VREF3 1 1 2 2 +1.05VO
SHORT_PIN GND
Z61Ae
1MM_OPEN_5MIL ASUSTECH CO.,LTD. Engineer: ADAMS LIN
Size Project Name Rev
Custom Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 46 of 57
A B C D E
A B C D E

SIGNAL IN: SUSB#_PWR


CPU_VRON

POWER IN: +3VSUS


+3V
+3VS +1.8V
1 1

OUT: +0.9VS
+1.5VSUS

1
+VCCP
R836 TPC32t +VCC_GMCH_CORE
T4 TPC32t +2.5VS_CRTDAC
0Ohm T8
/*
Vref=1.215V
TPC32t

1
T284 TPC32t

1
T283 U3
JP15
1 5

1
IN OUT

2
+1.05VO 1 2 +VCCP 2

1
1 2 CRTDAC_EN GND R16
3 EN ADJ 4
3MM_OPEN_5MIL (3A)
10.7KOhm

1
C535 SI9183DT C18
/*

1
C799 /*

1
0.1UF/25V 4.7u

2
0.1UF/25V /*

2
/*
GND
R6
2 10KOhm 2
/*
05/06/01

1
TPC32t
T289 TPC32t GND
T99
JP13
1

+1.05VO 1 2 +VCC_GMCH_CORE

1
1 2
3MM_OPEN_5MIL
1

C524 (3A)

0.1UF/25V T6
2

TPC32t T278
+1.8V TPC32t +1.8V

1
GND +0.9VS

R40
+3V

2MM_OPEN_5MIL

2MM_OPEN_5MIL
T15

100KOhm
1

1
TPC32t

2
JP2

JP4
+3V

2
3 3

1
2

2
T25 R42
TPC32t 100KOhm
U11

R39
1

1
1 6

2
VIN VCNTL2

3
T11 2 5 Q5B
TPC32t GND VOUT UM6K1N
3 VCNTL1 REFEN 4
5

1
RT9173ACL5

4
100KOhm
+0.9VO

6
Q5A
UM6K1N R48

1
+ T316 2 2 1 SUSB#_PWR

1
CE3 C71 TPC32t C57

1
1
100U/2.5V 10UF/6.3V 10UF/6.3V 0Ohm

2
GND

+3VS <46,52> SUSB#_PWR

4 4

+0.9VO

2
R62 R61
100KOhm 100KOhm

2
R51

1
20KOhm
VTT_PWRGD <48>
1
3
D
3
C
1 B 1
G Q8
E 2 S 2N7002
2

2 Q7
R50 PMBS3904
165KOhm
1

5 5

GND

Title : Z61Ae
ASUSTECH CO.,LTD. Engineer: ADAMS LIN
Size Project Name Rev
Custom Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 47 of 57
A B C D E
A B C D E

05/02/18
+5VLCM
U34

2
R311 R313 SOT23_S5_NB
5 VCC NC 1

1
SUB 2 T198 T190
T179 T280 T204 T296 T85 T207 C336 4 3
47KOhm 10KOhm VOUT GND
TPC32tTPC32t

2
1UF
TPC32tTPC32tTPC32tTPC32tTPC32tTPC32t 120104 GND GND

1
1 PST9142 1

1
R315 62KOhm U35 R314 62KOhm

1
<49> BAT2_SW1 1 2 1 RA2 RA1 20 1 2 BAT1_SW1 <49>
<49> BAT2_SW2 2 RA3 RA0 19 T216 T81 T294 T178 BAT1_SW2 <49>
3 T0CKL OSC1/CLKIN 18
4 17 TPC32t TPC32t TPC32t TPC32t
MCLR#/Vpp OSC2/CLKOUT
5 Vss1 Vdd2 16
6 15

1
Vss2 Vdd1
<50,51> AC_APR_UC 7 RB0 RB7 14 BAT1_LLOW# <17,51>
<49,53> TS1# 8 RB1 RB6 13 BAT2_LLOW# <18,51>
<49,51,53> TS2# 9 RB2 RB5 12 CTRL <50>
<50> EOC 10 RB3 RB4 11 CHG_EN# <40,50> CHG_EN#
TPC32t D23 LOW: CHARGER ENABLE
PIC16C54C_04/SS T189 R312 T188 CHG_FULL_OC <27>
2

2
GND 1 2 T214

1
D24 D37 TPC32t TPC32t RST_BTN# <43>
1MOhm 1SS355
V0402MHS03 V0402MHS03

1
X3
1

1
1 3
GND C339

2
4MHZ 1UF
2 2
GND GND
GND

Charge/Discharge Pins logic table


TPC32t
T185
BAT1_SW1 BAT1_SW2 BAT2_SW1 BAT2_SW2 CTRL
1

Adapter mode L H L H H
+5VALWAYS
+3VS
95 DEGREE C BAT1 charge L H L H H
2

R240 THERMAL PROTECTION BAT2 charge L H L H L


23.2KOhm
/* PLACE UNDER CPU BAT1 Discharge H H L L H
TPC32t
1

1
T107 RT1 C637 BAT2 Discharge L L H H L
1 1 2 2
T30 0.1UF

14
3 1 3
1

2
100KOhm GND TPC32t U64A
1 VCC GND
<47> VTT_PWRGD
3
C266 /* +5VALWAYS 2
GND

14
2 1
T37 LV08A U64B

14
1

7
1

TPC32t 4 VCC U64C


0.01uF/25V
TPC32t 6 9 VCC
/*
U28 T108 R248 5 8 POWERGD
100KOhm T338 GND

14
1 NC VCC 5 1 10
2 /* TPC32t U64D LV08A GND
1

7
SUB VCC LV08A
3 4 OTP_RESET# <6,43> <45> 3V_5V_PWRGD 12

7
GND VOUT
11
PST9013 13 GND
<46> 1.8_2.5_1.5_1_PWRGD GND
GND /*
1 LV08A T113 1

7
T175 TPC32t
+VCC_GMCH_CORE +3VS +3VS TPC32t
<21,44> VRM_PWRGD
1

R263
100KOhm
4 4
2

R261
VCC_MCH_VRPWRGD <8,44>
2

100KOhm 3 <4,17,21,29,32,37,40,43,52> PM_SUSB#


R264 D
Q36
1

10KOhm 3 Q37

2
C 1
1

1 B G 2N7002 D58 R663


2 S 1SS355
1MOhm VSUS_OFF# <43>
2

E
R265 2 Q145A

1
1

6
PMBS3904 UM6K1N
C287 30KOhm
TPC32t Q145B 2
2

0.22U T337 UM6K1N

1
3

1
1
POWERGD 5 C654

2
1UF
GND
GND
5 5

Title : Z61Ae
ASUSTECH CO.,LTD. Engineer: ADAMS LIN
Size Project Name Rev
Custom Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 48 of 57
A B C D E
5 4 3 2 1

AC_BAT_SYS
BAT1 Q51 BAT2 Q26 Q23
Q52 S D D S S D
1 8 8 1 1 8
BAT1 8 D S 1 2 7 AC_BAT_SYS BAT2 7 2 2 7 AC_BAT_SYS
7 2 3 6 6 3 3 6

1
100KOhm R310

100KOhm R309

100KOhmR185

15UF/25V

15UF/25V
100KOhmR200
6 3 4 G 5 5 G 4 4 G 5

2
+ C483 + C473

7343

7343
5750

5750
5 G 4
TPC8107 TPC8107
D TPC8107 D

2
TPC8107
GND

1
<48> BAT2_SW1

220KOhm R308
R189

2
<48> BAT1_SW2 Q46 3 3 1 2
TS2# <48,51,53> D
3 C Q91 3
D 1 R-1 B Q24 220KOhm R-1 C

Q47
1 B

PDTC144EK
3 1 2 1
47K D <48> BAT2_SW2
1 E G
<48> BAT1_SW1

1
G D22 R-2 Q48 2 S 47K
E
2 S

2
100KOhm R307

2N7002
2 1 47K 1 2N7002 1SS355 R-2

2
G 2N7002 R175 D15 47K
PDTC144EK 2 2 S
1SS355 R306 100KOhm R198 2
1 2 1 2

1
1
75KOhm 75KOhm
/* /* GND

D14
1
3 AD_IN_DS# <51>
2

RB715F

1
C C

T71

TPC32t
C270

C269

T213T209T208T205
GND T265T119T112T266
2

2
TPC32t
TPC32t
TPC32t
TPC32t GND
TPC32t
TPC32t TPC32t
TPC32t C341 0.1UF
0.1UF

0.1UF
1

1
BAT1_S
1

CON Part Number Modify as M3N BAT2_S


L57
L80 CON Part Number Modify as M3N 1 2 BAT1_S <51,53>
1 2 CON19
BAT2_S <51,53>
120Ohm/100Mhz
B L52 150Ohm/100Mhz B
BATT_CON_6P T97 120Ohm/100Mhz 1 T212
L44 150Ohm/100Mhz 1
2 2 1 2 BAT1
6 TPC32t 1 2 3 TPC32t L56
BAT2 3
5 L41 4 L55 1 2
4 BATSEL_2P# <17,50>
4 1 2 SMCLK_BAT2 <27> 5 1 2 SMCLK_BAT1 <27>
1

1
T92 TPC32t 5
3 6 120Ohm/100Mhz
L40 6 TPC32t T211
2 120Ohm/100Mhz 7 T210 120Ohm/100Mhz
1
7 L54
T88 1 2 SMDATA_BAT2 <27> 8
1

8 TPC32t
1 1 2 SMDATA_BAT1 <27>
TPC32t 120Ohm/100Mhz BATT_CON_8P
CON17 L39 T39 T292 T309 L53
120Ohm/100Mhz

1
1 2 TS2# 1 2 TS1# <48,53>
1

TPC32t TPC32t TPC32t


120Ohm/100Mhz 120Ohm/100Mhz

1
1

GND

T259T239T217T291 GND
1

1
C251 C256 C242
TPC32t
TPC32t
TPC32t
TPC32t C342 C343 C344
2

100PF 100PF 100PF

2
100PF 100PF 100PF
GND
GND

A A

Title : Z61Ae
ASUSTECH CO.,LTD. Engineer: ADAMS LIN
Size Project Name Rev
Custom Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 49 of 57
5 4 3 2 1
A B C D E

A/D_VIN
A/D_VIN_O
A/D_DOCK_IN

C580 0.1UF/25V

C583 0.1UF/25V
1

1
T66

2
GND GND
TPC32t

<53> MAX1909_PDS
N41437175 05/02/23 AC_BAT_SYS

1
1 1

1
+ +
C614 C610
5.6UF/25V 5.6UF/25V T77 T169

4
3
2
1
A/D_VIN_O

C592 0.1UF/25V
/*

2
A/D_DOCK_IN Q130 TPC32tTPC32t

S
G
SI4835BDY

1
MAX1909_LDO

1
D
CHG_GND CHG_GND

5
6
7
8
2
R602 GND
LDO : 5.4V D49

29
28
27
26
25
24
23
22
33Ohm
2

1SS400 MAX1909_LDO U58

2
100KOhm

REF : 4.2235V

PDS
CSSP

DHI
DHIV
GND2
PDL

CSSN
SRC

1
R597

C594 0.1UF/25V T311 T129 T128


1 21 1 2 TPC32t TPC32tTPC32t
DCIN DLOV
2 20
1

LDO DLO L89 R667


3 19

1
1909_REF ACIN PGND BAT_CHG
4 REF CSIP 18 1 2 1 2 BAT_CHG
2 5 PKPRES# CSIN 17 2
10UH 15mOhm
05/02/18 6 ACOK BATT 16

VCTL
7 15

ICTL

CCV
CCS
CLS
IINP
MODE GND1
2

5
6
7
8
CCI
1U

1U

1U
2

1
R587

R601
26.7KOhm

Q128

D
MAX1909 D53 + C650

7343
5750
8
9
10
11
12
13
14
SI4800BDY
R594

15UF/25V

G
EC31QS04

S
2

2
C568

C571

C572
19.6KOhm

GND
1

2
2

2
53.6KOhm
1

4
3
2
1

1
20KOhm

100KOhm

IINP
R593

GND TPC32t GND GND GND


R583

TPC32t T177

2
TPC32t T300 CHG_GND
1

10KOhm
AC_IN Threshold 2.089Vmax T301 R598 R710
1
A/D_DOCK_IN > 18.158V 1 2
1

active
1

1
C591

C599
9.31KOhm

0.01uF/25V
GND

1
T176 Q110
3
D 2N7002 T325

CHG_CCV
T90

0.047U
2

2
2

2
14.7KOhm

0.1UF/25V
TPC32t TPC32t BAT2TPC32t
R581
137KOhm

10KOhm
39.2KOhm

BAT1
R596

R600

1
1

1
2

1
G

1
3
2 S 3
1

1
C596
BAT_CHG

0.1UF/16V
2
BAT_CHG

R584

C577
GND H=4S1P(1.25A) GND GND Q109
L=4S2P(2.5A) 3
D 2N7002

SI4925DY Q135

Q29
5

8
D2

D2

D1

D1
GND

D2

D2

D1

D1
<17,49> BATSEL_2P# 1
<40,48> CHG_EN#

P
G

P
S

SI4925DY
2 GND

P
P
G2

G1
S2

S1
100KOhm R624
122704 05/02/18

G2

G1
S2

S1
100KOhm R220
+5VLCM
<48,51> AC_APR_UC

1
2

1
100KOhm

R561 Q111 +5VLCM

2
47KOhm IRLML2402
R585
R586

R210
MAX1909_LDO
2 S
D
1

3 200KOhm
3

D
GND 100KOhm
G

1
Q112 R638
1

<48> CTRL 1 3
100KOhm D
<27> BAT_LEARN 2N7002

Q27
G 3 3
S D D

Q25
2 GND
Q129 1
4 CTRL 1 G 1 CTRL 4
S 2

1
2N7002

2N7002
Adapter Iin(max) = [0.075V/Rsense(ADin)]*[VCLS/VREF] G G
2 S S 2

2N7002
Rsense(ADin)=0.02 ohm C249
VCLS= 3.685V C618 0.1UF/25V

2
=> Iin(max)=3.39A 0.1UF/25V

2
=> Constant Power = 19 * 3.42 = 64.4W GND
GND
Charge Current Ichg = [0.075V/Rsen(CHG)]*[VICTL/3.6V]
Rsense(CHG)=0.015 ohm
VICTL= 1.8Vor 0.9 8 4 CTRL=H CHARGE BAT1
V+ V-
100KOhm

100KOhm

=> Ichg = 2.5A or 1.25A +5VCHG GND


CTRL=L CHARGE BAT2
1

Vbatt = Cell * { Vref +[ (VCTL- 1.8V) / 9.52 ] }


0.01uF/25V

6 IINP
VCTL= 1.576V -B input current mointer output R573
7 OUTB  筿砏玥: 1.ㄢ聋筿     ,Adapter IN
C542

=> Cell = 4.2V 5 1 2 1909_REF


2

+B  癸材 聋筿  筿,  材 聋筿 
Mode pin : Vmode > 2.8V (trie to LDO pin) ----> 4 Cells GND 10KOhm 2.材 聋筿 ┪琌材 聋筿   ,Adapter IN
2.0 > Vmode > 1.6V (floating) ----> 3 Cells 2 CHG_CCV Detect   聋筿   ,碞癸  聋筿  筿,   埂 ゎ
U55 -A
R542

3.璝 聋筿   埂,  础   聋筿 ,玥  础
R547

0.8 > Vmode (trie to GND) ----> Learning mode 1 voltage regulation loop compensation R572
T206 A OUTA 1909_REF   筿 , 埂    ㄓ  埂 ê聋筿 
5 VCC 1 +A 3 1 2
2

4.璝 聋筿 タ  筿,  础   聋筿 
10KOhm

10KOhm

0.764V(300mA)
TPC32t
VICTL< 0.8V or DCIN < 7V -->Charger Disable B 2 45.3KOhm 玥     筿筿 , 埂 , 癸础  筿  筿
2

U56 LMV393
1

5 <48> EOC 4 GND 3 5


Pre_CHG_V = 3.1mV Y
1
R562

R554

Pre_CHG_I = 300mA
NC7SZ08M5
Title : Z61Ae
1

GND
GND GND
ASUSTECH CO.,LTD. Engineer: ADAMS LIN
Size Project Name Rev
Custom Z61Ae 2.0

Date: Thursday, June 09, 2005 Sheet 50 of 57


A B C D E
5 4 3 2 1

SHUT_DOWN#_DS
+5VLCM BATLL1_DS#
BATLL2_DS#
BAT_LOW#_DS

1
C529 BAT_LLOW#_OC <17>
T173

100KOhm R545
2
0.1UF TPC32t
/* 1

1
GND 3 D43 D42 D45 D44
D
/*
Q115 1SS355 1SS355 1SS355 1SS355
T174
1

2
D G 2N7002 D
TPC32t
D47 Q113 3 2 S /*
1 R-1 C

1
31 B
2 47K AD_IN_DS# <49>
E
F02JK2E R-2
/* 47K
T171
3
D
DTC144EK 2 TPC32t
T295 /* Q98
1 TPC32t 1
<48,50> AC_APR_UC

1
G 2N7002
2 S

GND

GND

+5VLCM
+5VLCM
R544
+5VLCM 1 2 BAT1_LLOW# <17,48>
C C
R541 4.7KOhm
100KOhm BAT1_LLOW# H -> L =13.425V

2
T134

R661
100KOhm
L -> H =14.1V

2
R539

BAT2_S T160 TPC32t

100KOhm
3 R662
D 122704
R530

TPC32t
1

1
BAT_LOW#_LED <40>
2

Q116
2

2
100KOhm

BATLL1_DS# 1

1
2N7002
4.7KOhm

R534 G
S
2 GND
T41 T320
634KOhm 3
D
1

1 TPC32t 3
<18,48> BAT2_LLOW# VR_PWRGD_DLY <43> TPC32t D
1

D56 Q140
1
TPC32tT156 U53
<53> BAT2_LOW# 1 Q137 BAT_LOW#_DS

1
1 14 3 1 G 2N7002
BATLL2_DS# 2
OUTPUT2 OUTPUT3
13 2 G 2N7002 2 S
<53> BAT1_LOW#
1

OUTPUT1 OUTPUT4 2 S

1
3 V+ GND 12

2
+2.5VREF R532 4 11 DAN202K
INPUT1- INPUT4+ VR_PWRGD <44>
1 2 5 10 R630
3 INPUT1+ INPUT4- T203
D 6 INPUT2- INPUT3+ 9 1MOhm
Q114 4.7KOhm 7 8
INPUT2+ INPUT3- TPC32t
2

2
R540 196KOhm
2N7002

1
100KOhm

1 LM339MX GND
C526

G
2 S
1
R531

BAT2_LLOW# H -> L =10.112V R526 GND


1

1 2 AC_BAT_SYS
0.1UF
2

B B
L -> H =11.04V
150KOhm
2

R515

100KOhm R516
R517 AC_BAT_SYS +5VLCM

2
BAT1_S 4.7KOhm T293
GND +5VLCM BAT1 & BAT2 in , shut_down# = 9.5V

47KOhm
TPC32t
1

+2.5VREF BAT1 only , shut_down# = 11.657V


2

1
R525
SHUT_DOWN# <43>
2

470KOhm
649KOhm +2.5VREF

1SS355
R495

D40

R524
0.1UF
1

560KOhm
1
1

1
C504

4 5 6
2
2

E C Q103
1

2
R527
BC847BPN
2

10KOhm
C522 143KOhm
B B
E
R537
C
R496

0.1UF/25V
2

0.1UF 3 2 1
0.1UF

649KOhm
1

2
1
1

1
R528
1

SHUT_DOWN#_DS
47KOhm
C519

GND 3 R512
D
2

2
1

C520
Q95

1
1

4.7u
100KOhm

200KOhm
2N7002

R538

1
1

A <48,49,53> TS2# A
G
2

2 S
C532
2

GND

Title : Z61Ae
ASUSTECH CO.,LTD. Engineer: ADAMS LIN
Size Project Name Rev
Custom Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 51 of 57
5 4 3 2 1
A B C D E

T42
Q35 TPC32t TPC32t
+1.8VO 1 6 (0.3A) +3VO T7 +3VSUS
D JP5 JP19
2 5

1
3 S 4 1 2 1 2 (0.4A)
+1.8VS

1
G 1 2 1 2
PMN45EN 1MM_OPEN_5MIL 1MM_OPEN_5MIL
1 1

TPC32t
+5VO T200 +5VSUS
JP20
1 2 (0.01A)

1
1 2
1MM_OPEN_5MIL

AC_BAT_SYS T312
C626 TPC32t

1
2
0Ohm R518
C512 0.1UF/25V U61

1
TPC32t TPC32t 1000PF 1 2 1 5 +12VO

2
IN OUT

2
T201 T193 GND
TPC32tTPC32t T5 2 R620
Q50 /* T199 T194 TPC32t GND
1

1
SUSC#_PWR 845KOhm
+3VO 1 6 JP11
GND 3 EN NC or ADJ 4
2 2 D 5 (2A) 2

4.7u
3 S 4 1 2 MIC5235BM5
1 2 +3VS
G

1
PMN45EN C334 2MM_OPEN_5MIL

2
2

C605
TPC32t TPC32t 0.1UF/25V 05/06/01 R614

2
T110 T324 TPC32tTPC32t T3
Q142 T336 T339 TPC32t 95.3KOhm
GND
8 D S 1
1

1
+5VO JP22
7 2 (4A)

1
6 3 1 2 +3VALWAYS GND
D61 1 2 +5VS
1SS355 5 G 4
2 1 3MM_OPEN_5MIL

1
C337 0.1UF/25V C645
SI4800BDY 1 2

100KOhm R268
+12VS 2 /* 1 SUSB#_PWR_ON 0.1UF/25V

2
GND
2

GND SUSB#_PWR_ON
R612
R666 100KOhm C652
TPC32t /* SUSB#_PWR_ON 2 1 TPC32t
<41> SUSB#_PWR_ON
1

0.1UF/25V

6
T314 GND T2 Q38A

1
Q127 UM6K1N
UMC4N 27KOhm
/* (0.01A) 2
1

1
+12VS
3 +12VO +12VS R2.0-S01 3

1
T28
C

4
3

R613
TPC32t C289
47K

R621 0Ohm
1

2
0.22UF

2
B

<4,17,21,29,32,37,40,43,48> PM_SUSB# 1 2
T22
2

B
47K

10K

3
47K

100KOhm
TPC32t Q38B /*
UM6K1N
1

SUSB#_PWR
1

5
C

<46,47> SUSB#_PWR

4
GND

GND GND

TPC32t TPC32t Q49


T321 T191 TPC32tTPC32t TPC32t
T197 T196 T235
1 6
1

D JP10 +3VALWAYS
+3VO 2 5 (2A)
1

1
3 S 4 1 2
1 2 +3V
4 G 4
PMN45EN 1 C338 2MM_OPEN_5MIL

R289
0.1UF/25V
2

2
TPC32tTPC32t GND TPC32t
TPC32t TPC32t Q132 T329 T330 T10 SUSC#_PWR_ON

100KOhm
T64 T331 8 D S 1 JP21
7 2 (3.5A)
1

6
6 3 1 2 Q43A
+5V
1

1
+5VO 1 2 UM6K1N
5 G 4
3MM_OPEN_5MIL SUSC_PWR 2
<23> SUSC_PWR
1

C622 0.1UF/25V N/A C633


R2.0-S01

1
SI4800BDY 1 2
0.1UF/25V C313
2

GND

2
0.22UF
GND

3
2 1 TPC32t Q43B /*
T232 UM6K1N
SUSC#_PWR_ON R635 10KOhm (0.1A) SUSC#_PWR 5
TPC32t
1

4
T322
+12V
GND
5 R639 0Ohm 5
1

+12VO 1 2
T228
TPC32t
R287 0Ohm Title : Z61Ae
1

<17,43> PM_SUSC# 1 2
T180 ASUSTECH CO.,LTD. Engineer: ADAMS LIN
TPC32t
Size Project Name Rev
1

<40,46> SUSC#_PWR Custom Z61Ae 2.0


Date: Thursday, June 09, 2005 Sheet 52 of 57
A B C D E
A B C D E

AC_BAT_SYS A/D_DOCK_IN

T27 T223 T218 T26 T246 T247 T56 T58 T46 T250 T242 T252 T255 T163
TPC32t

1
TPC32tTPC32tTPC32tTPC32t TPC32tTPC32tTPC32tTPC32t TPC32t TPC32tTPC32tTPC32tTPC32t

1
D12 Q134 R625
Q21 <27> ACIN_OC
R153 1 R672

1
A/D_DOCK_IN S D 3 100KOhm
A/D_DOCK_IN 1 8 1 2 2 AC_BAT_SYS D 2N7002 68KOhm
2 7 3

2
1 3 6 20mOhm 1

2
1
4 5 FD6JK3TP 1 TPC32t
G
C175 G T302
S 2
TPC8107 A/D_VIN_O

2
1UF

1
A/D_VIN <43> ACIN#
T333
+5VCHG

2
3 TPC32t
T243 T152

2
R149 C R-1
+5V

1
D11 10KOhm B 1
TPC32t TPC32t
D35

0.1UF/25V
1SS355 47K
U47 LM3480 1 E

R671
3 +5VLCM R-2
1 +5VLCM

1
2 1 2 47K
IN OUT

1
GND

2
F02JK2E 2
<50> MAX1909_PDS

C646
10KOhm
T279 Q136

2
C203 C470 R450 DTC144EK

2
4.7KOhm TPC32t

2
1UF 1UF

1
3
U46 GND

1
2 1 +2.5VREF
+2.5VREF
2 2
LM4040BIM3_2.5
ADAPTER IN DETECT
GND 1 2

C460 1UF/10V
1. ADAPTER IN CIRCUIT T168
2. +5VCHG TPC32t

1
3. +5VLCM & +2.5VREF +5VLCM
BAT1_IN#_OC <27>

T153 +5VLCM

100KOhm R654
1
D60

100KOhm
TPC32t R668

1
1 2 2 1
<49,51> BAT1_S
1

1MOhm

6
T154 1SS355 Q141A

2
2

R651
560KOhm

R656

2
R658

TPC32t 2 UM6K1N

100KOhm
U63
BAT1_LOW#(H--L)=

1
R665 BAT1_LOW#(L--H)= 14.67V T195
<49,51> BAT2_S
2 1

2
3 1 2 3 TPC32t 3
1

+A

3
1 BAT1_LOW# <51>

1
OUTA
R674
330KOhm

4.7KOhm 2 -A
2

+2.5VREF 5
<48,49> TS1#
R657
115KOhm

+2.5VREF Q141B

4
5 UM6K1N
1

+B
OUTB 7 BAT2_LOW# <51>

1000PF/16V
6
1

-B

1
R676 R664

D62

C640
1 2 BAT2_LOW#(H--L)=

2
100KOhm
4 8 BAT2_LOW#(L--H)=10.75V

2
4.7KOhm V- V+
2

1SS355
C644

GND
1

R675 LMV393
C656 C657
BATTERY1 IN CIRCUIT
2

1
100KOhm
1000P 1000P 1 2
2

CON Part Number Modify as ME


1

0.1UF 1MOhm
R673
1

T20 T220 A/D_VIN_P


C639 TPC28t TPC28t
2

0.1UF
T224 T19
4 T161 TPC28t TPC28t 4

1
TPC32t
GND
1

+5VLCM
BAT2_IN#_OC <27>

1
L27
1 2 A/D_DOCK_IN
J6
1

6 3 150Ohm/100Mhz
A/D_DOCK_IN <26,50>
1

P_GND
R481 5 2

1
NP_NC
R480 4 1 C72 C50 C49 C75
100KOhm P_GND1

100KOhm
6

Q96A DC_PWR_JACK_3P
2

2
0.1UF/25V 0.1UF 1U 0.1UF
2

2 UM6K1N

DC IN
1

1
T276
TPC32t
3

T14 T164 T166 T130


1

<48,49,51> TS2# 5 TPC28t TPC28t TPC28t TPC28t


Q96B
4

UM6K1N
1000PF/16V
1

5 5
C510
2

GND
Title : Z61Ae
ASUSTECH CO.,LTD. Engineer: ADAMS LIN
BATTERY2 IN CIRCUIT Size Project Name Rev
Custom Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 53 of 57
A B C D E
A B C D E

A/D_DOCK_IN
LM3480-5 +5VCHG (20mA) +5VLCM
SWITCH
(Regulator)
(F02JK2E) LM4040BIM
+2.5VREF
1
(Regulator) 1

VSUSON#
SI9183DT
+3VO (5A) +3VSUS +1.5VSUS/*
(Regulator)
AC_BAT_SYS LTC3728LX +12VO South Bridge
(Controllor) supply
+5VO (8A) +5VSUS

SUSC#_PWR
+12V
(UMC4N)
2 2
MIC5233BM5 +5V
(SI4800DY)
+3V
SUSB#_PWR
SUSC#_PWR SUSB#_PWR
+1.8VO (7A) +1.8V
RT9173ACL5 +0.9VS
(Regulator)
+1.5VO (4A) +1.5VS
+1.8VS
PMN45EN
+5VO +2.5VO (1A) +2.5VS
3 3
VREF3 +3VALWAYS
TPS5130
VREF5 +5VALWAYS
(Controllor)
CPU_VRON
+VCCP
+1.05VO (7A) SWITCH
(PMN45EN) +VCC_GMCH_CORE

SUSB#_PWR
+12VS
(UMC4N)
+5VS
4 4
+3VS

(SI4800DY)

CPU_VRON
+5VO
MAX1987 +VCORE
(27A)
(Controllor)
VRM_PWRGD, CLK_EN#
5 5

Title : Power Flowchart


VR_VID0 - VR_VID5, STP_CPU#, PM_DPRSLPVR, PM_PSI# ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
Custom Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 54 of 57
A B C D E
5 4 3 2 1

CPU Diff Pair


CPU
(Dothan)

CPU Diff Pair


D D

DDR2 CLK
HPLL MPLL
Memory slot
MCH
(Alviso 915GM)
3GIO Diff Pair

3GPLL
DPLL

LVDS PLL

Dot 96M Diff Pair

C C

3GIO Diff Pair

CLK GEN
(ICS954206) 3GPLL
(for DMI)

USB 48M USB


PLL

Ref 14M

ICH6-M
Ref 14M
SIO
PCI 33M LPC47N217

PCI 33M
B B

PCI 33M
CARDBUS&1394
R5C841
PCI 33M 24.576M

LAN

25M

PCI 33M 32.768K


24M
FWH

Azalia
PCI 33M
KBC

A 8M A

PCI 33M
DEBUG PORT

Title : CLK MAP


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
14.318M Date: Thursday, June 09, 2005 Sheet 55 of 57
5 4 3 2 1
A B C D E

A/D_DOCK_IN
+5VLCM
+2.5VREF 2
Power On
SWITCH
4
1 1

1
AC_BAT_SYS
+3VALWAYS +3VALWAYS PM_PWRBTN# PM_SUSC# 5
+5VALWAYS Stratup
3 VSUS_ON#
Circuit T17
PM_RSMRST# ICH6 PM_SUSB#
6
T16
T418 PWROK
VRMPWRGD
+3VSUS

H_PWRGD
PLT_RST#
+5VSUS
T278
+1.5VSUS
2
+2.5VSUS
T20
11 11 2

5 10
SUSC#
+1.8V
ICH6_PWROK 12
T102
+3V T378
ALVISO H_CPURST# CPU
+5V
T321
+12V
PWROK
3 3

9
CLK_PWR_GD#
CK-410M
+1.8VS T62
+0.9VS
+1.5VS
+2.5VS
6 +3VS
+5VS
SUSB#
+12VS
T181
4 4

Power On Sequence

Delay CPU_VRON +VCORE


1 12
T230
+VCCP

7
8
5 5

T195
Title : Z61Ae Power On Sequence
ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
Custom Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 56 of 57
A B C D E
A B C D E

Power Revision History


R1.0

1 1

System
R1.1
R1.1-S01 --> To fine tune power sequence and power select.
R1.1-S02 --> To fine tune clock quality.
R1.1-S03 --> ME change H4 & H6 & H25 to 13-N7510M270 (It need to modify in BOM by self.)
R1.1-S04 --> CE1 not used.Release space for bluetooth.
R1.1-S05 --> Follow W3V R2.1
R1.1-S06 --> RealTek suggestion.(To support MicroSoft new HCT12.1 test program.)
R1.1-S07 --> RealTek suggestion.To support Sofeware Jack Detect(JD) function.
R1.1-S08 --> To avoid POP sound when system BOOT.
R1.1-S09 --> To fine tune SPDIF_A signal quality.
R1.1-S10 --> unmount R629.(Due to dual pull low with R637.)
R1.1-S11 --> To avoid charge LED flash when adapter in and remove battery.
R1.1-S12 --> To support alert by BIOS control and delete R174 dual pull high.
R1.1-S13 --> Bypass MIC amplifer to improve MIC signal quality.
2
R1.1-S14 --> RealTek suggestion. 2
R1.1-S15 --> To use thinner than before.
R1.1-S16 --> Follow M6V/A R2.1
R1.1-S17 --> For factory testing.Sofeware can use the GPIO into test mode.
R1.1-S18 --> To solve CRT ripple problem.
R1.1-S19 --> Delete BAYDOCK_IN# pull high.Due to dual pull high with RN26.
R1.1-S20 --> Change DDR2 SODIMM to DUAL DDR2 DIMM.
R1.1-S21 --> Update PCB_VID.
R1.1-S22 --> To support HDD/ODD Hot SWAP.
R1.1-S23 --> To slove QTC bug for PRINTER PORT fail.(Run QA+PRO V)
R1.1-S24 --> For factory ATS power test at P/R stage.
R1.1-S25 --> To match ME new MIC cable defination.
R1.1-S26 --> Change to digital groung.To avoid noise.
R1.1-S27 --> RICOH suggestion.
R1.1-S28 --> Del unused Components and Net to release free space.
R1.1-S29 --> To avoid VCCA wrong Value.
R1.1-S30 --> delete unmount part to release MB space.
R1.1-S31 --> Due to KB Cover shut down cause Sys. Power on.
R1.1-S32 --> Unmount C for Cost down.
R1.1-S33 --> Fine tune LAN driving.
R1.1-S34 --> Change JRST1 PCB footprint for Layout suggestion.
R1.1-S35 --> Change R to RPACK for Cost down.
R1.1-S36 --> Fine tune -R value.
R1.1-S37 --> For Port Bar LAN Wake-up.
R1.1-S38 --> Give BT_ON signal a default state.
R2.0
R2.0-S01 --> To fine tune power sequence.
R2.0-S02 --> To fine tune crystal PPM.
3
R2.0-S03 --> To modify some mistake in V1.1. 3
R2.0-S04 --> To Re-define LED.
R2.0-S05 --> To get power switch signal when end-user press power key quickly.(over 30ms then PWR_ON# will be low.)
R2.0-S06 --> To avoid +3VSUS sometimes re-start in battery mode then loss 10mA arround.(Add 39K ohm can make +3VSUS low faster and U60 IC will shutdown faster.)
R2.0-S07 --> To solve can not resume when battery low.
R2.0-S08 --> To add 0.1u by EMI request.
R2.0-S09 --> To check O/S or DOS mdoe.To control power LED flash when battery low about 10%.DOS mode H/W detect battery then flash LED.O/S mode S/W detect 10% from gauge then inform LED to flash.
R2.0-S10 --> Mount MIC amplifer to improve MIC volume.
R2.0-S11 --> To set Switch default for Dothan.
R2.0-S12 --> To fine tune Speaker volume.
R2.0-S13 --> Fine tune CB_GBRST# timing.
R2.0-S14 --> To solve USB device leakage to +5V in S3.When use USB HDD storage that need power adapter.

4 4

5 5

Title : Revision History


ASUSTECH CO.,LTD. Engineer: Sam Wang
Size Project Name Rev
C Z61Ae 2.0
Date: Thursday, June 09, 2005 Sheet 57 of 57
A B C D E

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