LTC1864/LTC1865

µPower, 16-Bit, 250ksps

1- and 2-Channel
ADCs in MSOP
FEATURES DESCRIPTION
n 16-Bit 250ksps ADCs in MSOP Package The LTC®1864/LTC1865 are 16-bit A/D converters that
n Single 5V Supply are offered in MSOP and SO-8 packages and operate
n Low Supply Current: 850μA (Typ) on a single 5V supply. At 250ksps, the supply current is
n Auto Shutdown Reduces Supply Current only 850μA. The supply current drops at lower speeds
to 2μA at 1ksps because the LTC1864/LTC1865 automatically power down
n True Differential Inputs between conversions. These 16-bit switched capacitor
n 1-Channel (LTC1864) or 2-Channel (LTC1865) successive approximation ADCs include sample-and-
Versions holds. The LTC1864 has a differential analog input with an
n SPI/MICROWIRE™ Compatible Serial I/O adjustable reference pin. The LTC1865 offers a software-
n 16-Bit Upgrade to 12-Bit LTC1286/LTC1298 selectable 2-channel MUX and an adjustable reference pin
n Pin Compatible with 12-Bit LTC1860/LTC1861 on the MSOP version.
n Guaranteed Operation to +125°C (MSOP Package) The 3-wire, serial I/O, small MSOP or SO-8 package and
extremely high sample rate-to-power ratio make these
APPLICATIONS ADCs ideal choices for compact, low power, high speed
systems.
n High Speed Data Acquisition
n Portable or Compact Instrumentation These ADCs can be used in ratiometric applications or with
n Low Power Battery-Operated Instrumentation external references. The high impedance analog inputs
n Isolated and/or Remote Data Acquisition and the ability to operate with reduced spans down to
1V full scale, allow direct connection to signal sources
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. in many applications, eliminating the need for external
gain stages.

TYPICAL APPLICATION
Single 5V Supply, 250ksps, 16-Bit Sampling ADC Supply Current vs Sampling Frequency
1000
1μF
5V 100
SUPPLY CURRENT (μA)

LTC1864 10
1 8
VREF VCC
2 7
ANALOG INPUT IN+ SCK 1
3 6 SERIAL DATA LINK TO
0V TO 5V IN– SDO ASIC, PLD, MPU, DSP
4 5 OR SHIFT REGISTERS 0.1
GND CONV
18645 TA01

0.01
0.01 0.1 1 10 100 1000
SAMPLING FREQUENCY (kHz)
18645 TA02

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LTC1864/LTC1865
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)

Supply Voltage (VCC) .................................................7V Operating Temperature Range

Ground Voltage Difference LTC1864C/LTC1865C/
AGND, DGND LTC1865 MSOP Package ............ ±0.3V LTC1864AC/LTC1865AC...........................0°C to 70°C
Analog Input ................ (GND – 0.3V) to (VCC + 0.3V) LTC1864I/LTC1865I/
Digital Input ................................ (GND – 0.3V) to 7V LTC1864AI/LTC1865AI ...................... – 40°C to 85°C
Digital Output .............. (GND – 0.3V) to (VCC + 0.3V) LTC1864H/LTC1865H
Power Dissipation .............................................. 400mW LTC1864AH/LTC1865AH ................. – 40°C to 125°C
Storage Temperature Range...................–65°C to 150°C
Lead Temperature (Soldering, 10 sec) ..................300°C

PIN CONFIGURATION
LTC1864 LTC1865 TOP VIEW
TOP VIEW
CONV 1 10 VREF
VREF 1 8 VCC
CH0 2 9 VCC
IN+ 2 7 SCK
CH1 3 8 SCK
IN¯ 3 6 SDO AGND 4 7 SDO
GND 4 5 CONV DGND 5 6 SDI
MS8 PACKAGE MS PACKAGE
8-LEAD PLASTIC MSOP 10-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 210°C/W
TJMAX = 150°C, θJA = 210°C/W

LTC1864 TOP VIEW LTC1865 TOP VIEW

VREF 1 8 VCC CONV 1 8 VCC

IN+ 2 7 SCK CH0 2 7 SCK

IN– 3 6 SDO CH1 3 6 SDO

GND 4 5 CONV GND 4 5 SDI

S8 PACKAGE S8 PACKAGE
8-LEAD PLASTIC SO 8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 175°C/W TJMAX = 150°C, θJA = 175°C/W

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1864CMS8#PBF LTC1864CMS8#TRPBF LTHQ 8-Lead Plastic MSOP 0°C to 70°C
LTC1864IMS8#PBF LTC1864IMS8#TRPBF LTHQ 8-Lead Plastic MSOP –40°C to 85°C
LTC1864HMS8#PBF LTC1864HMS8#TRPBF LTHQ 8-Lead Plastic MSOP –40°C to 125°C
LTC1864ACMS8#PBF LTC1864ACMS8#TRPBF LTHQ 8-Lead Plastic MSOP 0°C to 70°C
LTC1864AIMS8#PBF LTC1864AIMS8#TRPBF LTHQ 8-Lead Plastic MSOP –40°C to 85°C
LTC1864AHMS8#PBF LTC1864AHMS8#TRPBF LTHQ 8-Lead Plastic MSOP –40°C to 125°C
LTC1864CS8#PBF LTC1864CS8#TRPBF 1864 8-Lead Plastic SO 0°C to 70°C
LTC1864IS8#PBF LTC1864IS8#TRPBF 1864I 8-Lead Plastic SO –40°C to 85°C
LTC1864ACS8#PBF LTC1864ACS8#TRPBF 1864A 8-Lead Plastic SO 0°C to 70°C
LTC1684AIS8#PBF LTC1684AIS8#TRPBF 1864AI 8-Lead Plastic SO –40°C to 85°C
LTC1865CMS#PBF LTC1865CMS#TRPBF LTHS 10-Lead Plastic MSOP 0°C to 70°C
LTC1865IMS#PBF LTC1865IMS#TRPBF LTHS 10-Lead Plastic MSOP –40°C to 85°C
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 LTC1864/LTC1865
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1865HMS#PBF LTC1865HMS#TRPBF LTHS 10-Lead Plastic MSOP –40°C to 125°C
LTC1865ACMS#PBF LTC1865ACMS#TRPBF LTHS 10-Lead Plastic MSOP 0°C to 70°C
LTC1865AIMS#PBF LTC1865AIMS#TRPBF LTHS 10-Lead Plastic MSOP –40°C to 85°C
LTC1865AHMS#PBF LTC1865AHMS#TRPBF LTHS 10-Lead Plastic MSOP –40°C to 125°C
LTC1865CS8#PBF LTC1865CS8#TRPBF 1865 8-Lead Plastic SO 0°C to 70°C
LTC1865IS8#PBF LTC1865IS8#TRPBF 1865I 8-Lead Plastic SO –40°C to 85°C
LTC1865ACS8#PBF LTC1865ACS8#TRPBF 1865A 8-Lead Plastic SO 0°C to 70°C
LTC1865AIS8#PBF LTC1865AIS8#TRPBF 1865AI 8-Lead Plastic SO –40°C to 85°C
LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1864CMS8 LTC1864CMS8#TR LTHQ 8-Lead Plastic MSOP 0°C to 70°C
LTC1864IMS8 LTC1864IMS8#TR LTHQ 8-Lead Plastic MSOP –40°C to 85°C
LTC1864HMS8 LTC1864HMS8#TR LTHQ 8-Lead Plastic MSOP –40°C to 125°C
LTC1864ACMS8 LTC1864ACMS8#TR LTHQ 8-Lead Plastic MSOP 0°C to 70°C
LTC1864AIMS8 LTC1864AIMS8#TR LTHQ 8-Lead Plastic MSOP –40°C to 85°C
LTC1864AHMS8 LTC1864AHMS8#TR LTHQ 8-Lead Plastic MSOP –40°C to 125°C
LTC1864CS8 LTC1864CS8#TR 1864 8-Lead Plastic SO 0°C to 70°C
LTC1864IS8 LTC1864IS8#TR 1864I 8-Lead Plastic SO –40°C to 85°C
LTC1864ACS8 LTC1864ACS8#TR 1864A 8-Lead Plastic SO 0°C to 70°C
LTC1684AIS8 LTC1684AIS8#TR 1864AI 8-Lead Plastic SO –40°C to 85°C
LTC1865CMS LTC1865CMS#TR LTHS 10-Lead Plastic MSOP 0°C to 70°C
LTC1865IMS LTC1865IMS#TR LTHS 10-Lead Plastic MSOP –40°C to 85°C
LTC1865HMS LTC1865HMS#TR LTHS 10-Lead Plastic MSOP –40°C to 125°C
LTC1865ACMS LTC1865ACMS#TR LTHS 10-Lead Plastic MSOP 0°C to 70°C
LTC1865AIMS LTC1865AIMS#TR LTHS 10-Lead Plastic MSOP –40°C to 85°C
LTC1865AHMS LTC1865AHMS#TR LTHS 10-Lead Plastic MSOP –40°C to 125°C
LTC1865CS8 LTC1865CS8#TR 1865 8-Lead Plastic SO 0°C to 70°C
LTC1865IS8 LTC1865IS8#TR 1865I 8-Lead Plastic SO –40°C to 85°C
LTC1865ACS8 LTC1865ACS8#TR 1865A 8-Lead Plastic SO 0°C to 70°C
LTC1865AIS8 LTC1865AIS8#TR 1865AI 8-Lead Plastic SO –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

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LTC1864/LTC1865
CONVERTER AND MULTIPILEXER CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions, unless otherwise noted.
LTC1864/LTC1865 LTC1864A/LTC1865A
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Resolution l 16 16 Bits
No Missing Codes Resolution l 14 15 Bits
INL (Note 3) l ±8 ±6 LSB
H-Grade (Note 3) l ±8.5 ±6.5 LSB
Transition Noise 1.1 1.1 LSBRMS
Gain Error l ±20 ±20 mV
Offset Error LTC1864 SO-8 and MSOP, LTC1865 MSOP l ±2 ±5 ±2 ±5 mV
LTC1865 SO-8 l ±3 ±7 ±3 ±7 mV
Input Differential Voltage Range VIN = IN+ – IN– l 0 VREF 0 VREF V
Absolute Input Range IN+ Input –0.05 VCC + 0.05 –0.05 VCC + 0.05 V
IN– Input –0.05 VCC/2 –0.05 VCC/2 V
VREF Input Range LTC1864 SO-8 and MSOP, 1 VCC 1 VCC V
LTC1865 MSOP
Analog Input Leakage Current (Note 4) l ±1 ±1 μA
CIN Input Capacitance In Sample Mode 12 12 pF
During Conversion 5 5 pF

DYNAMIC ACCURACY
TA = 25°C. VCC = 5V, VREF = 5V, fSAMPLE = 250kHz, unless otherwise noted.
LTC1864/LTC1865
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 87 dB
S/(N + D) Signal-to-Noise Plus Distortion Ratio 10kHz Input Signal 83 dB
100kHz Input Signal 76 dB
THD Total Harmonic Distortion Up to 5th Harmonic 10kHz Input Signal 88 dB
100kHz Input Signal 77 dB
Full Power Bandwidth 20 MHz
Full Linear Bandwidth S/(N+D) ≥ 75dB 125 kHz

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 LTC1864/LTC1865
DIGITAL AND DC ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply
over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, unless otherwise noted.
LTC1864/LTC1865
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage VCC = 5.25V l 2.4 V
VIL Low Level Input Voltage VCC = 4.75V l 0.8 V
IIH High Level Input Current VIN = VCC l 2.5 μA
IIL Low Level Input Current VIN = 0V l –2.5 μA
VOH High Level Output Voltage VCC = 4.75V, IO = 10μA l 4.5 4.74 V
VCC = 4.75V, IO = 360μA l 2.4 4.72 V
VOL Low Level Output Voltage VCC = 4.75V, IO = 1.6mA ● 0.4 V
IOZ Hi-Z Output Leakage CONV = VCC ● ±3 μA
ISOURCE Output Source Current VOUT = 0V –25 mA
ISINK Output Sink Current VOUT = VCC 20 mA
IREF Reference Current (LTC1864 SO-8 and MSOP, CONV = VCC ● 0.001 3 μA
LTC1865 MSOP) fSMPL = fSMPL(MAX) ● 0.05 0.1 mA
ICC Supply Current CONV = VCC After Conversion ● 0.001 3 μA
CONV = VCC After Conversion, H-Grade ● 0.001 5 μA
fSMPL = fSMPL(MAX) ● 0.85 1.3 mA
PD Power Dissipation fSMPL = fSMPL(MAX) 4.25 mW

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LTC1864/LTC1865
RECOMMENDED OPERATING CONDITIONS The ● denotes specifications which apply over the
full operating temperature range, otherwise specifications are TA = 25°C.
LTC1864/LTC1865
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage 4.75 5.25 V
fSCK Clock Frequency ● 20 MHz
H-Grade ● 16.7 MHz
tCYC Total Cycle Time 16 • SCK + tCONV μs
tSMPL Analog Input Sampling Time LTC1864 (Note 5) 16 SCK
LTC1865 (Note 5) 14 SCK
tsuCONV Setup Time CONV↓ Before First SCK↑ 60 30 ns
(See Figure 1) H-Grade 65 30 ns
thDI Hold Time SDI After SCK↑ LTC1865 15 ns
tsuDI Setup Time SSDI Stable Before SCK↑ LTC1865 15 ns
tWHCLK SCK High Time fSCK = fSCK(MAX) 40% 1/fSCK
tWLCLK SCK Low Time fSCK = fSCK(MAX) 40% 1/fSCK
tWHCONV CONV High Time Between Data Transfer (Note 5) tCONV μs
Cycles
tWLCONV CONV Low Time During Data Transfer (Note 5) 16 SCK
thCONV Hold Time CONV Low After Last SCK↑ 13 ns

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 LTC1864/LTC1865
TIMING CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are TA = 25°C. VCC = 5V, VREF = 5V, fSCK = fSCK(MAX) as defined in Recommended Operating Conditions,
unless otherwise noted.
LTC1864/LTC1865
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tCONV Conversion Time (See Figure 1) ● 2.75 3.2 μs
H-Grade ● 2.75 3.3 μs
fSMPL(MAX) Maximum Sampling Frequency ● 250 kHz
H-Grade ● 234 kHz
tdDO Delay Time, SCK↓ to SDO Data Valid CLOAD = 20pF 15 20 ns
CLOAD = 20pF ● 25 ns
CLOAD = 20pF, H-Grade ● 30 ns
tdis Delay Time, CONV↑ to SDO Hi-Z ● 30 60 ns
H-Grade ● 30 65 ns
ten Delay Time, CONV↓ to SDO Enabled CLOAD = 20pF ● 30 60 ns
CLOAD = 20pF, H-Grade ● 30 65 ns
thDO Time Output Data Remains Valid After SCK↓ CLOAD = 20pF ● 5 10 ns
tr SDO Rise Time CLOAD = 20pF 8 ns
tf SDO Fall Time CLOAD = 20pF 4 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 3: Integral nonlinearity is defined as deviation of a code from a
may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual endpoints of the transfer curve.
Maximum Rating condition for extended periods may affect device The deviation is measured from the center of the quantization band.
reliability and lifetime. Note 4: Channel leakage current is measured while the part is in sample
Note 2: All voltage values are with respect to GND. mode.
Note 5: Guaranteed by design, not subject to test.

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LTC1864/LTC1865
TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs Sampling
Frequency Supply Current vs Temperature Sleep Current vs Temperature
1000 1000 1000
VCC = 5V CONV = VCC = 5V
TA = 25°C 900
CONV LOW = 800ns
100 800 800

SUPPLY CURRENT (μA)

SUPPLY CURRENT (μA)

SLEEP CURRENT (nA)

700

10 600 600
500
1 400 400
300
200 VCC = 5V 200
0.1
VREF = 5V
fSAMPLE = 250kHz 100
CONV HIGH = 3.2μS
0.01 0 0
0.01 0.1 1.0 10 100 1000 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
SAMPLING FREQUENCY (kHz) TEMPERATURE (°C) TEMPERATURE (°C)
18645 G01 18645 G02 18645 G03

Reference Current vs Reference Current vs Reference Current vs

Sampling Rate Temperature Reference Voltage
60 55 60
VCC = 5V VCC = 5V VCC = 5V
TA = 25°C 54 VREF = 5V TA = 25°C
50 VREF = 5V f = 250kHz 50 fS = 250kHz
53 S

REFERENCE CURRENT (μA)

REFERENCE CURRENT (μA)

REFERENCE CURRENT (μA)

CONV LOW = 800ns

52
40 40
51
30 50 30
49
20 20
48
47
10 10
46
0 45 0
0 50 100 150 200 250 –50 –25 0 25 50 75 100 125 0 1 2 3 4 5
SAMPLE RATE (kHz) TEMPERATURE (°C) VREF (V)
18645 G04 18645 G05 18645 G06

Analog Input Leakage Current vs

Typical INL Curve Typical DNL Curve Temperature
4 2 100
VCC = 5V VCC = 5V VCC = 5V
TA = 25°C TA = 25°C VREF = 5V
VREF = 5V VREF = 5V CONV = 0V
ANALOG INPUT LEAKAGE (nA)

2 1 75
DNL ERROR (LSBs)
INL ERROR (LSBs)

0 0 50

–2 –1 25

–4 –2 0
0 16384 32768 49152 65536 0 16384 32768 49152 65536 –50 –25 0 25 50 75 100 125
CODE CODE TEMPERATURE (°C)
18645 G07 18645 G08 18645 G09

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 LTC1864/LTC1865
TYPICAL PERFORMANCE CHARACTERISTICS
Change in Offset Error vs Change in Gain Error vs
Reference Voltage Change in Offset vs Temperature Reference Voltage
75 5 20
VCC = 5V VCC = 5V VCC = 5V
TA = 25°C 4 VREF = 5V 15 TA = 25°C
CHANGE IN OFFSET ERROR (LSB)

CHANGE IN GAIN ERROR (LSB)

3

CHANGE IN OFFSET (LSB)

50 10
2
5
1
25 0 0

–1 –5
–2
0 –10
–3
–15
–4
–25 –5 –20
0 1 2 3 4 5 –50 –25 0 25 50 75 100 125 0 1 2 3 4 5
REFERENCE VOLTAGE (V) TEMPERATURE (°C) REFERENCE VOLTAGE(V)
18645 G10 18645 G11 18645 G12

Change in Gain Error vs Histogram of 4096 Conversions of

Temperature a DC Input Voltage 4096 Point FFT Nonaveraged
5 1800 0
VCC = 5V VCC = 5V fS = 203.125kHz
4 VREF = 5V 1600 1534 TA = 25°C fIN = 99.72763kHz
VREF = 5V –20
VCC = 5V
CHANGE IN GAIN ERROR (LSB)

3 1400 VREF = 5V
2 1178 –40 TA = 25°C
1200
AMPLITUDE (dB)
FREQUENCY

1
1000 –60
0
800 729 –80
–1
600 516
–2 –100
–3 400
–120
–4 200 127
0 0 12 0 0
–5 0 –140
–50 –25 0 25 50 75 100 125 –4 –3 –2 –1 0 1 2 3 4 5 0 20 40 60 80 100 120
TEMPERATURE (°C) CODE FREQUENCY (kHz)
18645 G13 18645 G14 18645 G15

SINAD vs Frequency THD vs Frequency SFDR vs Frequency

100 0 100
90 SNR –10 90
80 –20 80
70 SINAD –30 70
–40
SINAD (dB)

60 60
SFDR (dB)
THD (dB)

50 –50 50
40 –60 40
30 –70 30
VCC = 5V VCC = 5V VCC = 5V
20 –80 VREF = 5V 20 VREF = 5V
VREF = 5V
TA = 25°C TA = 25°C TA = 25°C
10 –90 10
VIN = 0dB VIN = 0dB VIN = 0dB
0 –100 0
1 10 100 1000 1 10 100 1000 1 10 100 1000
FIN (kHz) FIN (kHz) FIN (kHz)
18645 G16 18645 G17 18645 G18

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LTC1864/LTC1865
PIN FUNCTIONS
LTC1864
VREF (Pin 1): Reference Input. The reference input defines
the span of the A/D converter and must be kept free of
noise with respect to GND.
IN +, IN–
(Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
CONV (Pin 5): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is finished, the part
LTC1865 (MSOP Package)
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is finished, the part
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to AGND.
AGND (Pin 4): Analog Ground. AGND should be tied directly
to an analog ground plane.
DGND (Pin 5): Digital Ground. DGND should be tied directly
to an analog ground plane.
SDI (Pin 6): Digital Data Input. The A/D configuration
word is shifted into this input.
LTC1865 (SO-8 Package)
CONV (Pin 1): Convert Input. A logic high on this input
starts the A/D conversion process. If the CONV input is
left high after the A/D conversion is finished, the part
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
CH0, CH1 (Pins 2, 3): Analog Inputs. These inputs must
be free of noise with respect to GND.
GND (Pin 4): Analog Ground. GND should be tied directly
to an analog ground plane.
10
powers down. A logic low on this input enables the SDO
pin, allowing the data to be shifted out.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this pin.
SCK (Pin 7): Shift Clock Input. This clock synchronizes
the serial data transfer.
VCC (Pin 8): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane.
SDO (Pin 7): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK (Pin 8): Shift Clock Input. This clock synchronizes
the serial data transfer.
VCC (Pin 9): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the
analog ground plane.
VREF (Pin 10): Reference Input. The reference input defines
the span of the A/D converter and must be kept free of
noise with respect to AGND.
SDI (Pin 5): Digital Data Input. The A/D configuration
word is shifted into this input.
SDO (Pin 6): Digital Data Output. The A/D conversion
result is shifted out of this output.
SCK (Pin 7): Shift Clock Input. This clock synchronizes
the serial data transfer.
VCC (Pin 8): Positive Supply. This supply must be kept
free of noise and ripple by bypassing directly to the analog
ground plane. VREF is tied internally to this pin.
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 LTC1864/LTC1865
FUNCTIONAL BLOCK DIAGRAM

VCC CONV (SDI) SCK

PIN NAMES IN
PARENTHESES
REFER TO LTC1865
CONVERT BIAS AND SERIAL SDO
CLK SHUTDOWN PORT

DATA IN

16 BITS
IN+
(CH0) + 16-BIT
SAMPLING DATA OUT
IN– ADC
(CH1) –

18645 BD
GND VREF

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LTC1864/LTC1865
TEST CIRCUITS
Load Circuit for tdDO, tr, tf, tdis and ten Voltage Waveforms for SDO Rise and Fall Times, tr, tf
TEST POINT
VOH
SDO
VOL
3k VCC tdis WAVEFORM 2, ten
SDO
tdis WAVEFORM 1 tr tf 18645 TC04

20pF

18645 TC01

Voltage Waveforms for ten Voltage Waveforms for tdis

CONV
CONV VIH

SDO 18645 TC03

SDO 90%
WAVEFORM 1
ten
(SEE NOTE 1)
tdis
SDO
WAVEFORM 2
Voltage Waveforms for SDO Delay Times,tdDO and thDO 10%
(SEE NOTE 2)
NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL
SCK
VIL NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH
THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL
tdDO 18645 TC05

thDO
VOH
SDO
VOL
18645 TC02

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 LTC1864/LTC1865
APPLICATIONS INFORMATION
LTC1864 OPERATION Analog Inputs

Operating Sequence
The LTC1864 conversion cycle begins with the rising edge
of CONV. After a period equal to t CONV, the conversion is
finished. If CONV is left high after this time, the LTC1864
goes into sleep mode drawing only leakage current. On the
falling edge of CONV, the LTC1864 goes into sample mode
and SDO is enabled. SCK synchronizes the data transfer
with each bit being transmitted from SDO on the falling
SCK edge. The receiving system should capture the data
from SDO on the rising edge of SCK. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefinitely. See Figure 1.
The LTC1864 has a unipolar differential analog input. The
converter will measure the voltage between the “IN + ”
and “IN–” inputs. A zero code will occur when IN+ minus
IN– equals zero. Full scale occurs when IN+ minus IN–
equals VREF minus 1LSB. See Figure 2. Both the “IN+” and
“IN–” inputs are sampled at the same time, so common
mode noise on the inputs is rejected by the ADC. If “IN–”
is grounded and VREF is tied to VCC, a rail-to-rail input
span will result on “IN+” as shown in Figure 3.
Reference Input
The voltage on the reference input of the LTC1864 defines
the full-scale range of the A/D converter. The LTC1864 can
operate with reference voltages from VCC to 1V.

tsuCONV

CONV tSMPL
tCONV SLEEP MODE

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

SCK

SDO B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*

Hi-Z Hi-Z

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE

APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
18645 F01

Figure 1. LTC1864 Operating Sequence

1111111111111111 1μF
1111111111111110
VCC
•
•
• LTC1864
1 8
0000000000000001 VIN* VREF VCC
0000000000000000 2 7
VIN = 0V TO VCC IN+ SCK
0V

1LSB

SERIAL DATA LINK TO

VREF – 1LSB

VREF
VREF – 2LSB

3 6
*VIN = IN+ – IN– IN– SDO ASIC, PLD, MPU, DSP
4 5 OR SHIFT REGISTERS
GND CONV
18645 F02 18645 F03

Figure 2. LTC1864 Transfer Curve Figure 3. LTC1864 with Rail-to-Rail Input Span

18645fb

13
LTC1864/LTC1865
APPLICATIONS INFORMATION
LTC1865 OPERATION single-ended mode, all input channels are measured
with respect to GND. A zero code will occur when the
Operating Sequence “+” input minus the “–” input equals zero. Full scale oc-
The LTC1865 conversion cycle begins with the rising edge curs when the “+” input minus the “–” input equals VREF
of CONV. After a period equal to t CONV, the conversion is minus 1LSB. See Figure 5. Both the “+” and “–” inputs
finished. If CONV is left high after this time, the LTC1865 are sampled at the same time so common mode noise
goes into sleep mode drawing only leakage current. The is rejected. The input span in the SO-8 package is fixed
LTC1865’s 2-bit data word is clocked into the SDI input at VREF = VCC. If the “–” input in differential mode is
on the rising edge of SCK after CONV goes low. Additional grounded, a rail-to-rail input span will result on the “+”
inputs on the SDI pin are then ignored until the next CONV input.
cycle. The shift clock (SCK) synchronizes the data transfer
Reference Input
with each bit being transmitted on the falling SCK edge and
captured on the rising SCK edge in both transmitting and The reference input of the LTC1865 SO-8 package is
receiving systems. The data is transmitted and received internally tied to VCC. The span of the A/D converter is
simultaneously (full duplex). After completing the data therefore equal to VCC. The voltage on the reference
transfer, if further SCK clocks are applied with CONV low, input of the LTC1865 MSOP package defines the span
SDO will output zeros indefinitely. See Figure 4. of the A/D converter. The LTC1865 MSOP package can
operate with reference voltages from 1V to VCC.
Analog Inputs
Table 1. Multiplexer Channel Selection
The two bits of the input word (SDI) assign the MUX
MUX ADDRESS CHANNEL #
configuration for the next requested conversion. For a SGL/DIFF ODD/SIGN 0 1 GND
given channel selection, the converter will measure the SINGLE-ENDED 1 0 + –
voltage between the two channels indicated by the “+” MUX MODE 1 1 + –
and “–” signs in the selected row of the following table. In DIFFERENTIAL 0 0 + –
MUX MODE 0 1 – +
18645 TBL1

CONV tSMPL
tCONV SLEEP MODE

SDI DON’T CARE S/D O/S DON’T CARE

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

SCK

SDO B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*

Hi-Z Hi-Z

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE

APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY

18645 F04

Figure 4. LTC1865 Operating Sequence

18645fb

14

APPLICATIONS INFORMATION
GENERAL ANALOG CONSIDERATIONS
Grounding
The LTC1864/LTC1865 should be used with an analog
ground plane and single point grounding techniques. Do not
use wire wrapping techniques to breadboard and evaluate
the device. To achieve the optimum performance, use a
printed circuit board. The ground pins (AGND and DGND
for the LTC1865 MSOP package and GND for the LTC1864
and LTC1865 SO-8 package) should be tied directly to the
analog ground plane with minimum lead length.
Bypassing
For good performance, the VCC and VREF pins must be free
of noise and ripple. Any changes in the VCC/VREF voltage
with respect to ground during the conversion cycle can
LTC1864/LTC1865
induce errors or noise in the output code. Bypass the VCC
and VREF pins directly to the analog ground plane with
a minimum of 1μF tantalum. Keep the bypass capacitor
leads as short as possible.
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1864/LTC1865
have capacitive switching input current spikes. These cur-
rent spikes settle quickly and do not cause a problem if
source resistances are less than 200Ω or high speed op
amps are used (e.g., the LT®1211, LT1469, LT1807, LT1810,
LT1630, LT1226 or LT1215). But if large source resistances
are used, or if slow settling op amps drive the inputs, take
care to ensure the transients caused by the current spikes
settle completely before the conversion begins.

1111111111111111
1111111111111110
•
•
•
0000000000000001 VIN*
0000000000000000
0V

1LSB

VCC – 1LSB

VCC
VCC – 2LSB

*VIN = (SELECTED “+” CHANNEL) –

(SELECTED “–” CHANNEL) 18645 F05

REFER TO TABLE 1

Figure 5. LTC1865 Transfer Curve

18645fb

15
 LTC1864 Evaluation Circuit Schematic

16
5VDIG 5VDIG
15V 5VAN R4 5VDIG
15V R3
2Ω 2Ω C13 C14
E1 2 6 1 3
15V VIN VOUT C2 VIN VOUT 0.1μF 0.1μF
C26
U1 GND J4
C27 GND C1 1μF 10μF
LT1021-5 3201S40G1
0.1μF 4 0.1μF 10V 2 6.3V
0805 5VAN 1206 U4 39 40
J1
IN+ 1 2 5VDIG 74HC595ADT
IN+ 37 38
JP1 C3 16 1 35 36
R7 C5 C4
15V 0.1μF 10μF V QB
51Ω 0.1μF 15 CC 2 33 34
6.3V QA QC
0PT 1206 14 3 31 32
A QD
RN1 13 4 29 30
R1 OENB QE
+ 1 8 330 12 5 27 28
1 2 510Ω V VCC LCLK QF
U2 2 REF 7 1 8 11 6 25 26
IN+ SCK SCLK QG
E8 OPT JP2 C8 3 6 2 7 R5 10 7 23 24
AGND C7 IN– SDO 402Ω, 1% RESET QH
– 1000pF 4 5 3 6 9 8 21 22
GND CONV
LTC1864/LTC1865

390pF SQH GND

OPT 4 5 19 20
E9 C21 U8A
U3 47pF 74AC14 17 18
C6 C9 C10 15 16
LTC1864CMS8
–15V 0.1μF R2 180pF 680pF 16 1 13 14
J2 OPT VCC QB
510Ω 15 2 11 12
IN– QA QC
IN– R6 14 3 9 10
R8 2 C12 402Ω A QD
C11 13 4 7 8
51Ω JP3 1000pF 1% OENB QE
390pF 12 5 5 6
0PT OPT LCLK QF
APPLICATIONS INFORMATION

1 11 6 3 4
C22 U8B SCLK QG
ANALOG GROUND PLANE 10 7 1 2
47pF 74AC14 RESET QH
C23 C24 9 8
5VDIG 5VDIG SQH GND
0.1μF 0.1μF C15
U5 5VDIG 0.1μF
U12A U12B 74HC595ADT U9D
U9B 74AC109 16 74AC109 16 U9C 74AC00
74AC00 2 VCC 6 14 VCC 10 JP4 74AC00
J Q J Q 2
3 7 13 9 1
K Q K Q
4 12 C25
CLK CLK 5VDIG 0.1μF E2
1 15
CLR CLR CONV
5 8 11 8
PRE GND PRE GND E3 ENABLE
DATA
5VDIG 5VDIG 2 E7
U9A DGND
JP5
74AC00 C16 C17 U8D U8E U8F 1 E6
0.1μF 0.1μF 74AC14 74AC14 DGND
74AC14
5VDIG
5VDIG 5VDIG E4
DOUT
2 4 6 E5
U6 U7 C18 CLKOUT
74HC163AD 74HC163AD R12 5VDIG 0.1μF
10k J3
JP8 1 16 1 16
RESET VCC RESET VCC CLKIN
2 15 2 15 U10 C19
CLK RCO CLK RCO 1 R9
1 3 5 3 14 3 14 LTC1799 5VDIG 0.1μF
P0 Q0 P0 Q0 JP6 51Ω
4 13 4 13 1 + 5 2
P1 Q1 P1 Q1 V OUT JP7
5 12 5 12 2
P2 Q2 P2 Q2 GND 3 2 1
6 11 6 11 3 4
P3 Q3 P3 Q3 SET DIV 3
2 4 6 7 10 7 10
ENP ENT ENP ENT R10 U13A U13D
8 9 8 9 20k U8C
GND LO GND LO 74AC32 74AC32
JP9 74AC14

1 3 5 NOTES: UNLESS OTHERWISE SPECIFIED

U13C INSTALL SHUNTS ON JP1, JP3-JP7 PIN 1 AND PIN2;
U13B CLK ON JP8 AND JP9 PIN 2 AND PIN 4, PIN 3 AND PIN 5.
74AC32
74AC32 18645 AI1

18645fb
 LTC1864/LTC1865
APPLICATIONS INFORMATION

Component Side Silk Screen for LTC1864 Evaluation Circuit

Component Side Showing Traces Bottom Side Showing Traces

(Note Sider Traces on Analog Side) (Note Almost No Analog Traces on Board Bottom)

Ground Layer with Separate Analog and Digital Grounds Supply Layer with 5V Digital Supply and
Analog Ground Repeated

18645fb

17
LTC1864/LTC1865
APPLICATIONS INFORMATION

U11
15V LT1121CST-5 5VAN R4 5VDIG

1 3 2Ω
VIN VOUT C26
GND 10μF
2 6.3V
5VAN 1206
C3
10μF C4
6.3V 0.1μF
1206 5VDIG 5VDIG 15V
RN1 LTC1485
1 8 330 1 8
1V to 5V REFERENCE V VCC RO VCC
2 REF 7 1 8 2 7
0V to VREF INPUT IN+ SCK RE B
3 6 2 7 3 6
IN– SDO DE A
4 5 3 6 4 5
GND CONV DI GND 120Ω
4 5
U3
LTC1864CMS8

ANALOG GROUND PLANE 4 CONDUCTOR

TELEPHONE WIRES
C23 C24 TO RECEIVER
5VDIG 0.1μF 5VDIG 0.1μF
4

1 2
500Ω
U12A U12B 5V
U9B 74AC109 16 74AC109 16 5 3
74AC00 2 VCC 6 14 VCC 10
J Q J Q
3 7 13 9
K Q K Q MC74VHC1G66
4 12
CLK CLK
v

1 15
CLR CLR
5 8 11 8
PRE GND PRE GND

U9A 5VDIG 5VDIG

74AC00 C16 C17
0.1μF 0.1μF
5VDIG 5VDIG
5VDIG
74AC74 74AC86
U6 U7 C18
74HC163AD 74HC163AD 5VDIG PRE Q
0.1μF
1 16 1 16 D
RESET VCC RESET VCC CLK
v

2 15 2 15 U10
CLK RCO CLK RCO CLR Q
3 14 3 14 LTC1799
P0 Q0 P0 Q0
4 13 4 13 100k 1 + 5
P1 Q1 P1 Q1 V OUT 5VDIG
5 12 5 12 2
P2 Q2 P2 Q2 GND
6 11 6 11 3 4 74AC74
P3 Q3 P3 Q3 SET DIV
7 10 7 10
ENP ENT ENP ENT PRE Q
8 9 8 9
GND LO GND LO D
CLK
v

U13C
74AC32 CLR Q

CLK
18645 AI2
U13B
74AC32

Figure 6. LTC1864 Manchester Transmitter

18645fb

18
 LTC1864/LTC1865
APPLICATIONS INFORMATION

VCC VCC VCC IC3A

IC2B IC4B 74AC74
IC2A 74AC74
IC6D 74AC08 4 5
IC5C IC4A 74AC74 10 9 PRE Q
VCC IC1A VCC 74AC32 PRE Q 2
74AC86 74AC08 4 5 12 D
74AC74 PRE Q D CLK 3
2 CLK 11 CLK

v
4 5 D CLK 1 6

v
PRE Q CLK 3 13 8 CLR Q
DATA IN 2 CLK CLR Q

v
D 1 6
CLK 3 10 9 CLR Q
CLK PRE Q
v

1 6 12
CLR Q D
CLK 11
CLK IC6C
v

13 8
CLR Q DATA 74LS32D
DATA
IC1B
74AC74

VCC IC3B
IC4D 74AC74
74AC08 IC4C
74AC08 10 PRE Q 9 STROBE
12 D
CLK 11
CLK

v
13 8
CLR Q

RECEIVE CLOCK AT IC8

8 X TRANSMIT 74AC595
CLOCK FREQUENCY 14 15
SER QA D15
1
11 QB D14
2
U1 SCK QC D13
VCC 3
LTC1485 10 QD D12
4
VCC SCL QE D11
1 8 5
RO VCC 12 QF D10
2 7 6
RE RCK QG D9

v
B
3 6 7
DE A 13 QH D8
4 5 9
DI GND 8 QHIN
OPTIONAL SERIAL TO
PARALLEL CONVERTER VCC IC9
15V SUPPLY TO 74AC595
TRANSMITTER 14 15
SER QA D7
1
11 QB D6
2
STROBE SCK QC D5
3
10 QD D4
IC7B 4
SCL QE D3
4 CONDUCTOR 74AC109 5
R1 12 QF D2
TELEPHONE WIRES 11 6
120Ω PRE Q 10 RCK QG D1
v
TO TRANSMITTER 14 7
J 13 QH D0
12 9
CLK 8 QHIN
v

13
DATA K
15 9
CLR Q

18645 AI3

Figure 7. LTC1864 Manchester Receiver

18645fb

19
LTC1864/LTC1865
APPLICATIONS INFORMATION
Transmit LTC1864 Data Over Modular Telephone Wire
Using Simple Transmitter/Receiver
Figure 6 shows a simple Manchester encoder and dif-
ferential transmitter suitable for use with the LTC1864.
This circuit allows transmission of data over inexpensive
telephone wire. This is useful for measuring a remote
sensor, particularly when the cost of preserving the analog
signal over a long distance is high.
Manchester encoding is a clock signal that is modulated
by exclusive ORing with the data signal. The resulting
signal contains both clock and data information and has
an average duty cycle of 50%, that also allows transformer
coupling. In practice, generating a Manchester encoded
signal with an XOR gate will often produce glitches due
to the skew between data and clock transitions. The D
flip-flops in this encoder retime the clock and data such
that the respective edges are closely aligned, effectively
suppressing glitches. The retimed data and clock are then
XORed to produce the Manchester encoded data, which
is interfaced to telephone wire with an LTC1485 RS485
transceiver.
In order to synchronize to incoming data, the receiver
needs a sequence to indicate the start of a data word. The
transmitter schematic shows logic that will produce 31
20
zeros, a start bit, followed by the 16 data bits (one sample
every 48 clock cycles) at a clock frequency of 1MHz set by
the LTC1799 oscillator. Sending at least 18 zeros before
each start bit ensures that if synchronization is lost, the
receiver can resynchronize to a start bit under all condi-
tions. The serial to parallel converter shown in Figure 7
requires 18 zeros to avoid triggering on data bits.
The Manchester receiver shown in Figure 7 was adopted
from Xilinx application note 17-30 and would typically be
implemented in an FPGA. The decoder clock frequency is
nominally 8 times the transmit clock frequency and is very
tolerant of frequency errors. The outputs of the decoder
are data and a strobe that indicates a valid data bit. The
data can be deserialized using shift registers as shown.
The start bit resets the J-K/flip-flop on its way into the
first shift register. When it appears at the QHIN output of
the second shift register, it sets the flip-flop that loads the
parallel data into the output register.
With AC family CMOS logic at 5V the receiver clock fre-
quency is limited to 20MHz; the corresponding transmitter
clock frequency is 2.5MHz. If the receiver is implemented
in an FPGA that can be clocked at 160MHz, the LTC1864
can be clocked at its rated clock frequency of 20MHz.
18645fb
 LTC1864/LTC1865
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)

3.00 ± 0.102
0.889 ± 0.127 (.118 ± .004) 0.52
(.035 ± .005) (.206)
(NOTE 3) 8 7 6 5
REF

5.23
(.206) 3.2 – 3.45 3.00 ± 0.102
4.88 ± 0.1
MIN (.126 – .136) DETAIL “A” (.118 ± .004)
0.254 (.192 ± .004)
NOTE 4
(.010)
0° – 6° TYP

0.42 ± 0.04 0.65 GAUGE PLANE

(.0165 ± .0015) (.0256) 1 2 3 4
TYP BSC 0.53 ± 0.015
(.021 ± .006) 1.10 0.86
RECOMMENDED SOLDER PAD LAYOUT (.043) (.034)
DETAIL “A” MAX REF
0.18
(.077)
SEATING
PLANE 0.22 – 0.38 0.13 ± 0.05
(.009 – .015) (.005 ± .002)
0.65 MSOP (MS8) 1001
(.0256)
NOTE:
BCS
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

18645fb

21
LTC1864/LTC1865
PACKAGE DESCRIPTION
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)

3.00 ± 0.102
0.889 ± 0.127 (.118 ± .004) 0.497 ± 0.076
(.035 ± .005) (NOTE 3) (.0196 ± .003)
10 9 8 7 6
REF

5.23
3.2 – 3.45 4.88 ± 0.10 3.00 ± 0.102
(.206)
MIN (.126 – .136) DETAIL “A” (.118 ± .004)
0.254 (.192 ± .004)
NOTE 4
(.010)
0° – 6° TYP

0.305 ± 0.038 0.50 GAUGE PLANE

(.0120 ± .0015) (.0197) 1 2 3 4 5
TYP BSC 0.53 ± 0.01
RECOMMENDED SOLDER PAD LAYOUT (.021 ± .006) 1.10 0.86
(.043) (.034)
DETAIL “A” REF
MAX
0.18
(.007)
SEATING
PLANE 0.17 – 0.27
NOTE: 0.13 ± 0.05
1. DIMENSIONS IN MILLIMETER/(INCH) (.007 – .011) (.005 ± .002)
0.50
2. DRAWING NOT TO SCALE MSOP (MS) 1001
(.0197)
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
TYP
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

18645fb

22
 LTC1864/LTC1865
PACKAGE DESCRIPTION
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)

0.189 – 0.197*
(4.801 – 5.004)
8 7 6 5

0.228 – 0.244 0.150 – 0.157**

(5.791 – 6.197) (3.810 – 3.988)

SO8 1298

1 2 3 4

0.010 – 0.020
× 45° 0.053 – 0.069
(0.254 – 0.508)
(1.346 – 1.752)
0.004 – 0.010
0.008 – 0.010
0°– 8° TYP (0.101 – 0.254)
(0.203 – 0.254)

0.016 – 0.050
0.014 – 0.019 0.050
(0.406 – 1.270)
(0.355 – 0.483) (1.270)
TYP BSC
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

18645fb

23
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC1864/LTC1865
TYPICAL APPLICATION
Sample Two Channels Simultaneously with a Single Input ADC 4096 Point FFT of Output
0
5V f1 = 7.507324kHz AT 530mVP-P
10
0.1μF f2 = 45.007324kHz AT 1.7VP-P
f1 20 fS = 100kHz
(0V TO 0.66V) + 4.096V 0.1μF 1μF 30
1/2 100Ω
REF 40

AMPLITUDE (dB)
LT1492
4.096V 50
– 100pF
60
REF 5k 0.1μF 1μF
20k 70
28.7k 8 1 80
5pF VCC REF 7
10k 2 90
SCK
IN+ 6 100
10k 1μF LTC1864 SDO 110
5V IN– 5 120
5k
3 CONV
GND 130
0.1μF 0 5 10 15 20 25 30 35 40 45 50
f2 0.1μF 4
8
(0V TO 2V) + FREQUENCY (kHz)
100Ω
1/2 18645 TA03b
LT1492
– 4 100pF

18645 TA03a

RELATED PARTS
PART NUMBER SAMPLE RATE POWER DISSIPATION DESCRIPTION
14-Bit Serial I/O ADCs
LTC1417 400ksps 20mW 16-Pin SSOP, Unipolar or Bipolar, Reference, 5V or ±5V
LTC1418 200ksps 15mW Serial/Parallel I/O, Internal Reference, 5V or ±5V
16-Bit Serial I/O ADCs
LTC1609 200ksps 65mW Configurable Bipolar or Unipolar Input Ranges, 5V
References
LT1460 Micropower Precision Series Reference Bandgap, 130μA Supply Current, 10ppm/°C, Available in SOT-23
LT1790 Micropower Low Dropout Reference 60μA Supply Current, 10ppm/°C, SOT-23
Op Amps
LT1468/LT1469 Single/Dual 90MHz, 16-Bit Accurate Op Amps 22V/μs Slew Rate, 75μV/125μV Offset
LT1806/LT1807 Single/Dual 325MHz Low Noise Op Amps 140V/μs Slew Rate, 3.5nV/√Hz Noise, –80dBc Distortion
LT1809/LT1810 Single/Dual 180MHz Low Distortion Op Amps 350V/μs Slew Rate, –90dBc Distortion at 5MHz

18645fb

24 Linear Technology Corporation

LT 1207 REV B • PRINTED IN USA

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