15. 15.4 Table 15-1 ATmega328PB INT- Interrupts This section describes the specifies of the interupt handling of the device. For a general explanation of the AVR interrupt handling, refer to the description of Reset and Interrupt Handling. In general + Each Interrupt Vector occupies two instruction words for + The Reset Vector is affected by the BOOTRST fuse, and the Interrupt Vector start address is affected by the IVSEL bitin MCUCR. Related Links Reset and Interrupt Handling Interrupt Vectors in ATmega328PB, Reset and Interrupt Vectors in ATmega328PB a 1 2 13 14 18 16 7 18 19 20 a 2 x0000 RESET Extemal Pin, Power-on Reset, Brown-out Reset and Watchdog System Reset ‘ox0002 INTO Extemal interrupt Request 0 ‘x0004 INT Extemal interrupt Request 0 x0008 PoINTO Pin Change interrupt Request 0 ‘x0008 POINT Pin Change Interrupt Request 1 ‘x0008 POINT2 Pin Change interrupt Request 2 x000¢ wor Watchdog Time-out Interrupt 0000 TIMER2_COMPA TimeriCounter2 Compare Match A ‘x0010 TIMER2_COMPB |TimeriCoutner2 Compare Match 8 ‘oxoot2 TIMER2_OVF _ Timer/Gounter2 Overiow oxo014 TIMER1_CAPT _|Timer/Countert Capture Event 00018 TIMER1_COMPA TimeriCountert Compare Match A oxoo18 TIMER1_COMPB TimeriCoutnert Compare Match B ox001A TIMER1_OVF _Timer/Gountert Overiow ox001¢ TIMERO_COMPA | Timer/CounterO Compare Match A Ox001€ TIMERO_COMPB TimeriCoutner0 Compare Match 8 x0020 TIMERO_OVF —_Timer/CounterO Overiow x0022 sPi0 STC SPI1 Serial Transfer Complete ox0024 USARTO_RX | USARTO Rx Complete 00028 USARTO_UDRE | USARTO, Data Register Emply x0028 USARTO_TX | USARTO, Tx Complete x0028 ‘ape ‘ADC Conversion Complete © 2017 Microchip Technology ne Datasheet Complete ~49001806Apage 78ATmega328PB By 25 26 27 28 29 30 3t 32 33 34 35 36 37 38 39 40 a 2 43 “4 45 15.2 15.2.1 18.2.2 0026 EEREADY EEPROM Ready 0002 ‘ANALOG COMP Analog Comparator ‘0x0030 T™ 2ewire Serial Interface (/2C x0032 SPMREADY Store Program Memory Ready ox0084 USARTO_START | USARTO Stat frame detection (00038 POINTS Pin Change Interrupt Request 3 x0038 USARTI_RX | USARTO Rx Complete (x003A USARTI_UDRE USARTO, Data Register Empty ox003¢ USART1_TX | USARTO, Tx Complete (0003 USART1_START USARTI Stat frame detection ‘x0040 TIMERS_CAPT | Timer/Counter3 Capture Event x0042 TIMER3_COMPA TimeriCounter8 Compare Match A ox0044 TIMER3_COMPB |TimeriCoutner3 Compare Match B 0x0046 TIMERS_OVF _Timer/Gounter3 Overiow ox0048 crD Clock fallure detection interrupt ox004A PTCEOC PTC End of Conversion ox004¢ PTC_WCOMP | PTC Window comparator mode 0x004E SPI_STC SPI Serial Transfer Complete x0050 Twit TWH Transfer complete ‘ox0052 TIMER4 CAPT Timer/CounterS Capture Event ox0054 TIMER4_COMPA TimeriCounter3 Compare Match A (0x0056 TIMER4_COMPB TimeriCoutner3 Compare Match B x0058 TIMER4_OVF _Timer/Counter3 Overiow Register Description Moving Interrupts Between Application and Boot Space ‘The MCU Control Register controls the placement of the Interrupt Vector table. MCU Control Register ‘The MCU Control Register controls the placement of the Interrupt Vector table in order to move interrupts between application and boot space. ‘When addressing /O Registers as data space using LD and ST instructions, the provided offset must be used. When using the /O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an VO address offset within 0x00 - Ox3F. ‘The device is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in Opcode for the IN and OUT instructions, For the Extended VO space from 0x60 in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. © 2017 Microchip Technology ne Datasheet Complete “20001908A-page 74