• Design a 4 bit BCD to Excess-3 code converter and obtain its logic

diagram
• From the truth table, the minterms are obtained for each
outputs(E3, E2, E1, E0).
• E3 = ∑m(5, 6, 7, 8, 9),
• E2 = ∑m(1, 2, 3, 4, 9),
• E1 = ∑m(0, 3, 4, 7, 8),
• E0 = ∑m(0, 2, 4, 6, 8,)
The minterms of each output in plotted in k-map and simplified
expression is obtained.
Multiplexers
MUX types
• 2-to-1 (1 selection line)
• 4-to-1 (2 selection line)
• 8-to-1 (3 selection line)
• 16-to-1 (4 selection line)
module m21(Y, D0, D1, S);

output Y;

input D0, D1, S;

wire T1, T2, Sbar;

and (T1, D1, S), (T2, D0, Sbar);

not (Sbar, S);

or (Y, T1, T2);

endmodule
module m21(D0, D1, S, Y);

output Y;

input D0, D1, S;

assign Y=(S)?D1:D0;

endmodule
VIT UNIVERSITY 15
8 :1 Multiplexers

16
VIT UNIVERSITY 17
 Multiplexer IC Package

▪ Some IC packages have a few multiplexers in each package. The

selection and enable inputs are common to all multiplexers within
the package.
A0
Y0
A1
Y1
A2
Y2
A3
Y3
B0
B1
B2
Quadruple 2:1 multiplexer
B3
S
(select)
E'
(enable)
 Larger Multiplexers

▪ Larger multiplexers can be constructed from smaller ones.

▪ An 8-to-1 multiplexer can be constructed from smaller
multiplexers like this (note placement of selector lines):
I0
I1 I0 When
4:1 S2S1S0 =
I2 MUX
I3 000 I
0
2:1
S1 S0 MUX Y
I4
I5 4:1 I4
I6 MUX S2
I7
S1 S0
 Larger Multiplexers

▪ Another implementation of an 8-to-1 multiplexer using

smaller multiplexers:
I 0
I0 2:1 When
I1 MUX S2S1S0 =
I2 000
I2 2:1 S0
I3 MUX
4:1 I0
S0 I4 MUX Y
I4 2:1
I5 MUX
S2 S1
S0 I6 2:1 I6
I7 MUX
Q: Can we use only 2:1 multiplexers?
S0
 Larger Multiplexers

▪ A 16-to-1 multiplexer
can be constructed from
five 4-to-1 multiplexers:
 Problem: Construct a 16x1 multiplexer with two
8x1 and one 2x1 multiplexers. Use block diagrams
De-multiplexer
1:2 demux
1:8 Demux
1:16 demux
Encoder

• An encoder is a combinational circuit that converts binary

information in the form of a 2N input lines into N output lines,
which represent N bit code for the input. For simple encoders, it is
assumed that only one input line is active at a time
Encoder:
• It is a combinational logic circuits that converts an active input signal
into a coded output signal.
• It has n input lines, only one of which is active at any time
• It has m output lines, the number of outputs is less than the number of
inputs.

n inputs Encoder m outputs

17-09-2022 36
4 to 2 line Encoder

D0 D2
X X
D1 4:2 D3
D2 Encoder
Y
D3
Y
D1

X = D2 + D3
Y = D1 + D3
Verilog Code for 4- 2 Encoder:
// a 4-to-2 Encoder using Data Flow Modeling
// a 4-to-2 Encoder using Behavior Level Modeling
module encoder_4to2(x, y);
module encoder_4to2(x, y); input [3:0] x;
input [3:0] x; output reg [1:0] y;
output reg [1:0] y;
assign A= x[2] + x[3];
// the body of the 4-to-2 Encoder assign B = x[1] + x[3];
always @ (x)
begin endmodule
case (x)
4'b0001 : y = 2'b00;
4'b0010 : y = 2'b01; // a 4-to-2 Encoder using Structured Modeling
4'b0100 : y = 2'b10;
module encoder_4to2(x, y);
4'b1000 : y = 2'b11;
input [3:0] x;
endcase
output reg [1:0] y;
end
or(y[0], x[2],x[3]);
endmodule
or(y[1], x[1],x[3]);
endmodule
Test Bench for 4-2 Encoder:

// Test Bench for 4-to-2 Encoder

module encoder_4to2_Test;
reg [3:0] x;
wire [1:0] y;

encoder_4to2 E1(x, y);

initial
begin
x= 0;
# 5 x = 4'b0001;
#5 x = 4'b0010;
#5 x = 4'b0100;
#5 x = 4'b1000;
end

endmodule
X= D4 + D5 + D6 + D7
Y= D2 + D3 + D6 + D7
Z= D1 + D3 + D5 + D7
Verilog Code for 8- 3 Encoder:
// a 8-to-3 Encoder using Behavior Level Modeling
module encoder_8to3(x, y);
input [7:0] x;
output reg [2:0] y;
// the body of the 8-to-3 Encoder
always @ (x)
begin
case (x)
8'h01 : y = 3'b000;
8'h02 : y = 3'b001;
8'h04 : y = 3'b010;
8'h08 : y = 3'b011;
8'h10 : y = 3'b100;
8'h20 : y = 3'b101;
8'h40 : y = 3'b110;
8'h80 : y = 3'b111;
default:y = 3'bxxx;
endcase
end
endmodule
// a 8-to-3 Encoder using Data Flow Modeling
module encoder_8to3(x, y);
input [7:0] x;
output reg [2:0] y;
assign A= x[4] + x[5]+x[6]+x[7];
assign B = x[2] + x[3]+x[6]+x[7];
assign C = x[1] + x[3]+x[5]+x[7];
endmodule
// a 4-to-2 Encoder using Structured Modeling
module encoder_8to3(x, y);
input [7:0] x;
output reg [2:0] y;
or(y[0], x[4],x[5],x[6],x[7]);
or(y[1], x[2],x[3],x[6],x[7]);
or(y[1], x[1],x[3],x[5],x[7]);
endmodule
Test Bench for 8-3 Encoder:

// Test Bench for 8-to-3 Encoder

module encoder_8to3_Test;
reg [7:0] x;
wire [2:0] y;

encoder_8to3 E1(x, y);

initial
begin
x= 8’h00;
# 5 x= 8'h01;
# 5 x= 8'h02;
# 5 x= 8'h04;
# 5 x= 8'h08;
# 5 x= 8'h10;
# 5 x= 8'h20;
# 5 x= 8'h40;
# 5 x= 8'h80;
end

endmodule
Types of Encoder:

Decimal to BCD Encoder

Octal to Binary Encoder (8 to 3 Encoder)

Hexa decimal to Binary Encoder

Priority Encoder
Decimal to BCD Encoder:
Decimal to BCD Encoder:
Truth Table:
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A B C D
0 0 0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 0 0 0 0 1 0 0 0 0 1 0
0 0 0 0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 0 1 0 0 0 0 0 1 0 0
0 0 0 0 1 0 0 0 0 0 0 1 0 1
0 0 0 1 0 0 0 0 0 0 0 1 1 0
0 0 1 0 0 0 0 0 0 0 0 1 1 1
0 1 0 0 0 0 0 0 0 0 1 0 0 0
1 0 0 0 0 0 0 0 0 0 1 0 0 1
Decimal to BCD Encoder:
Drawbacks of Encoder:
 D0-bit skipped during encoding operation.

 If more than one input bit activated at once. Encoder will

not produce accurate output.
Priority Encoder:
• If 2 or more inputs are equal to 1 at the same time, the input has the
highest priority will take precedence.
• Two outputs for four input priority encoder
• There is third output said to be valid (V)bit indicator.
• It is set to 1 when one or more inputs are equal to 1.
• If all the inputs are 0, there is no valid input. V=0
• When V=0, other two outputs are not inspected consider as don’t
care

17-09-2022 48
4 to 2 Priority Encoder:

Where,
V  Valid Bit

V = 0; all inputs are “logic-0”.

Ignore values of A, B.

V = 1; any one or more inputs

are “logic-1”. Consider values
of A, B.
Priority Order
D3 > D2 > D1 > D0
Solve k-map for Valid (V)
Applications of Encoder:

 Keypad Interface with

Controller:
Keypad Interface with Controller through 8 to 3 Encoder ( 8 to 3
Priority Encoder):
Decoder
• A decoder is a combinational circuit that converts binary information
from n input lines to a maximum of 2" unique output lines

• The name decoderis also used in conjunction with some code converters
such as a BCD-to-seven segment decoder
Verilog Code for 2 - 4 Decoder:

// a 2-to-4 decoder with active-high output

// Test Bench for 2-to-4 Decoder
module decoder_2to4_high(x,enable,y);
module decoder_2to4_Test;
input [1:0] x;
reg [1:0] x;
input enable;
wire [3:0] y;
output reg [3:0] y;
decoder_2to4_high d1(x, y);
// the body of the 2-to-4 decoder
initial
always @ (x or enable)
begin
x= 0;
if (!enable) y = 4'b0000;
# 5 x = 2'b00;
#5 x = 2'b01;
else
#5 x = 2'b10;
case (x)
#5 x = 2'b11;
2'b00 : y = 4'b0001;
end
2'b01 : y = 4'b0010;
2'b10 : y = 4'b0100;
endmodule
2'b11 : y = 4'b1000;
default : y = 4'b0000;
endcase

endmodule
Verilog Code for 3- 8 Decoder:
// a 3-to-8 decoder with active-high output
module decoder_3to8_high(x,enable,y); // Test Bench for 3-to-8 Decoder
input [2:0] x; module decoder_3to8_Test;
input enable; reg [2:0] x;
output reg [7:0] y; wire [7:0] y;
// the body of the 3-to-8 decoder
always @ (x or enable) decoder_3to8_high d1(x, y);
initial
if (!enable) y = 8'h00; begin
x= 0;
else # 5 x = 3'b000;
case (x) #5 x = 3'b001;
3'b000 : y = 8'h01; #5 x = 3'b010;
3'b001 : y = 8'h02; #5 x = 3'b011;
3'b010 : y = 8'h04; # 5 x = 3'b100;
3'b011 : y = 8'h08; #5 x = 3'b101;
3'b100 : y = 8'h10; #5 x = 3'b110;
3'b101 : y = 8'h20; #5 x = 3'b111;
3'b110 : y = 8'h40;
3'b111 : y = 8'h80; end
endcase endmodule
endmodule
4:16 decoder
Implement the boolean expression F(A, B, C) = ∑ m(2, 3, 6, 7) using a
multiplexer.
Implement the boolean expression F(A, B, C) = ∑ m(0, 1, 3, 5, 7) using a
multiplexer.
• If the two minterms in a column are not circled, apply 0 to the
corresponding multiplexer input.
• If the two min terms are circled, apply 1 to the corresponding multiplexer
input.
• If the bottom minterm is circled and the top is not circled, apply A to the
corresponding multiplexer input.
• If the top minterm is circled and the bottom is not circled, apply A' to the
corresponding multiplexer input.
Implement the boolean expression F(A, B, C) = ∑ m(0, 2, 5, 6) using 4 : 1 multiplexer.
Implement F(A, B, C, D) = ∑ m(0, 1, 5, 6, 8, 10, 12, 15) using 8 : 1 multiplexer.
Implement a full-adder circuit with a decoder and two OR gates.
S(x, y, z) = Σ(1, 2, 4, 7)
C(x, y, z) = Σ(3, 5, 6, 7)
Example-01:
Implement Full Adder using 4x1 MUX

Sol:
Truth Table – Full Adder
Full Adder using 4x1 MUX:
4x1 MUX for Sum:
K-Map for Sum:

Truth Table for Sum using 4x1 MUX:

S1 = A S0 = B Sum (S)

0 0 I0 = Ci
0 1 I1 = Ci’
1 0 I2 = Ci’
1 1 I3 = Ci
Full Adder using 4x1 MUX:
K-Map for Carry(C0): 4x1 MUX for Carry:

Truth Table for Carry using 4x1 MUX:

S1 = A S0 = B Sum (S)

0 0 I0 = 0

0 1 I1 = Ci
1 0 I2 = Ci
1 1 I3 = 1
Example-02:
Obtain Logical Expression from 4x1 MUX
Truth Table:
A B Y1

0 0 I0 = C
0 1 I1 = C
1 0 I2 = 1
1 1 I3 = 0

Boolean Expression:
Example-03:
Implement Logic Gates using 2x1 MUX

1) NOT Gate using 2x1 MUX:

Truth Table:
A Y

0 d0

1 d1

Note:
 In given Data, Assign LSB for Select Lines & MSB for Input Data Lines
2) AND Gate using 2x1 MUX:

Y = A’ D0 + A D1
Truth Table:
3) OR Gate using 2x1 MUX:

Boolean Expression:
Y = A’ D0 + A D1
 Implementation table

Apply variables B and C to the select lines. The procedures for implementing the function
are:
i. List the input of the multiplexer
ii. List under them all the minterms in two rows as shown below.
The first half of the minterms is associated with A’ and the second half with A. The given
function is implemented by encircling the minterms of the function and applying the
following rules to find the values for the inputs of the multiplexer.
1. If both the minterms in the column are not circled, apply 0 to the corresponding
input.
2. If both the minterms in the column are circled, apply 1 to the corresponding input.
3. If the bottom minterm is circled and the top is not circled, apply A to the input.
4. If the top minterm is circled and the bottom is not circled, apply A’ to the input.
 Example-4
Implement the following Boolean function using 8:1 multiplexer.
F( P, Q, R, S)= ∑m (0, 1, 3, 4, 8, 9, 15)
 Example-5

Implement the Boolean function using 8:1 multiplexer

F (A, B, C, D) = ∏m (0, 3, 5, 8, 9, 10, 12, 14)

 IMPLEMENTATION OF BOOLEAN FUNCTION USING DEMUX

Example-6: Implement the following Boolean function using 8:1 mux.

• F (A, B, C) = ∑m (1, 3, 5, 6).

Example:7 Implement full subtractor using
demultiplexer
Example:8
4x16 decoder using two 3x8 decoders
Implement 7-Segment Display using 4 to 16 Decoder

Sol:
Numbers display on 7-Segment Display: 7-Segment display:
7-Segment Display Decoder:
Truth Table for 7-Segment Display Decoder:
Obtain Simplified Boolean Expression for 7-Segment Decoder outputs by using K-Map:
Simplified Boolean Expression for 7-Segment Decoder outputs by using K-Map:

g = b3+b1b0’+b2’b1+b2b1’