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Voltage Divider Bias
Voltage Divider Bias
ENGI 242
ELEC 222
BJT Biasing 3
For the Voltage Divider Bias Configurations
• Draw Equivalent Input circuit
• Draw Equivalent Output circuit
• Write necessary KVL and KCL Equations
• Determine the Quiescent Operating Point
– Graphical Solution using Load lines
– Computational Analysis
• Design and test design using a computer simulation
VB - VBE
IE =
RE
Determining VTH
⎛ R2 ⎞
VTH = VCC ⎜ ⎟
⎝ R1 + R2 ⎠
Determining RTH
R1 R2
RTH =
R1 + R2
RTH
-VTH + IE + VBE + IE RE = 0
β+1
Solving for IE we obtain:
VTH - VBE
IE =
RTH
+ RE
β+1
Collector-Emitter Loop
or
VC = VCE + IE RE
CE Amplifier Design
• Design a Common Emitter Amplifier with Voltage Divider
Bias for the following parameters:
VCC = 24V
IC = 5mA
VE = .1VCC
VC = .55VCC
β = 135
CE Amplifier Design
ENGI 242
ELEC 222
BJT Biasing 4
For the Collector Feedback Bias Configuration:
• Draw Equivalent Input circuit
• Draw Equivalent Output circuit
• Write necessary KVL and KCL Equations
• Determine the Quiescent Operating Point
– Graphical Solution using Loadlines
– Computational Analysis
• Design and test design using a computer simulation
Another way to improve the stability of a bias circuit is to add a feedback path
from collector to base
In this bias circuit the Q-point is only slightly dependent on the transistor β
23 February 2005 ENGI 242/ELEC 222 23
Network Example
Network Example
⎛ R2 ⎞
VTH1 = VCC ⎜ ⎟
⎝ R1 + R2 ⎠
(Note VEE is negative)
⎛ R1 ⎞
VTH2 = - VEE ⎜ ⎟
⎝ R1 + R2 ⎠
VTH = VTH1 + VTH2
⎛ R2 ⎞ ⎛ R1 ⎞
VTH = VCC ⎜ ⎟ - VEE ⎜ ⎟
⎝ R1 + R2 ⎠ ⎝ R1 + R2 ⎠
R1 R2
RTH =
R1 + R2
PSpice Simulation