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Microprocessor (IS5C01) Module 1
Microprocessor (IS5C01) Module 1
Microprocessor (IS5C01) Module 1
By
B N KIRAN
Assistant Professor
Department of Information Science and
Engineering
NIE, Mysuru – 570 008
Introduction
• Mechanical Age
– 500BC rotors, Abacus Babylonians, geared mechanical
machines,
– Charles Babbage Difference engine
• Electrical age 1800
– Electric motor, Transistors, IC’s
• Microprocessor age 4004, 8008, 8080, 8085, 8086,
8088, 80186, 80286, 80386, 80486, (80x86), 80586
(Pentium, Pentium pro), celeron, HT processors, dual
core processors, core2 duo, Xeon, Atom, movidious,
quark, core i1, i3, i5, i7, i9 processors
Suffix Meaning
K Unlocked
S Special edition
T Power-optimized lifestyle
U Mobile power efficient
Y Mobile extremely low power
• Computer Languages
– COBOL, ADA, Pascal, C, C++ Etc
• Companies
• Texas Instruments, Intel, AMD, Philips,
Motorola
List of processor manufacturing
companies
16EnSilica
• 1Altera 17Fairchild Semiconductor
• 2AMD 18Freescale Semiconductor
• 3Apollo (formerly Motorola)
• 4ARM 19Fujitsu
• 5Atmel 20Garrett AiResearch
• 6AT&T 21Google
22Harris Semiconductor
• 7Bell Labs
23Hewlett-Packard
• 8BLX IC Design Corporation 24Hitachi
• 9Centaur Technology/IDT 25Inmos
• 10Cyrix 26IBM
• 11Data General 26.1POWER
• 12Digital Equipment Corporation 26.2PowerPC-AS
• 13Emotion Engine by Sony & Toshiba 26.3z/Architecture
• 14Elbrus 27Intel
• 15Electronic Arrays 28Intersil
29ISRO
30Lattice Semiconductor
List of processor manufacturing
companies contd...
• 31MIPS Technologies
• 32MOS Technology 46Western Design
• 33National Semiconductor Center
• 34NEC 47Western Digital
• 35NVIDIA 48Western Electric
• 36NXP (formerly Philips Semiconductors) 49Xilinx
• 37OpenCores 50XMOS
• 38Oracle Corporation (formerly Sun Microsystems) 51Zilog
• 39RCA
• 40Renesas Electronics
• 41RISC-V Foundation
• 42Sunway
• 43Texas Instruments
• 44Toshiba
• 45VIA
Block diagram of MP based systems
ISA
EISA
PCA
Memory division
Memory map of TPA in PC
System area of a typical PC
Block diagram of a computer showing
control, data and address bus
8086 (1978)
• 20-bit address bus : 1M byte(1024Kbytes) memory
• Instruction : over 20,000 variation
– 4004 : 45, 8085 : 246
• A separate BIU and EU
– Fetch and Execute instruction simultaneously
• 16-bit Internal processor registers
– With the ability to access the high and low 8 bits separately
if desired
• Hardware multiply and divide built in
• Support for an external math coprocessor
– Perform floating-point math operations as much as 100
times faster than the processor alone via software emulation
Chapter 1 Introduction to the
13
Microprocessor and Computer
Chapter 1 Introduction to the
16
Microprocessor and Computer
The EFLAG and FLAG register counts for the entire 8086 and Pentium microprocessor family.
(*) For the LARGE model, the largest arrays size can not exceed 64 KB.(br)
(**)For the HUGE model, an array may have a size greater than 64 KB and
hence can span more than one physical segment.
• TINY Model:
– In the TINY model both code and data occupy one
physical segment. Therefore, all procedures and
variables are by default addressed as NEAR, by
pointing at their offsets in the segment.
On assembling and linking a source file, the tiny
model automatically generates a com file, which is
smaller in size than an exe file.
• SMALL Model:
– In the SMALL model all code is placed in one
physical segment and all data in another physical
segment. In this model, all procedures and
variables are addressed as NEAR by pointing to
their offsets only.
• COMPACT Model:
– In the COMPACT model, all elements of code (e.g.
procedures) are placed into one physical segment.
However, each element of data can be placed by
default into its own physical segment. Consequently,
data elements are addressed by pointing both at the
segment and offset addresses.
– In this model, all code elements (procedures) are
addressed as NEAR and data elements (variables) are
addressed as FAR.
• MEDIUM Model:
– The MEDIUM model is the opposite of the compact
model. In this model data elements are treated as
NEAR and code elements are addressed as FAR.
• LARGE Model:
– In the LARGE model both code elements (procedures)
and data elements (variables) are put in different
physical segments. Procedures and variables are
addressed as FAR by pointing at both the segment and
offset addresses that contain those elements.
However, no data array can have a size that exceeds
one physical segment (i.e. 64 KB).
• HUGE Model:
– The HUGE memory is similar to the LARGE model with
the exception that a data array may have a size that
exceeds one physical segment (i.e. 64 KB).
Use of memory models
• The amount of data that has to be manipulated and
code that needs to be written are the major factors in
determining the choice of an appropriate model. The
following are guidelines to help chose the right model
for a program.
• For a small fast program that operates on small
quantities of data, the SMALL or TINY models are the
most suitable ones. These models allow up to 64K of
memory (i.e. one single physical segment), but the
executable code is fast since only near references are
used in the calculation of addresses.
The only difference between these two models is that
the TINY model generates a .COM module in which far
references cannot be used, whereas the SMALL model
generates a .exe module.