CSE1003

DIGITAL LOGIC AND DESIGN

LAB ASSIGNMENT 2

SUBMITTED TO:
RAJESH KUMAR V
 Minterm A B C D W X Y Z
s
m0 0 0 0 0 0 0 1 1
m1 0 0 0 1 0 1 0 0
m2 0 0 1 0 0 1 0 1
m3 0 0 1 1 0 1 1 0
m4 0 1 0 0 0 1 1 1
m5 0 1 0 1 1 0 0 0
m6 0 1 1 0 1 0 0 1
m7 0 1 1 1 1 0 1 0
m8 1 0 0 0 1 0 1 1
m9 1 0 0 1 1 1 0 0

BCD to Excess 3 code

Truth Table:

Circuit Diagram:
Verification:

Output w

i)w=A+BC+BD
K-map

Result:
ii) Output x

x=B’C+B’D+BC’D’
K-map:

Result:
iii) Output y

y=C’D’+CD
k-MAP

Result:
IV)Output Z

Z=D’
K-map:

Result:

Inference:
The output Obtained for BCD to excess 3 code by stimulation using LTspice matches with the truth
Table.

BCD to 2421 code convertor

Truth table:

Minterm A B C D w x y z
s
m0 0 0 0 0 0 0 0 0
m1 0 0 0 1 0 0 0 1
m2 0 0 1 0 0 0 1 0
m3 0 0 1 1 0 0 1 1
m4 0 1 0 0 0 1 0 0
m5 0 1 0 1 0 1 0 1
m6 0 1 1 0 0 1 1 0
m7 0 1 1 1 0 1 1 1
m8 1 0 0 0 1 1 1 0
m9 1 0 0 1 1 1 1 1

Circuit Diagram:
Verification:

I)Output w(2421)
W=A
K-map:
Result:

Output X(2421)
X=A+B
K-map:
Result:

Output Y(2421):
Y=A+C
K-map:
Result:

Output Z :(2421)
Z=D
K-map:

Result:

Inference:
The output Obtained for BCD to 2421 code by stimulation using LTspice matches with the truth Table.
SOP FORM OF THE OUTPUTS :

1. w=A
2. x=A+B
3. y=A+C
4. z=D

Implementation using NAND Gates:

1.) Circuit Diagram:

Result:

POS FORM :
a) w = A
b) x = (A+B+C+D).(A+B+C+D’).(A+B+C’+D’).(A+B+C’+D)
c) y = (A+B+C+D).(A+B+C+D’).(A+B’+C+D).(A+B’+C+D’)
d) z = D
IMPLEMENTATION USING NOR GATES :

1. Circuit Diagram
Result:

Inference:
The output Obtained for BCD to 2421 code by stimulation using LTspice by implementing in SOP form
and POS form matches with the truth Table.