ISSCC2020-SC-1 Device and Physical Design Considerations For Circuits in FinFET Technology Alvin Loke

ISSCC 2020 Short Course
Device and Physical Design Considerations for

Circuits in FinFET Technology
Alvin Loke
TSMC
aloke@tsmc.com
February 20, 2020
1 of 80
Semiconductor Drivers
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1960 1970 1980 1990 2000 2010 2020 2030
Hou, TSMC [1] / Wikipedia [2]
Alvin Loke ISSCC 2020 Short Course 2 of 80
Moore’s Law – Scaling for Density Reduces Cost
Dennard Scaling Strain+HKMG FinFET+DTCO

10M
Inverter
1M
SRAM
Relative Density
100k
Logic gates
10k
Transistors
1k (microprocessors)
100
µm
µm
µm
90 µm
10
m
m
µm
65 m
nm
32 m
nm
nm
nm
7n m
5µ
0µ
8µ
6µ
35
25
18
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m
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m
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3µ
5n
10
45
22
14
10
1.
1.
0.
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1
1970 1980 1990 2000 2010 2020
Wong, TSMC [3] / Cai, TSMC [4]
Outline
o Road to FinFET
o Technology Scaling Enablers
o Design Realities
o Design Strategies
o What’s Ahead
o Conclusion

Outline
o Road to FinFET
n Dennard Scaling (Lgate, tOX, N, xj, VDD Scaling)
n Extending Dennard Scaling – Mechanical Strain & HKMG
n Fully Depleted Device
o Design Realities
o Design Strategies
o What’s Ahead
o Conclusion

Short-Channel Effects (SCEs)
o Area scaling à smaller Contacted Gate Pitch (CGP) à smaller Lgate
o Scaling Lgate weakens gate control of body depletion & channel formation
n More S/D junction control of body depletion à VT rolloff
n VDS increases drain-side depletion à drain-induced barrier lowering (DIBL)
CGP
Lgate contact
VT VT
gate
DIBL
source drain
body (well) Lgate VDS

Dennard Scaling Recipe for SCE Reduction
re is no Original Device Scaled Device

atively (Factor of a)
types
at the
wever,
e gated
on the
re very
re also 1
𝑋" ∝
nough 𝑁&
activeFig. 1. Schematic illustrationillustration
Fig. 1. Schematic of the scaling of Si
of the technology
scaling by aet al., IBMby
of Dennard
Si technology [5] a
/ Frank et al., IBM [6]
factor
oint of alpha. Adapted from [5].
Alvin Loke factor alpha. Adapted from [5]. ISSCC 2020 Short Course 7 of 80
ust the
Not Bad for 3 Decades of Scaling
o 10+ nodes: 10µm to 0.13µm
o ~100x reduction in Lgate & tOX gate
spacer
o Innovations along the way
S/D
n Optimized body doping profile for extension
short-channel control halo poly
o Lateral halo implants for higher gate
local doping under gate edge
o Vertical retrograded well with S/D
STI
shallow surface VT implant retrograded well
n Gate spacers to enable self-aligned
halo, S/D extension & S/D
o Shallow junction with extension
o Short extension to reduce Rext
STI = Shallow Trench Isolation
Temporary Roadblocks to Further Dennard Scaling
o Higher body doping
n Worse channel mobility µ from dopant
scattering Igate
o Thinner physical tOX
n Severe tunneling leakage through nitrided
oxide (SiON) gate dielectric
n Poly-Si depletion from high gate resistivity
& channel quantum confinement limits
further effective (electrical) tOX scaling poly
depletion
o Innovations
n Channel strain
n High-K (HK) Gate Dielectric & Metal Gate (MG)
Wong, IBM [7]

Mechanical Strain for Mobility Boost
o Straining channel lattice by 1% o Works for short channel only,
can increase µ (reduce carrier m*) not effective for long channel
by several times o Techniques
o Surround channel with several GPa n Stress memorization
stress (steel breaks at 0.8GPa) n SiGe & SiC/SiP source/drain
o Increase Ion for same Ioff & COX n Contact dielectric stress layers
o NMOS & PMOS want opposite n Strained gate & contact
stress; desired stress is anisotropic
tension à faster NMOS compression à faster PMOS
Chan et al., IBM [8]

High-K Gate Dielectric & Metal Gate (HKMG)
o Extends COX or EOT scaling N metal P metal
n Thicker HfO2 HK gate dielectric à less Igate fill fill
n More conductive MG work function (ΦM) layer HK ΦMN ΦMP
& even more conductive metal fill
à less gate depletion
o VT set by body implant or gate ΦM (VFB)
adjustment (MG composition, HK dipole)
o Lots of integration challenges
n Replacement metal gate (RMG) for stable VT NMOS PMOS
with thermally delicate HK-MG interface
n Silicide-last (silicide after contact etch) to silicide in
accommodate HK post-deposition anneal trench contact
EOT = Equivalent Oxide Thickness
VFB = flatband voltage Hou, TSMC [1] / Loke, Qualcomm [9] / Kang et al., SEMATECH [10]
Road Closed to Further Scaling
o Subthreshold FET is a BJT with base (ϕs) controlled by COX vs. (CB+CD)
o Higher body doping & Lgate scaling à higher CB & CD
o Higher subthreshold swing (mV/decade) incongruent with VT & VDD scaling
o More performance with further Lgate scaling comes with high leakage cost
VGS gate DIBL
gate control
(what we want)
COX VDS
ϕs drain body
source source effect
CB CD
VGS drain
VDS
body VBS |VBS|

Turning to Fully Depleted
o Surface dopants not fundamental to field-effect action, just provide mirror
charge to establish dipole & electric field for inducing surface inversion
o Use heavy doping under undoped surface (extremely retrograded well) to
terminate fields from gate à like parallel-plate capacitor
o Undoped body becomes fully depleted without undoped
ionized dopant charge to offer body
o Fewer dopants à less scattering à higher µ gate surface
o Variation sensitive to geometry, not RDF
o Fully depleted options
n Planar on bulk source drain
n Planar on SOI (FD-SOI)
n 3-D on bulk (finFET) “bottom plate”
n 3-D on SOI
Yan et al., Bell Labs [11] /
RDF = Random Dopant Fluctuation Fujita et al., Fujitsu [12] / Cheng et al., IBM [13] /
Enabling Disruptive VT and VDD Scaling
VGS log (ID) log (ID)

gate IDsat IDsat
COX SS IDlin SS IDlin

VDS
ϕs drain
source Ioff Ioff
CB CD
DIBL DIBL
body VBS VGS VGS
VTsat VTlin VDD VTsat VTlin VDD
o Fully depleted device reduces CB & CD à less SS, DIBL & body effect
o VT & VDD scaling for lower power at given Ion & Ioff

Less DIBL for Better Analog AND Digital
IDsat grossly underestimates

VGS
IHI (no-DIBL) IDsat CV/I switching delay à use Ieff
VDD
Ieff = ILO + IHI
Drain Current, ID
Ieff (no-DIBL) 2
IHI
ILO @ VGS=½VDD, VDS=VDD
Ieff ILO
½VDD IHI @ VGS=VDD, VDS=½VDD
inverter
switching
trajectory Less DIBL
½VDD VDD à higher Ieff & rout for same IDsat
Drain Voltage, VDS
Na et al., IBM [14] / Wei et al., Stanford [15]
Outline
o Road to FinFET
n FinFET
n Lithography & Self-Aligned Patterning
n Mechanical Stressors & HKMG for FinFET
n Middle-End-Of-Line (MEOL) & Self-Aligned Contacts
n Other Design/Technology Co-Optimization (DTCO) Innovations
o Design Realities
o Design Strategies
o What’s Ahead
o Conclusion

Planar FET à Tri-Gate FinFET
channel fully depleted body

n+ drain
n+ drain
gate p-well p-well
tie NMOS n+ source tie
n+source
STI STI
p-well p-well
p-substrate p-substrate
p+ drain
p+ drain
n-well n-well
tie PMOS p+ source
tie
p+ source
n-well n-well
p-substrate p-substrate
STI = Shallow Trench Isolation Huang et al., UC Berkeley [16]
Characteristics of Fully Depleted Tri-Gate FinFET
o More Ion & gm per area – Weff ~ 3-4x fin pitch
fully o Quantized channel width
depleted n Challenge for SRAM & logic
body n Not big issue for analog with low gm per fin
drain well tie
o Less DIBL à higher rout & intrinsic gain
o Negligible body effect (ΔVT < 10mV)
o Fully depleted à less RDF mismatch
source
STI o Parasitics
well n High S/D resistance & coupling to gate
n Fin width ≪ fin pitch à low Cj, high Rwell
p-substrate
o 1/f noise comparable to much worse
o Device self-heating à reliability concerns
Hsueh et al., TSMC [17] / Loke et al., Qualcomm [18]

Analog/Mixed-Signal (AMS) Dashboard
1.2x 1.2x 5x
planar finFET planar finFET o Lower power
1.0x
1.0x 4x o Lower leakage
0.8x rout
Vmax 3x o Better switch
0.8x 0.6x
o Higher intrinsic gain
0.4x 2x gm
Vnom o Better mismatch
0.6x Ioff 1x
0.2x
planar finFET o Smaller area
0.4x 0.0x 0x
28nm 16nm 7nm 28nm 16nm 7nm 28nm 16nm 7nm
1.2x 1.2x 1.2x
o Overall a good PPA
planar finFET planar finFET (power, performance,
1.0x
1.0x 1.0x area) story to first
VT 0.8x mismatch order
0.8x 0.6x 0.8x o Benefits saturate after
0.4x Ron first migration to
0.6x 0.6x
0.2x finFET
planar finFET
0.4x 0.0x 0.4x
28nm 16nm 7nm 28nm 16nm 7nm 28nm 16nm 7nm Loh, Mediatek [19]
Foundry Pitch Scaling
40 28 20 16/14 10 7nm o Incremental physical scaling
200 rate slower than 0.7x per node
Minimum Pitch (nm)
gate o Node name tied to area scaling,

100 metal
80
no longer Lgate scaling
60 o 13.5nm Extreme Ultra-Violet
193i single
(EUV) only started in production
40 exposure limit
fin at 7nm
o Process complexity & cost for
20 0.7x sub-80nm pitch without EUV
per 2 years
2008 2010 2012 2014 2016 2018 2020

Yang, Qualcomm [20] / Wu et al., TSMC [21] / Wu et al., TSMC [22]
Lithography Innovations
Pitch Splitting Orthogonal Cutting
o Interleave two or more exposures o Extra mask(s) to break line patterns
o Mask color decomposition & balance o Reduced end-to-end spacing
o Limited by overlay between masks o Limited by cut mask overlay
cut mask
pattern
Mask
A
Mask
B
Arnold et al., ASML [23] Wikipedia [24]

Spacer-Based Self-Aligned (SA) Patterning
o Pattern fins, short-channel gates, MEOL & lower BEOL (Back-End-Of-Line)
o Results in sea of spacers with single feature width
o Conformal spacer à correlated line edge roughness à less width variation
sacrificial
mandrel Spacer 1 SADP
Spacer 2 SAQP
top
view
mandrel = shape for forming sidewall spacers Choi et al., UC Berkeley [25]
Variations of Spacer-Based Patterning
Spacer Trim Mask SADP/SAQP + Block Mask
o Extra mask to trim spacers for o Extra mask to bridge spacers prior to
extra feature width prior to etch etch for more flexible metal space
o Example: Lmin & Lmin+Δ gates o Adjust mandrel width/space for more
trim mask flexible metal width/space
block mask
Lmin+Δ Lmin
Loke et al., Qualcomm [18] Lazzarino et al., imec [26]

Extreme Ultra-Violet (EUV) Lithography
o Entry in 7nm production o Many 193i masks (pitch-split,
n High source power & sensitive SADP/SAQP, cut & block masks)
resist for high throughput à one EUV mask
n 13.5nm λ à reflective mask/optics n Process simplicity, fewer defects
reflective n Simpler OPC & DRC, better overlay
mask n Reduced cycle time à cost saving
reflective
illuminator Five 193i masks
One EUV mask
optics (mirrors)
reflective
EUV source projection
optics (mirrors)
wafer
Chang et al., NTU [27] Yeap et al., TSMC [28]

Mechanical Stressors for FinFET
o Induce channel strain along L with
surrounding stressors
n Tensile for NMOS & compressive for PMOS
but reality very complicated with 3D
n (110) sidewall vs. (100) top NMOS
n Limited options: S/D fin recess & epitaxy
n Limited stressor volume with CGP scaling
o Much more effective for PMOS, β ratio à 1
o Much less effective for longer Lgate
o µ depends on OD length, width & space
n Layout-Dependent Effects (LDEs)
PMOS
n Pre/post-layout simulation gap
OD = Oxide Definition (active area) Loke et al., Qualcomm [18] / Faricelli, AMD [29]
HKMG for FinFET
o Implant-based VT tuning not
feasible beyond 14nm due to S/D
gate cap HKMG gate
small fin volume (RDF) trench over fin spacer
contact
n VT tuning with MG
composition & HK dipole
o MG layer(s) very resistive
n Effective gate ΦM influenced
by metal fill composition &
thickness
silicide fins with S/D
o High Rgate in short Lgate only at metal fill epitaxial fill
o High S/D resistance with bottom ΦM metal
silicide last of contact HK dielectric
RDF = Random Dopant Fluctuation

Complex Middle-End-Of-Line (MEOL)
o Tight CGP à tough to land diffusion & gate contacts without shorts
o Dielectric caps protect gate & contact to prevent gate-to-diffusion shorts
à self-aligned diffusion contacts (SACs) & self-aligned gate contacts
o More via & contact interfaces from metal to FET à higher FET access resistance
metal contact metal

dielectric
diffusion gate cap self-aligned self-aligned
contact contact S/D via gate contact
gate
gate dielectric self-
cap aligned
contact
CGP = Contacted Gate Pitch Yang, Qualcomm [20]

Self-Aligned Gate Contact for Reduced Cell Height
o Land gate contact directly on top of gate, not gate overhang
o Less space between OD rows à shorter standard cell height
o Reduces Rgate à less non-quasistatic (NQS) effect
gate contact self-aligned

S/D contact on overhang gate contact
S/D via
Yeap et al., TSMC [28]

Gate-Cut Last for Reduced Cell Height
o Gate conventionally cut prior to RMG module
o Sidewall HK & ΦM metal at gate ends requires more gate overhang
o Cut gate after RMG to eliminate sidewall HKMG à reduce overhang
sidewall reduced
N metal fill gate cut P metal fill
HKMG fin-to-fin spacing
ΦMN metal ΦMP metal
HK
gate reduced
overhang overhang
gate cut before RMG module gate cut after RMG module
Greene et al., IBM [30]
Single vs. Double Diffusion Break
o Dummy gates terminate OD to constrain S/D epitaxy
o SDB eliminates dummy gate waste à saves 10–20% logic area
o Aggressive isolation in SDB à process/model risk, stress LDE
dummy
gates DDB SDB
OD = Oxide Definition (active area) Yang et al., Qualcomm [31]

Fin Depopulation for Higher Logic Density
o Fin depopulation can increase speed & power efficiency
o More fins à highest speed at highest power
o Less fins à highest speed for given power, lowest power for given speed
4-fin cell 3-fin cell 2-fin cell
Power
Lu, TSMC [32] Frequency
Outline
o Road to FinFET
o Design Realities
n Analog/Mixed-Signal Device Palette
n Parasitics & Layout-Dependent Effects (LDEs)
n Layout Considerations
n Design Concurrent with Technology Development
o Design Strategies
o What’s Ahead
o Conclusion

Stacked FET for Higher rout
o Maximum Lgate limited by gate litho/etch loading & HKMG CMP
o Short Lgate has most µ boost à may use less area with fewer fingers
o More process & DRC friendly than long Lgate
o Intermediate diffusions degrade HF rout (gain, CMRR, …)
1.2
DC iac HF iac 240nm
Normalized rout
1.0
0.8
0.6
0.4
Lmin stack
0.2
0.0
0.01 0.10 1.00 10.00
Normalized Frequency
CMP = Chemical-Mechanical Polishing Loke et al., Qualcomm [18]

Thick-Oxide I/O FET
o General-Purpose I/Os still use 1.8V swing
despite reduced core VDD
n Talk to peripheral ICs made in lower cost nodes
o Challenging to keep 1.8V I/O devices
n Tighter fin pitch à tough gate fill
n Complex level shifters to handle larger ΔVDD
n Many links stopped supporting legacy modes to
enable higher data rate & lower power
n Better power & area with thinner I/O oxide, e.g., 1.2V
n Challenging with nanowire or nanosheet integration
o System impact
n Chipset (SoC) / chiplet (SiP) partitioning tighter fin pitch
n More options with more system ownership
Resistors
MEOL Thin Film Precision Resistor Metal Gate Resistor
o HKMG à poly resistor obsolete o Available for free
o Low temperature coefficient o Small area but higher variation
o Ends not well defined à current spreading from gate density & limited Wmax
o Decouples resistor integration from FEOL o Higher temperature coefficient
o Variation limits area scaling o Coupled to HKMG stack VT tuning
o Not scaling from node to node
metal fill
ΦM metal
Loke et al., Qualcomm [18] HK dielectric
Capacitors
MOM (Metal-Oxide-Metal) Planar MIM (Metal-Insulator-Metal)
o Pitch scaling à higher cap density o Primarily for supply decoupling
o Reduced AC coupling efficiency o Typically near top of BEOL stack
(i.e., more capacitive attenuation) o Extra process cost
from worse parasitic to AC ground o Contacted from top or via sidewall
o Beware of dielectric TDDB reliability o High plate ESR à bandwidth limitation
dictating minimum metal space
TDDB = Time-Dependent Dielectric Breakdown ESR = Equivalent Series Resistance

Varactors & Inductors
Accumulation-Mode Varactor Inductor
o Fully depleted à steeper C-V transition o Use low-Rsheet thick upper Cu
o Tougher circuit biasing to use narrower layer & Al RDL
high-slope region o Upper BEOL almost unchanged
Cgg node-to-node à no area scaling
o More restrictive dummy fill rules
finFET o Use much smaller active
n+ n+ inductors where noise & low Q
planar can be tolerated
n-well desired
p-substrate R
VG
Chang et al., Xilinx [33]

Diodes & PNP-BJTs
o Ubiquitous in ESD, bandgap references & thermal sensors
o High Rwell à high diode/BJT series resistance
o Stricter well tie density, guard ring & latch-up rules
o Current limited by junction area à limited node-to-node scaling
emitter base collector Ideality higher

p+ n+ p+ Factor, η series
RD
usable
Io/N & Io
range
Rwell
n-well p-well
1
p-substrate
Loke et al., Qualcomm [22]
log(ID)
Outline
o Road to FinFET
o Design Realities
n Analog/Mixed-Signal Device Palette
n Questions?
n Parasitics & Layout-Dependent Effects (LDEs)
n Layout Considerations
n Design Concurrent with Technology Development
o Design Strategies
o What’s Ahead
o Conclusion

Interconnect Resistance
o Resistance is arguably the defining
agony of finFET era design Cu
n High-ρ Cu barrier liner 75 2.0
Mx Capacitance (vs. 40nm)

Mx Resistance (vs. 40nm)
not scaling
1.8
n Very high R in MEOL & 60
lower BEOL 1.6
n C-only post-layout sims 45
virtually useless 1.4
o FET performance greatly 30
1.2
compromised by source
15
degeneration 1.0
n Every mV of source-side
0 0.8
IR drop matters given 40nm 28nm 16nm 7nm 5nm
aggressive VDD scaling
Hou, TSMC [1]
Gate Resistance
o Rgate increases with Lgate scaling
Rgate
o Distributed RC (NQS effect) has
increasing impact on FET delay
gate
o Rgate has complex horizontal & drain contact
vertical components
gate
o Mitigation
source
n Fewer fins
n Double-sided gate contact
n Self-aligned gate contacts
Wu and Chan, HKUST [34]

Gate-to-Contact Capacitance
o S/D epi & SAC form vertical plate capacitors with gate sidewall
o Worse noise coupling in many analog circuits (2 examples below)
n Adding capacitance increases area & wake-up time (burst-mode)
Worse PSRR in Kickback noise

SAC LDO regulator in LPDDR RX
Vref Vbias CGS
CGD
Vout Vin Vref
epi
Vout
SAC = Self-Aligned (diffusion) Contact Loke et al., Qualcomm [18]

Flicker (1/f) Noise
o Noise ratio (16nm finFET vs. 20nm planar) is par to much worse
o Depends on device type
n NMOS vs. PMOS, VT type, core vs. I/O, Lgate & frequency
o Very bias-dependent à even higher ratios at low gate overdrive
o Cumbersome but not showstopper à overcome with circuit topology
Device Type Noise Ratio (FinFET:Planar)

Lgate Oxide NMOS PMOS
Minimum Core 1.1x 6.8x
72nm Core 2.4x 25.7x
200nm I/O 3.8x 9.7x
Chang et al., Xilinx [35]

Stress LDEs
o Stronger FET stressors & interaction with surrounding STI/ILD
o Stronger layout effects à more pre/post-layout simulation gap
o Well-established stress LDEs from planar nodes
Length of OD
OD Gate
Width Oxide Pitch
Space
Faricelli, AMD [29] / Garcia Bardon et al., imec [36] / Bianchi et al., STMicroelectronics [37]
Gate-Cut Stress LDE (New in FinFET Nodes)
o Gate cut disrupts mechanical support of continuous gate
o Modulate stress near cut à Δµ & ΔVT
gate no gate cut with gate cut

cut impacted
device
fins
gate
compressive tensile
Yang et al., Qualcomm [31]
HKMG LDEs
Metal Boundary Effect Density Gradient Effect
o ΔVT near border of different ΦM o Gate density gradients à ΔVT &
o Interdiffusion of ΦM variation from RMG CMP dishing
o Mitigated with gate cut o Gate ΦM influenced by metal fill &
sidewall ΦM metal
PMOS ΦM1 ΦM metal

fins gate metal fill
NMOS ΦM2
fins gate
Hamaguchi et al., Toshiba [38] Yang et al., Qualcomm [39]

Electrical Chip-Package Interaction
o FET mobility sensitive to stress from die attach to package
o More PMOS than NMOS sensitivity, single gate orientation
o Package stress can impact long-range device matching
(e.g., I/O impedance, bias references, data converters)
0% +10%
-2% +8%
-4% +6%
-6% +4%
-8% +2%
-10% 0%
Terzioglu, Qualcomm [40]
Layout Density & Floorplan Considerations
o 1000s of DRCs, many very tough to pass, always getting more
restrictive & foreign à layout should resemble logic arrays
o Density checks to reduce long-range pattern variation
à iterative rework of smaller cells
n Area, perimeter, gradient ADPLL partial floorplan
n Contacts, vias, cuts, tight-pitch metal
n Larger checking windows Synthesized Digital
n Density union of multiple metal levels Transition
Decoupling
o Floorplanning more tedious & bloated Capacitance Custom
Digital
n More dummy gates, well taps, guard rings Transition
n Transitions between different device types AMS AMS
& pattern densities

The Fuss about Uniform Pattern Density
o Critical process steps are extremely sensitive to pattern density,
especially at nanoscale geometries
n DRCs constrain range of pattern density variation to limit extent of
systematic & random process variation
o What the fab wants

n Consistent pattern density at
every layer
n Regular logic/SRAM gate array
snapped to regular MEOL &
BEOL grid
n Short-channel core FETs
(fab’s priority)

Pattern Density – Chemical Mechanical Polishing
o Pattern-dependent 10
topography caused by 90nm Metal-1
Line Space (µm)

8
n Metal dishing
n Dielectric erosion 6
o Uncontrolled topography 4
leads to higher level shorts
2
0
0 2 4 6 8 10
Line Width (µm)
Normalized Sheet Resistance
0.8 0.9 1.0 1.1 1.2

Loke & Wee, Agilent [42]
Pattern Density – Rapid Thermal Annealing
o Active area & gate density impacts surface heat absorption & anneal
temperature uniformity
o Non-uniform anneal à non-uniform dopant activation à device variation
o Major source of systematic across-chip variation
Poly sheet resistance before and after density optimization

Before After
Wei et al., U Minnesota [43]

Pattern Density – Deposition & Etch Microloading
o Pattern density modulates deposition rate, etch rate & CD
Spacer width Etch depth

modulated by modulated by
deposition loading etch loading
CD = Critical Dimension Belyansky, IBM [44]

Bleeding-Edge Product Development
o Design concurrently developed with technology to shorten product
time-to-market à initial models are target-based
o Multiple models & design iterations à earlier design start & finish
Model Uncertainty
Test Chip
Speculative Silicon-Influenced Silicon-Based

Models Models Models
Initial Updated Final

Design Design Design
Time
Bair, AMD [45]
FET Modeling for Analog vs. Digital
o Technology & modeling prioritized 1.5
28nm example VGS
to logic & SRAM core FETs IDsat
VDD=1.0V
o Lower priority for long-channel & IHI 1.0V
1.0
I/O devices
I (mA)
Ieff
o Device targeting & model 0.7V
D
0.5
correlation at limited number of ILO
0.5V
I-V & C-V points IDlin Ioff
0.0
o Analog also needs accurate slope 0.0 0.2 0.4 0.6 0.8 1.0
modeling (gm, gds) which gets VDS (V)
some attention but not priority typical analog biasing
VGS = VT to VT + 0.1V
McAndrew et al., Freescale [46]
Process Corner Model Limitations
o Corners are digital-centric
PMOS Parameter (e.g., Ieff)

n Don’t necessarily correlate to
AMS worst-case corners FF
o Systematic within-die process SF
SFG FFG
gradients typically not modeled
o Within-die random variation typically TT
captures side-by-side local mismatch
n Not distance-dependent FSG
SSG
o AMS model quality only as good as FS
SS
fab understanding of design usage
NMOS Parameter (e.g., Ieff)

Pre/Post-Layout Simulation Gaps
o Accept more iterations in each new node – that’s just life!
o Sources of Δ
n Layout-extracted vs. default schematic LDE parameters
n Layout-extracted interconnect parasitics (especially in MEOL) not
anticipated in pre-layout netlist
o Estimated parasitics typically included in pre-layout netlist
n S/D contact resistance (big help!)
n Gate resistance
n Gate-to-contact capacitance
o Making pre-layout netlist more layout aware to reduce gap
n Back-annotate key parasitics into schematic
n Specify FET schematic options that estimates LDE & parasitic

Recap of Bleeding-Edge AMS Challenges
Speculative device
DRC updates
model updates
R & C parasitics Strict layout

(FET, MEOL, BEOL) DESIGN density rules
ITERATIONS
Layout-Dependent Strict ESD &
Effects latch-up rules
Lower I/O FET

Limited area scaling
voltage
Leary, Qualcomm [47]

Outline
o Road to FinFET
o Design Realities
o Design Strategies
n Pattern Density, Parasitics & LDEs
n Target-Based Model Uncertainty
n Analog Cells
o What’s Ahead
o Conclusion

Avoid Mixing Short- & Long-Channel FETs
o Short Lgate patterned by SADP;
long Lgate with conventional 2nd
mask
o SADP prone to litho, deposition
& etch loading
o Consistent Lgate is more
SADP- & CMP-friendly preferred
o Mixed Lgate prone to DGE
o Example: current mirror
with enable devices

Mitigation of MEOL Resistance
o Challenging for high-current circuits, e.g., I/O drivers, clock buffers
o Examples of resistance mitigation (despite higher C)
n Double-source layout halves S/D Rcontact
n Extend SAC to land extra diffusion via
extra
short extended S/D via
together SAC
gate
fin
diffusion
contact (SAC)

Mitigation of BEOL Resistance – Via Pillar
o Lower BEOL DPT layers & vias are very resistive
o Be careful to not block routing tracks with unnecessary via pillars
Connection through Layer promotion to Via pillar
DPT layer non-DPT layer
standard 20µm wire

cell
DPT wire resistance Source via resistance Best combination of

dominates increases metal & source via
resistance
DPT = Double-Patterning Technology Hou, TSMC [1]
Thermal Sensor with RD Cancellation
N+1 identical Io ηkT
ΔVBE,M = q ln M + (M-1) Io RD
Io partitioned into
1, M & N ηkT
ΔVBE,N = q ln N + (N-1) Io RD
ADC
RD
ηkT (N-1)ΔVBE,M – (M-1)ΔVBE,N
=
q (N-1) ln M – (M-1) ln N
o Measure ΔVBE at M:1 & N:1 à eliminate RD

o Dynamic Element Matching (DEM) à cancel Io mismatch
o Swap amp inputs à cancel diode mismatch
ON Semiconductor [48]
Continuous OD for Performance & Matching
o Build up stress plateau
for higher µ
µ variation in constant µ in
o Desensitize FET from µ short OD continuous OD
variation in short OD OD
stress
o Most critical for short (µ)
Lgate with strongest LDE
o Pay area tax of dummy
gates in each OD
o Matched FETs also need
dummy stress dummy
matched spacing to gates plateau for gates
surrounding devices active gates
OD = Oxide Definition (active area) Loke et al., Qualcomm [18]

Avoid Resistors
o Precision resistor area not scaling à more costly in each new node
o Resistorless topologies
n LPDDR4 TX controlled-impedance driver (example below)
n Less CML, more CMOS
Lu et al., TSMC [49]

Bandgap Reference – Epitome of Resilience
o Not aging gracefully but won’t die
n High PNP/diode resistance
à smaller diode ratio & higher Io Io AIo
variation sensitivity
n High VD from high well doping
à higher VDD for headroom
n Output variation dominated
by PMOS mirror mismatch
à trimming? DEM? N
n OTA mismatch à offset cancellation

n PNP & resistor area not scaling
o Is there a better way?
Banba et al., Toshiba [50]
Self-Heating Mitigation
o Concerns
n Device performance & reliability (HCI, BTI, gate dielectric TDDB)
n MEOL & BEOL reliability (electromigration, interconnect TDDB)
o Heat sink mitigation simulated
n Funnel heat to stacked vias & well taps temperature
n Fewer fins (narrower OD) better than rise profile
fewer fingers (shorter OD)
n Insert dummies
r
ge
in
nf
FET well tap FET nfin
Liu et al., TSMC [51]
Dealing with Target-Based Uncertainty
o Process at tapeout more immature in each new node
n More masks & longer fab cycle time à fewer cycles of silicon learning
(EUV provides some relief)
o Process development areas, even after tapeout
n HKMG stack & RMG optimization to tune multiple VT
n S/D epitaxy, MEOL modules (contacts, vias & metal)
n Logic & SRAM area-saving constructs (SDB, S/D jumper)
o Most vulnerable (unstable) model parameters
n FET VT, µ, LDEs
n Long L & I/O FETs not top priority
n RC parasitics in S/D & MEOL

Template-Based Analog Cells for Productivity
o Technology aware for fast design closure
o Layout considerations
n Incorporate process-friendly layout guidelines
n Anticipate density concerns
n Short-channel stack to emulate long-channel FET
n Pre-defined routing tracks
n Include MEOL & lower BEOL for easier assembly
o Schematic considerations for reduced
pre/post-layout simulation gap
n Anticipate LDEs with continuous OD placement
(e.g., SA/SB override)
n Disable Rcontact in stacked FET
n Back-annotate MEOL & BEOL parasitic estimates

Outline
o Road to FinFET
o Design Realities
o Design Strategies
o What’s Ahead
n FinFET Improvements
n Beyond the FinFET
o Conclusion

FinFET Improvements
o Really tough after 4 generations of finFET
n Realistically, never been any low hanging fruit with each new node
n Process innovations & complexity required for only incremental gain
o Areas of development
n Short-channel control à narrower fins, tradeoff vs. µ reduction
n Channel mobility à high µ fin material, e.g., TSMC 5nm
n EOT à higher K, thinner & reliable gate dielectrics
n Device variation à fin uniformity & geometry control
n Rcontact à contact resistivity (interface quality) & area
n Rgate à selective bottom-up HKMG deposition
n CGS & CGD à gate spacer K
n MEOL & BEOL resistance à metal resistivity, Rvia
Cai, TSMC [4] / Yeap et al., TSMC [28]
Migrating to Gate-All-Around
o FinFET has poor short-channel control with further Lgate scaling
o Need better short-channel control & more Weff per die area
o Gate-all-around (GAA) nanowires & nanosheets are promising
FinFET Nanowire Nanosheet
stacked
nanosheet
demonstration
Cai, TSMC [4] / Loubet et al., IBM [52]

FinFET à Nanosheet
FinFET Nanosheet
Y cut X cut
W
PMOS W
H
S/D S/D
NMOS X cut inner spacer
Y cut current mostly flows

Gate Contact along (100) surface
Silicon Metal
Cai, TSMC [4]

2D & 1D Materials for Even Shorter Gate Control
o Geometry scaling requires thinner channels for shorter Lgate
o Mobility falls rapidly in very thin Si channels from surface scattering
o Intense R&D on naturally thin, atomically smooth 2D & 1D materials
2D TMD (MoS2, WSe2, WS2…)
10,000
Mobility (cm2/V-s)
CNT
1,000 WSe2 < 1 nm
WS2 Si
100 TMD = Transition Metal Dichalcogenide
MoS2
Ge 1D carbon nanotube (CNT)
10
1
0 1 2 3 4
Channel thickness (nm)
Wong, TSMC [3] / Su et al., TSMC [53] / Radisavljevic et al., EPFL [54] / Ströck [55]

Conclusion
o “Moore’s Law is well and alive, it’s not even sick” [3]
o Area scaling now driven primarily by device innovation & DTCO,
less by feature size reduction
o Design success all about understanding & exploiting technology
o Scaling prioritizes logic & memory, not friendly to classic analog
o Digital-friendly AMS design inspires new performance, power &
integration, but implementation needs a lot more perspiration
o Economic case for new nodes increasingly challenging, motivating
traction for more heterogeneous integration
o We are at an exciting inflection point of innovation
Wong, TSMC [3]

Acknowledgments
o Jin Cai o Szu-Lin Liu

o Min Cao o Lee-Chung Lu
o Jonathan Chang o Linus Lu
o Chung-Hui Chen o Yung-Chow Peng
o Mark Chen o Dirk Pfaff
o Alan Cheng o Alan Roth
o Vincent Chou o Eric Soenen
o Emily Fan o Philip Wong
o Cliff Hou o Geoffrey Yeap
o Kenny Hsieh o Tsung-Hsin Yu

References (1/5)
[1] C. Hou, “A smart design paradigm for smart chips,” in IEEE ISSCC, Paper 1.1 Keynote, San Francisco, CA, Feb.
2017.
[2] https://en.wikipedia.org/wiki/Transistor_count
[3] H.-S. P. Wong, “IC technology – what will the next node offer us?” in HotChips, Keynote, Stanford, CA, Aug.
2019.
[4] J. Cai, “Device Technology for 3nm Node and Beyond,” in IEEE Int. Electron Devices Meeting, Short Course, San
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Circuits, vol. 9, no. 5, pp. 256–268, Oct. 1974.
[6] D.J. Frank et al., “Device scaling limits of silicon MOSFETs and their application dependencies,” Proc. IEEE, vol.
89, no. 3, pp. 259–288, Mar. 2001.
[7] H.-S. P. Wong, “Beyond the conventional transistor,” IBM J. Research & Development, vol. 2-3, no. 46, pp. 133–
168, Mar. 2002.
[8] V. Chan et al., “Strain for CMOS performance improvement,” in IEEE Custom Integrated Circuits Conf., San Jose,
CA, Sep. 2005.
[9] A. Loke, “The journey to finFETs,” in IEEE Int. Midwest Symp. Circuits and Systems, Tutorial, Fort Collins, CO,
Aug. 2015.
[10] C.Y. Kang et al., “The impact of La-doping on the reliability of low Vth high-k/metal gate nMOSFETs under various
gate stress conditions,” in IEEE Int. Electron Devices Meeting, San Francisco, CA, Dec. 2008.
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References (2/5)
[12] K. Fujita et al., “Advanced channel engineering achieving aggressive reduction of VT variation for ultra-low power
applications,” in IEEE Int. Electron Devices Meeting, San Francisco, CA, Dec. 2011.
[13] K. Cheng et al., “Fully depleted extremely thin SOI technology fabricate by a novel integration scheme featuring
implant-free, zero-silicon-loss, and faceted raised source/drain,” in IEEE Symp. VLSI Technology, Kyoto, Japan,
Jun. 2009.
[14] M. Na et al., “The effective drive current in CMOS inverters,” in IEEE Int. Electron Devices Meeting, San
Francisco, CA, Dec. 2002.
[15] L. Wei et al., “Exploration of device design space to meet circuit speed targeting 22nm and beyond,” in Int.
Conf. Solid State Devices and Materials, Miyagi, Japan, Oct. 2009.
[16] X. Huang et al., “Sub-50nm finFET: PMOS,” in IEEE Int. Electron Devices Meeting, Washington, DC, Dec. 1999.
[17] F.-L. Hsueh et al., “Analog/RF wonderland: circuit and technology co-optimization in advanced finFET
technology,” in IEEE Symp. VLSI Technology, Honolulu, HI, Jun. 2016.
[18] A. Loke et al., “Analog/mixed-signal design challenges in 7-nm CMOS and beyond,” in IEEE Custom Integrated
Circuits Conf., San Diego, CA, Apr. 2018.
[19] K.L. Loh, “FinFETs for analog & mixed-signal designs,” in IEEE ISSCC, Forum F2, San Francisco, CA, Feb. 2018.
[20] D. Yang, “SoC scaling challenges in the era of the single digit technology nodes,” in Int. Workshop Advanced
Patterning Solutions, Beijing, China, Oct. 2017.
[21] S.-Y. Wu et al., “A 16nm finFET CMOS technology for mobile SoC and computing applications,” in IEEE Int.
Electron Devices Meeting, Washington, DC, Dec. 2013.
[22] S.-Y. Wu et al., “A 7nm CMOS platform technology featuring 4th generation finFET transistors with a 0.027um2
high-density 6-T SRAM cell for mobile SoC applications,” in IEEE Int. Electron Devices Meeting, San Francisco,
CA, Dec. 2016.
References (3/5)
[23] W. Arnold et al., “Manufacturing challenges in double patterning lithography,” in IEEE Int. Symp. Semiconductor
Manufacturing, Tokyo, Japan, Sep. 2006.
[24] https://en.wikipedia.org/wiki/Multiple_patterning
[25] Y.-K. Choi et al., “A spacer patterning technology for nanoscale CMOS,” IEEE Trans. Electron Devices, vol. 49,
no. 3, pp. 436–441, Mar. 2002.
[26] F. Lazzarino et al., “Self-aligned block technology: a step toward further scaling,” in SPIE Advanced Lithography,
San Jose, CA, Apr. 2017.
[27] Y.-W. Chang et al., “EUV and e-beam manufacturability: challenges and solutions,” in ACM/EDAC/IEEE Design
Automation Conf., San Francisco, CA, Jun. 2015.
[28] G. Yeap et al., “5nm CMOS production technology platform featuring full-fledged EUV, and high mobility channel
finFETs with densest 0.021µm2 SRAM cells for mobile SoC and high performance computing applications,” in IEEE
Int. Electron Devices Meeting, San Francisco, CA, Dec. 2019.
[29] J. Faricelli, “Layout-dependent proximity effects in deep nanoscale CMOS,” in IEEE Custom Integrated Circuits
Conf., San Jose, CA, Sep. 2010.
[30] A.K. Greene et al., “Gate-cut-last in RMG to enable gate extension scaling and parasitic capacitance reduction,”
in IEEE Symp. VLSI Technology, Kyoto, Japan, Jun. 2019.
[31] S. Yang et al., “10 nm high performance mobile SoC design and technology co-developed for performance,
power, and area scaling,” in IEEE Symp. VLSI Technology, Kyoto, Japan, Jun. 2017.
[32] L.C. Lu, “Physical design challenges and innovations to meet power, speed, and area scaling trend,” in Int.
Symp. Physical Design, Keynote, Lake Oswego, OR, Mar. 2017.
[33] K. Chang et al., “Device aware high-speed transceiver design in planar and finFET technologies,” in IEEE Int.
Electron Devices Meeting, San Francisco, CA, Dec. 2014.
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[34] W. Wu and M. Chan, “Gate resistance modeling of multifin MOS devices,” IEEE Electron Device Lett., vol. 27, no.
1, pp. 68–70, Jan. 2006.
[35] K. Chang, “High-speed wireline transceivers in finFET,” in IEEE ISSCC, Forum F2, Feb. 2018.
[36] M. Garcia Bardon et al., “Layout-induced stress effects in 14nm & 10nm finFETs and their impact on
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[37] R.A. Bianchi et al., “Accurate modeling of trench isolation induced mechanical stress effects on MOSFET electrical
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[38] M. Hamaguchi et al., “New layout dependency in high-K/metal gate MOSFETs,” in IEEE Int. Electron Devices
Meeting, Washington, DC, Dec. 2011.
[39] S. Yang et al., “High-performance mobile SoC design and technology co-optimization to mitigate high-K metal
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[41] A. Loke et al., “Nanoscale CMOS implications on analog/mixed-signal design,” in IEEE Custom Integrated Circuits
Conf., Educational Session, Austin, TX, Apr. 2019.
[42] A. Loke and T.T. Wee, “Introduction to copper/low-K interconnects and electromigration fundamentals,” in IEEE
Solid-State Circuits Soc. Chapter Seminar, Fort Collins, CO, Sep. 2003.
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[45] L. Bair, “Process/product interactions in a concurrent design environment,” in IEEE Custom Integrated Circuits
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[55] https://en.wikipedia.org/wiki/File:Types_of_Carbon_Nanotubes.png

ISSCC2020-SC-1 Device and Physical Design Considerations For Circuits in FinFET Technology Alvin Loke

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ISSCC2020-SC-1 Device and Physical Design Considerations For Circuits in FinFET Technology Alvin Loke

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ISSCC 2020 Short Course

Device and Physical Design Considerations for

February 20, 2020

Dennard Scaling Strain+HKMG FinFET+DTCO

Alvin Loke ISSCC 2020 Short Course 4 of 80

Alvin Loke ISSCC 2020 Short Course 5 of 80

body (well) Lgate VDS

re is no Original Device Scaled Device

Wong, IBM [7]

tension à faster NMOS compression à faster PMOS

Chan et al., IBM [8]

Alvin Loke ISSCC 2020 Short Course 12 of 80

VGS log (ID) log (ID)

COX SS IDlin SS IDlin

Alvin Loke ISSCC 2020 Short Course 14 of 80

IDsat grossly underestimates

Alvin Loke ISSCC 2020 Short Course 16 of 80

channel fully depleted body

Hsueh et al., TSMC [17] / Loke et al., Qualcomm [18]

gate o Node name tied to area scaling,

2008 2010 2012 2014 2016 2018 2020

Arnold et al., ASML [23] Wikipedia [24]

Loke et al., Qualcomm [18] Lazzarino et al., imec [26]

Alvin Loke ISSCC 2020 Short Course 24 of 80

RDF = Random Dopant Fluctuation

metal contact metal

Alvin Loke ISSCC 2020 Short Course 27 of 80

gate contact self-aligned

Alvin Loke ISSCC 2020 Short Course 28 of 80

OD = Oxide Definition (active area) Yang et al., Qualcomm [31]

Alvin Loke ISSCC 2020 Short Course 30 of 80

4-fin cell 3-fin cell 2-fin cell

Alvin Loke ISSCC 2020 Short Course 32 of 80

Alvin Loke ISSCC 2020 Short Course 33 of 80

TDDB = Time-Dependent Dielectric Breakdown ESR = Equivalent Series Resistance

Chang et al., Xilinx [33]

Alvin Loke ISSCC 2020 Short Course 37 of 80

emitter base collector Ideality higher

Alvin Loke ISSCC 2020 Short Course 39 of 80

n High-ρ Cu barrier liner 75 2.0

Mx Capacitance (vs. 40nm)

Wu and Chan, HKUST [34]

Worse PSRR in Kickback noise

SAC = Self-Aligned (diffusion) Contact Loke et al., Qualcomm [18]

Alvin Loke ISSCC 2020 Short Course 42 of 80

Device Type Noise Ratio (FinFET:Planar)

Alvin Loke ISSCC 2020 Short Course 43 of 80

gate no gate cut with gate cut

PMOS ΦM1 ΦM metal

Hamaguchi et al., Toshiba [38] Yang et al., Qualcomm [39]

Alvin Loke ISSCC 2020 Short Course 48 of 80

o What the fab wants

Loke et al., Qualcomm [41]

Alvin Loke ISSCC 2020 Short Course 49 of 80

Line Space (µm)

Normalized Sheet Resistance

0.8 0.9 1.0 1.1 1.2

Poly sheet resistance before and after density optimization

Wei et al., U Minnesota [43]

Spacer width Etch depth

CD = Critical Dimension Belyansky, IBM [44]

Speculative Silicon-Influenced Silicon-Based