HW Assignment 1 COL215 Date: 22 th Oct.

2022

COL215 Hardware Assignment 1

4 – Digit 7 – Segment Display
Member 1: Keval Makwana (2021CS10585)
Member 2: Dev Sutariya (2021CS10793)
PROBLEM DESCRIPTION:
The assignment requires you to design the following:

1. Design a combinational circuit that takes a single 4-bit hexadecimal or decimal digit input
from the switches and produces a 7-bit output for the seven-segment display of Basys3
FPGA board.
2. Extend the design to create a timing circuit that will drive all 4-displays for displaying 4-digits
together.

SOLUTION:
 In this question we were instructed in the assignment question to build a
seven-segment decoder, a mux and a timer circuit. We have combined
all the three components in a single VHDL file named
“seven_segment.vhd” (attached).
1. Seven Segment Decoder:
 To switch an LED on, the anode should be driven HIGH and cathode
LOW. In general, LED display is activated via driving anode HIGH and
the corresponding digit via varying cathode signals. Now, if the input
number is ”0000”, then all LEDs except G should be switched ON.
Similarly, for ”0011” LEDs F and E will be OFF, and rest will be ON.

Keval & Dev |9

HW Assignment 1 COL215 Date: 22th Oct. 2022

 Note that on basys 3 board anode/cathode are ACTIVE LOW pins (i.e.,
0 = ACTIVE, 1 = INACTIVE) i.e., for whatever component we need to lit
we need to assign it the value ‘0’.
 We have made a combinational circuit for which the inputs are the
four bits of the given decimal number and outputs corresponds to
the 7 output signals.
a b c d A B C D E F G
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 x 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 X 0 1 1
1 0 1 0 1 1 1 0 1 1 0
1 0 1 1 0 0 1 1 1 1 1
1 1 0 0 1 0 0 1 1 1 0
1 1 0 1 0 1 1 1 1 0 1
1 1 1 0 1 0 1 1 1 1 1
1 1 1 1 1 0 0 0 1 1 1

 Using this truth table and the code we had written in Software
assignment 3 for finding the reduced optimal region we found out
the combinational logics (sum of minterms) for each of A, B, C, D,
E, F and G.
 This all the 7 outputs were for cathodes as shown in the figure.
 While implementing it in vivado we put a “not” in front of the
logic since assigning the value ‘0’ will turn the led on.
 For anode part, if we want to turn the first display from right, we
need to assign anode “0111” as a vector quantity, similarly for the
rest in sequence we need to assign anode “1011”, “1101” and
“1110”.
 For the combinational logic part, we have used AND, OR and NOT
only.

Keval & Dev |9

HW Assignment 1 COL215 Date: 22th Oct. 2022

2.MUX:
 We are required to create a mux taking 16 inputs and gives 4 outputs.
 We have implemented the mux using if else statements.
 We have done a slight modification in our mux implementation the mux
will take input as a vector containing 16 elements and this will return
two outputs one a vector with the required 4 bits and another a signal
for the anode.
 Code for the MUX implementation:
process (c, input)
begin
if c = "00" then
an <= "0111";
i <= input(15 downto 12);
elsif c = "01" then
an <= "1011";
i <= input(11 downto 8);
elsif c = "10" then
an <= "1101";
i <= input(7 downto 4);
elsif c = "11" then
an <= "1110";
i <= input(3 downto 0);
end if;
end process;

Here ‘c’ is the selector for the MUX.

Keval & Dev |9

HW Assignment 1 COL215 Date: 22 th Oct. 2022

3. TIMER CIRCUIT:
In the timer circuit we ran a counter with the input as the 100 MHz clock
given on the basys 3 board. We have set the frequency to 8 ms i.e., the
anode will change its value after 8 milliseconds.
Code for the timer circuit:
process (clk)
begin
if (rising_edge(clk)) then
counter <= counter + 1;
if (counter = 1200000) then ## 1200000 is equivalent to 24 ms
c <= "00";
elsif (counter = 800000) then ##equivalent to 16 ms
c <= "01";
elsif (counter = 400000) then ##equivalent to 8 ms
c <= "10";
elsif (counter = 0) then ##equivalent to 0 ms
c <= "11";
end if;
end if;

Keval & Dev |9

HW Assignment 1 COL215 Date: 22th Oct. 2022

4. Final seven_segment.vhd:
In this file we have combined all the 3 components explained above,
We have declared 4 ports (2 for input and 2 for output)for this
implementation
a. “input” a vector taking 16 bits inputs from the 16 slider switches
present on the board. Each 4 bits represent a hexadecimal digit
b. “clk”: this is the 100 MHz clock present on the basys 3 board this is
also taken as an input port.
c. “an”: this is an output for anodes. It is given out in the form of a 4 bit
vector.
d. ‘Cat’ : this is the output for cathodes. It is given in the form of a 7 bit
vector.
Running procedure of our implementation:
The counter will change the value of the selector ‘c’, as a consequence of
which the mux will tell us which display should be turned on via ‘an’ and what
should be displayed via ‘i’(just a temporary vector consisting of 4 bits of the
hexadecimal digit which will be given as an input to our combinational logic).
Using ‘i’ our combinational logic will give signal to the corresponding display
which cathode is assigned low and which one is high. Low ones will be lit
displaying an hexadecimal digit. The value of selector will change every 8 ms,
which a human eye cant sense so it looks like all the 4 displays are working
simultaneously, while actually they aren’t.

LAB WORK:
We have programmed the basys 3 board and we have checked the working of
our implementation. We have attached the pictures of the bsys 3 board with
different inputs.

Last 3 digits
of our entry numbers.
Keval & Dev |9
HW Assignment 1 COL215 Date: 22th Oct. 2022

Simulation Snapshots:
We had created a test bench with 4 inputs changing after 30 ns.

Keval & Dev |9

HW Assignment 1 COL215 Date: 22th Oct. 2022

Keval & Dev |9

HW Assignment 1 COL215 Date: 22th Oct. 2022

Synthesis Report:
The vhd file synthesizes successfully.

The implementation part also runs successfully.

Keval & Dev |9

HW Assignment 1 COL215 Date: 22th Oct. 2022

Snaps of synthesis report:

THANK YOU!!

Keval & Dev |9