The Federal Polytechnic, Bauchi

CMP 751
Digital Computer Design
1.1 Definitions
Digital has to do with system of one and zero or
binary. Computer system operates on one and
zero, one for high and zero low voltage. Because of
that any system that make use of computer system
or major components of computer are said to be
digital.
The way a computer system, which is digital is
designed is referred to as digital design.
The architecture shows the major
design concepts and strategies.
Many concepts in mathematics
and electronics are used in the
design.
This course intends to take you
into what lies beneath the laptop
or desktop you operates and three
are pre-requisites: A) Mathematics
B) Electronics, and
C) Programming
Abstraction: is a method
used in studying a complex
system that cannot be
viewed conveniently in full,
so some parts are made to
become hiding and few
components are studied.
Abstraction is used in
studying digital computer
design. The diagram beside
shows level of abstraction for digital computer
design.
Abstraction
When you are working at one level of abstraction, it is
good to know something about the levels of abstraction
immediately above and below where you are working.
For example, a computer scientist cannot fully optimize
code without understanding the architecture for which
the program is being written. A device engineer cannot
make wise trade-offs in transistor design without
understanding the circuits in which the transistors will be
used.
Discipline
Discipline is the act of intentionally restricting your design
choices so that you can work more productively at a higher
level of abstraction. . Using interchangeable parts is a
familiar application of discipline. Interchangeable parts
example is computer assembly, professional system
engineer buys the several components in the system unit,
couples them and comes up with a system unit.
Digital vs Analog Circuits
Digital circuits use discrete voltage, while
analog circuits use continuous voltage.
Analog circuits are the ancestors of their
digital counterparts, but the use of digital
ones are taken over the analog ones.
The 3 Y’s
In addition to abstraction and
discipline, designers use the three “-y’s” to
manage complexity: i. Hierarchy, ii.
Modularity, and iii. Regularity..

3 y’s to handle complexity

This aspect briefs about how well a software has the
capabilities to maintain itself in the ever-changing
environment:

• Hierarchy involves dividing a system into modules,

then further subdividing each of these modules
until the pieces are easy to understand.
• Modularity states that the modules have well-
defined functions and interfaces, so that they
connect together easily without unanticipated side
effects.

• Regularity seeks uniformity among the modules.

Common modules are reused many times, reducing
 the number of distinct modules that must be
designed.
3 y’s to handle complexity
Using the system unit assembling as example, we
examine the 3 Y’s:
• Hierarchy the assembly divides into motherboard,
auxiliary memory and front panel.
• Modularity states that motherboard should have
CPU, RAM fix, jumper settings done, Power cable
connects. Auxiliary memory to have IDE cables and
 power connect and front panel to have switch and
LEDs connect.
• Regularity seeks motherboard of same form factor
can be used irrespective of manufacturers,
auxiliary memory can be SATA or PATA as the
motherboard support and front panel has to be
software switch.

1.2 Digital Abstraction

An early digital system using variables with
ten discrete values was Charles Babbage’s
Analytical Engine. Babbage laboured from
1834 to 1871,1 designing and attempting to
build this mechanical computer.
The Analytical Engine used gears with ten
positions labelled 0 through 9, much like a
mechanical odometer in a car.
Babbage Analytical Engine
The Analytical Engine make use ten gears labelled 0
to , each row processes one digit. Babbage chose 25
rows of gears, so the machine has 25-digit precision.
Unlike Babbage’s machine, most electronic computers
use a binary (two-valued) representation in which a
high voltage indicates a '1' and a low voltage indicates
a '0', because it is easier to distinguish between two
voltages than ten. The amount of information D in a
discrete valued variable
with N distinct states is measured in units of bits as
D = log2N bits (1.1)
A binary variable conveys log22 = 1 bit of information.
Indeed, the word bit is short for binary digit. Each of
Babbage’s gears carried log210 = 3.322 bits of
information because it could be in one of 23.322 = 10
unique positions.

Boolean Logic
George Boole developed a system of
logic operating on binary variables that
is now known as Boolean logic. Each of
Boole’s variables could be TRUE or
FALSE. Electronic computers commonly
use a positive voltage to represent '1' and zero volts to
represent '0'.
The beauty of the digital abstraction is that digital
designers can focus on 1’s and 0’s, ignoring whether the
Boolean variables are physically represented with specific
voltages, rotating gears, or even hydraulic fluid levels.
Beneath the Digital Abstraction

A digital system uses discrete-valued variables. However,

the variables are represented by continuous physical
quantities such as the voltage on a wire, the position of a
gear, or the level of fluid in a cylinder. Hence, the
designer must choose a way to relate the continuous
value to the discrete value.
For example, consider representing a binary signal A with
a voltage on a wire. Let 0 volts (V) indicate A = 0 and 5 V
indicate A = 1. Any real system must tolerate some noise,
so 4.97 V probably ought to be interpreted as A = 1 as
well.

Supply Voltage

Suppose the lowest voltage in the system is 0 V, also

called ground or GND. The highest voltage in the system
 comes from the power supply and is usually called VDD.
In 1970’s and 1980’s technology, VDD was generally 5 V.
As chips have progressed to smaller transistors, VDD has
dropped to 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, or even
lower to save power and avoid overloading the
transistors.

2.1 Building Blocks

CMOS TRANSISTORS
The two main types of
transistors are bipolar junction Babbage’s Analytical Engine
transistors and metal-oxide-was built from gears, and early
semiconductor field effect
electrical computers used
transistors (MOSFETs or
MOS
relays or vacuum tubes.
transistors, pronounced
“moss-
Modern computers use fets”
or “M-O-S”,
 respectively).
transistors because they are cheap,
small, and reliable.
Transistors are electrically
controlled switches that turn ON or
OFF when a voltage or current is
applied to a control terminal.
2.2 Semiconductors
MOS transistors are built from silicon, the predominant atom in
rock and sand. Silicon (Si) is a group IV atom, so it has four
electrons in its valence shell and forms bonds with four adjacent
atoms, resulting in a crystalline lattice. By itself, silicon is a poor
conductor because all the electrons are tied up in covalent
bonds. However, it becomes a better conductor when small
amounts of impurities, called dopant atoms, are carefully added.
If a group V dopant such as arsenic (As) is added, the dopant
atoms have an extra electron that is not involved in the bonds.
The electron can easily move about the lattice, leaving an ionized
dopant atom (As+) behind. The electron carries a negative
charge, so we call arsenic an ntype dopant. On the other hand, if
a group III dopant such as boron (B) is added, the dopant atoms
are missing an electron. , the dopant atoms are missing an
electron, as shown in Figure 1.26(c). This missing electron is
called a hole. An electron from a neighbouring silicon atom may
move over to fill the missing bond, forming an ionized dopant
atom (B−) and leaving a hole at the neighbouring silicon atom. In
a similar fashion, the hole can migrate around the lattice.
Semiconductor
 Silicon Lattice and dopant atoms
2.3 Diode
The junction between ptype and
n-type silicon is called a diode. The
p-type region is called the anode
and the n-type region is called the
cathode. When the voltage on the
anode rises above the voltage on
the cathode, the diode is forward
biased, and current flows through the diode from
the anode to the cathode.
Diode
But when the anode voltage is lower than
the voltage on the cathode, the diode is
reverse biased, and no current flows. The
diode symbol intuitively shows that current
only flows in one direction.
2.3 Capacitor
A capacitor consists of two conductors
separated by an insulator. When a voltage V
is applied to one of the conductors, the
conductor accumulates electric charge Q and
the other conductor accumulates the
opposite charge
−Q.
The capacitance C of the capacitor is the ratio
of charge to voltage: C = Q/V. The
capacitance is proportional to the size of the
conductors and inversely proportional to the
distance between them.
Capacitance is important because charging
or discharging a
conductor takes time and
energy. More capacitance
means that a circuit will be slower and
require more energy to operate.
2.4 nMOS and pMOS
transistor
There are two flavours of MOSFETs: nMOS
and pMOS (pronounced “n-moss” and “p-
moss”). The n-type transistors, called
nMOS, have regions of n-type dopants
adjacent to the gate called the source and
the drain and are built on a p-type
semiconductor substrate. The pMOS
transistors are just the opposite,
consisting of ptype source and drain
regions in an n-type substrate.
Single Transistor
 Combination of
Transistors

3.1 Combinational Logic Design

In digital electronics, a circuit is a
network that processes
discrete-valued variables. A
circuit can be viewed as a black
box, with:
• one or more discrete-valued
input terminals
• one or more discrete-valued
output terminals
•a functional specification describing the relationship
between inputs and outputs
•a timing specification
describing the delay between
inputs changing and outputs
responding.
Digital circuits are classified as combinational or
sequential. A combinational circuit’s outputs depend
only on the current values of the inputs; in other words,
it combines the current input values to compute the
output. For example, a logic gate is a combinational
circuit.
A sequential circuit’s outputs depend on both current
and previous values of the inputs; in other words, it
depends on the input sequence.
A combinational circuit is memoryless, but a sequential
circuit has memory.
The functional specification of a combinational circuit
expresses the output values in terms of the current input
values. The timing specification of a combinational
circuit consists of lower and upper bounds on the delay
from input to output.
The rules of combinational
composition tell us how we can build a
large combinational circuit from smaller combinational circuit
elements.
A circuit is combinational if it consists of interconnected circuit
elements such that:  Every circuit element is itself
combinational.
 Every node of the circuit is either
designated as an input to the circuit or
connects to exactly one output terminal
of a circuit element.
The circuit contains no cyclic paths:
every path through the circuit visits
each circuit node at most once.
 Project 3.1.1
Which of these circuits is/are combinational?
 Project 3.1.2
Ben Bit diddle is having a picnic. He won’t enjoy it if it
rains or if there are ants. Design a circuit that will
output TRUE only if Ben enjoys the picnic.
De Morgan Theorem
 Seven Segment Display
A seven-segment display
decoder takes a 4-bit data
input D3:0 and produces
seven outputs to control
light-emitting diodes to
display a digit from 0 to 9.
The seven outputs are often called segments a
through g, or Sa–Sg
Project 3.1.3
Write a truth table for the outputs of
seven segment display decoder, and use
K-maps to find Boolean equations for
outputs Sa and Sb. Assume that illegal
input values (10–15) produce a blank
readout.
Multiplexer (Mux)
Multiplexers are among the most
commonly used combinational circuits.
They choose an output from among
several possible inputs based on the value
of a select signal.
multiplexer with two data
inputs D0 and D1, a select input
S, and one output Y. The
multiplexer chooses between
the two data inputs based
on the select: if S = 0, Y = D0,
and if S = 1, Y = D1. S is also
called a control signal
because it controls what the
 multiplexer does. multiplexer can be built
from sum-of-products logic.
 Multiplexer
Multiplexer using tristate
buffer implementation using
2
level logic
Decoders
A decoder has N inputs and
2^N outputs. It asserts
exactly one of its outputs
 depending on the input combination. Decoder
Implementation
Implement a 2:4 decoder with AND, OR, and
NOT gates.

4.1 Sequential Logic Design

The outputs of sequential logic depend on both current and
prior input values. Hence, sequential logic has memory.
Sequential logic might explicitly remember certain previous
inputs, or it might distill the prior inputs into a smaller
amount of information called the state of the system
The state of a digital sequential circuit is a set of
bits called state variables that contain all the
information about the past necessary to explain the
future behaviour of the circuit.
Latches and flipflop
The fundamental building block of memory
is a bistable element, an element with two
stable states.
The first figure beside(a) shows a simple
bistable element consisting of a pair of
inverters connected in a loop. While the one
below (b) shows the same circuit redrawn to
emphasize the symmetry. The inverters are
cross-coupled, meaning that the input of I1 is the output of I2 and vice versa.
The circuit has no inputs, but it does have two outputs, Q and Q:.
Analyzing this circuit is different from analyzing a combinational circuit because
it is cyclic: Q depends on Q, and Q depends on Q.
Consider the two cases, Q is 0 or Q is 1. Working through the consequences of
each case, we have:
Case I: Q = 0 As shown in (a), I2 receives a FALSE
input, Q, so it produces a TRUE output on Q: I1
receives a TRUE input, Q, so it produces a FALSE
output on Q. This is consistent with the original
assumption that Q = 0, so the case is said to be
stable.
Case II: Q = 1 As shown in (b), I2 receives a TRUE
input and produces a FALSE output on Q: I1
receives a FALSE input and produces a TRUE
output on Q. This is again stable.
Because the cross-coupled inverters have two
stable states, Q = 0 and Q = 1, the circuit is said to
be bistable. A subtle point is that the circuit has a
third possible state with both outputs
approximately halfway between 0 and 1. This is
called a metastable state.
An element with N stable states conveys log2N bits of information,
so a bistable element stores one bit. The state of the cross-coupled
inverters is contained in one binary
state variable, Q. The value of Q tells
us everything about the past that is
necessary to explain the future
behaviour of the circuit. Specifically,
if Q = 0, it will remain 0 forever, and
if Q = 1, it will remain 1 forever. The
circuit does have another node, Q,
but Q does not contain any additional
information because if Q is known, Q
is also known. On the other hand, Q
is also an acceptable choice for the state variable.
When power is first applied
to a sequential circuit, the
 initial state is unknown and
usually unpredictable. It
may differ each time the
circuit is turned on.

4.2 SR Latch
One of the simplest sequential
circuits is the SR latch, which is
composed of two cross-coupled
NOR gates.
The latch has two inputs, S and R,
and two outputs, Q and Q: The SR
latch is similar to the cross-
coupled inverters, but its state can be controlled through
the S and R inputs, which set and reset the output Q.
• Case I: R = 1, S = 0 N1 sees at least one TRUE input,
R, so it produces a FALSE output on Q. N2 sees both
Q and S FALSE, so it produces a TRUE output on Q:
• Case II: R = 0, S = 1 N1 receives inputs of 0 and Q:
Because we don’t yet know Q, we can’t determine
the output Q. N2 receives at least one TRUE input, S,
so it produces a FALSE output on Q: Now we can
revisit N1, knowing that both inputs are FALSE, so
the output Q is TRUE.
• Case III: R = 1, S = 1 N1 and N2 both see at least one
TRUE input (R or S), so each produces a FALSE
output. Hence Q and Q are both FALSE.
• Case IV: R = 0, S = 0 N1 receives inputs of 0 and Q:
Because we don’t yet know Q, we can’t determine
the output. N2 receives inputs of 0 and Q. Because
we don’t yet know Q, we can’t determine the
output. Now we are stuck. This is reminiscent of the
cross-coupled inverters. But we know that Q must
either be 0 or 1. So we can solve the problem by
checking what happens in each of these subcases.
• Case IVa: Q = 0 Because S and Q are FALSE,
N2 produces a TRUE output on Q, as
shown in Figure 3.4(a). Now N1 receives
one TRUE input, Q, so its output, Q, is
FALSE, just as we had assumed.
• Case IVb: Q = 1 Because Q is TRUE, N2
produces a FALSE output on Q, as shown
in Figure 3.4(b). Now N1 receives two
FALSE inputs, R and Q, so its output, Q, is
TRUE, just as we had assumed.
Putting this all together, suppose Q has some
known prior value, which we will call Qprev,
before we enter Case IV. Qprev is either 0 or
1, and represents the state of the system.
When R and S are 0, Q will remember this
old value, Qprev, and Q will be its
complement, Qprev : This circuit has
memory.
The inputs S and R stand for Set and Reset. To set a bit
means to make it TRUE. To
reset a bit means to make it
FALSE. The outputs, Q and Q, are normally
complementary.
The SR latch is represented by the symbol in beside.
Using the symbol is an application of abstraction and
modularity. There are various ways to build an SR
latch, such as using different logic gates
or transistors. Nevertheless, any circuit
element with the relationship specified
by the truth table and the symbol is
called an SR latch.
 4.3 D Latch
The SR latch is awkward because
it behaves strangely when both S
and R are simultaneously
asserted. Moreover, the S and R
inputs conflate the issues of
what and when. Asserting one of
the inputs determines not only
what the state should be but also
when it should change. Designing
circuits becomes easier when these questions of what and
when are separated.
The D latch solves these problems. It has two inputs. The data input, D,
controls what the next state should be. The clock input, CLK, controls
when the state should change.
For convenience, we first consider the internal nodes D, S, and R. If CLK =
0, both S and R are FALSE, regardless of the value of D. If CLK = 1, one
AND gate will produce TRUE and the other FALSE, depending on the
value of D. Given S and R, Q and Q are determined.
Observe that when CLK = 0, Q remembers its old value, Qprev. When
CLK = 1, Q = D. In all cases, Q is the complement of Q, as would seem
logical. The D latch avoids the strange case of simultaneously asserted R
and S inputs.
Putting it all together, we see that the clock controls when data flows
through the latch. When CLK = 1, the latch is transparent. The data at D
flows through to Q as if the latch were just a buffer. When CLK = 0, the
latch is opaque. It blocks the new data from flowing through to Q, and Q
retains the old value. Hence, the D latch is sometimes called a
transparent latch or a level-sensitive latch.
The D latch updates its state continuously while CLK = 1. We shall see
later in this section that it is useful to update the state only at a specific
instant in time. The D flip-flop described in the next section does just
that.

4.4 Flip flop

A D flip-flop can be built from two
back-to-back D latches controlled by
complementary clocks. The first latch,
L1, is called the master. The second
latch, L2, is called the slave. The node between them
is named N1. When the Q(bar) output is not needed,
the symbol is often condensed)c)
When CLK = 0, the master latch is transparent and the slave is opaque.
Therefore, whatever value was at D propagates through to N1. When CLK = 1,
the master goes opaque and the slave becomes transparent. The value at N1
propagates through to Q, but N1 is cut off from D. Hence, whatever value was
at D immediately before the clock rises from 0 to 1 gets copied to Q
immediately after the clock rises. At all other times, Q retains its old value,
because there is always an opaque latch blocking the path between D and Q
In other words, a D flip-flop copies D to Q on the rising edge of the clock, and
remembers its state at all other times. Reread this definition until you have it
memorized; one of the most common problems for beginning digital designers
is to forget what a flip-flop does. The rising edge of the clock is often just called
the clock edge for brevity. The D input specifies what the new state will be.
The clock edge indicates when the state should be updated..
A D flip-flop is also known as a master-slave flip-flop, an edge-triggered flip-
flop, or a positive edge-triggered flip-flop. The triangle in the symbols denotes
an edge-triggered clock input. The Q(bar) output is often omitted when it is not
needed.

Project 4.4.1 (Flip flop transistor count)

How many transistors are needed to build the D flip-flop
described in this section?
 4.5 Register
An N-bit register is a bank of N
flip-flops that share a common
CLK input, so that all bits of the
register are updated at the same
time. Registers are the key
building block of most sequential
circuits.
The figure (a) and (b) shows the
schematic and symbol for a four-
bit register with inputs D3:0 and outputs Q3:0. D3:0 and
Q3:0 are both 4-bit busses.

Summary
Latches and flip-flops are the fundamental
building blocks of sequential circuits.
Remember that a D latch is level-sensitive,
whereas a D flipflop is edge-triggered. The
D latch is transparent when CLK = 1,
allowing the input D to flow through to the
 output Q. The D flip-flop copies D to Q on
the rising edge of CLK. At all other times,
latches and flip-flops retain their old state.
A register is a bank of several D flip-flops
that share a common CLK signal.
5.1 HARDWARE DESCRIPTION LANGUAGE
Thus far, we have focused on designing combinational and
sequential digital circuits at the schematic level. The process
of finding an efficient set of logic gates to perform a given
function is labour intensive and error prone, requiring
manual simplification of truth tables or Boolean equations
and manual translation of finite state machines (FSMs) into
gates. In the 1990s, designers discovered that they were far
more
productive
if they worked at a higher level of abstraction,
specifying just the logical function and allowing a
computer-aided design (CAD) tool to produce the
optimized gates. The specifications are generally
given in a hardware description language (HDL). The
two leading hardware description languages are
SystemVerilog and VHDL
You can download system verilog IDE via
https://www.mentor.com/comp
any/higher_ed/modelsimstudent-edition or you can use an
online IDE at
https://www.edaplayground.co m/
SystemVerilog and VHDL are built on similar principles but
have different syntax, in this course attention will be given
to System verilog, students can easily learn VHDL on their
own if they like since the two are similar in most cases.
HDL is recommended to
students because
Digital computers are nowadays design in HDLs and not
schematic design.
Module
A block of hardware with inputs and outputs is called a
module. An AND gate, a multiplexer, and a priority circuit
are all examples of hardware modules. The two general
styles for describing module functionality are behavioural
and structural. Behavioural models describe what a module
does. Structural models describe how a module is built from
simpler pieces; it is an application of hierarchy.
Assignment Students should learn more about system
verilog syntax at https://en.wikipedia.org/wiki/Sy
stemVerilog
SystemVerilog started with the donation of the Superlog
language to Accellera in 2002 by the startup company Co-
Design Automation.[1] The bulk of the verification
functionality is based on the OpenVera language donated
by Synopsys. In 2005, SystemVerilog was adopted as IEEE
Standard 1800-
2005.[2] In 2009,
the standard was merged with the base Verilog (IEEE
13642005) standard, creating IEEE Standard 1800-2009. The
current version is IEEE standard 1800-2017. Example 1
illustrate behavioural descriptions of a module that
computes the Boolean function
from

the module is named sillyfunction and has three inputs, a, b,

and c, and one output, y.
SystemVerilog
Module sillyfunction (input logic
a, b, c, output logic y);
assign y = ~a & ~b & ~c | a & ~b &
~c
| a & ~b & c;
endmodule

explanation
A SystemVerilog module begins with the module name and a listing of the
inputs and outputs. The assign statement describes combinational logic. ~
indicates NOT, & indicates AND, and | indicates OR.
logic signals such as the inputs and outputs are Boolean variables (0 or 1).
They may also have floating and undefined values.
The logic type was introduced in SystemVerilog. It supersedes the reg type,
which was a perennial source of confusion in Verilog. logic should be used
 everywhere except on signals with multiple drivers. Signals with multiple
drivers are called nets
5.2 Simulation and synthesis
The two major purposes of HDLs are logic simulation and
synthesis. During simulation, inputs are applied to a
module, and the outputs are checked to verify that the
module operates correctly. During synthesis, the textual
description of a module is transformed into logic gates.
Simulation
Humans routinely make mistakes. Such errors in
hardware designs are called bugs. Eliminating the bugs from
a digital system is obviously important, especially
when customers are paying money and lives depend on the
correct operation. Testing a system in the laboratory is
timeconsuming. Discovering the cause of errors in the lab
can be extremely difficult, because only signals routed to the
chip pins can be observed. There is no way to directly
observe what is happening inside a chip. Correcting errors
after the system is built can be devastatingly expensive.
Synthesis
Logic synthesis transforms
HDL code into a netlist
describing the hardware
(e.g., the logic gates and the wires connecting
them). The logic synthesizer might perform
optimizations to reduce the amount of hardware
required. The netlist may be a text file, or it may be
drawn as a schematic to help visualize the circuit.
Because our primary interest is to build hardware, we will emphasize a
synthesizable subset of the languages. Specifically, we will divide HDL
code into synthesizable modules and a testbench. The synthesizable
modules describe the hardware. The testbench contains code to apply
inputs to a module, check whether the output results are correct, and
print discrepancies between expected and actual outputs. Testbench
code is intended only for simulation and cannot be synthesized.
One of the most common mistakes for beginners is to think of HDL as a
computer program rather than as a shorthand for describing digital
hardware. If you don’t know approximately what hardware your HDL
should synthesize into, you probably won’t like what you get. You might
create far more hardware than is necessary, or you might write code
that simulates correctly but cannot be implemented in hardware.
Instead, think of your system in terms of blocks of combinational logic,
registers, and finite state machines. Sketch these blocks on paper and
show how they are connected before you start writing code.
In our experience, the best way to learn an HDL is by example. HDLs
have specific ways of describing various classes of logic; these ways are
called idioms. When you need to describe a particular kind of hardware,
look for a similar example and adapt it to your purpose.
5.3 Combinational Logic
Software design is a process to conceptualize the software
requirements into software implementation. Software
design takes the user requirements as challenges and tries
to find optimum solution. There are multiple variants of
software design. Bitwise operators
Bitwise operators act on singlebit signals or on multi-bit
busses. For example, the inv SystemVerilog
module inv(input logic [3:0] a, output
logic [3:0] y); assign y = ~a;
endmodule
Explanation a[3:0] represents a 4-bit bus. The bits, from
most significant to least significant, are a[3], a[2], a[1], and
a[0]. This is called little-endian order, because the
least significant bit has the smallest bit number.
module describes four inverters connected to 4-bit busses.
Example 3
The gates module in HDL Example 4.3 demonstrates bitwise operations
acting on 4-bit busses for other basic logic functions.

module gates(input logic [3:0] a, b, output logic

[3:0] y1, y2, y3, y4, y5);
/* five different two-input logic gates acting
on 4bit busses */
assign y1 = a & b; // AND assign y2 = a | b; //
OR assign y3 = a ^ b; // XOR assign y4 = ~(a &
b); // NAND assign y5 = ~(a | b); // NOR
endmodule

Explanation ~, ^, and | are examples of SystemVerilog operators,

whereas a, b, and y1 are operands. A combination of operators and
operands, such as a&b, or ~(a | b), is called an expression. A complete
command such as assign y4 = ~(a & b); is called a statement. assign out
= in1 op in2; is called a continuous assignment statement. Continuous
assignment statements end with a semicolon. Anytime the inputs on
the right side of the = in a continuous assignment statement change,
the output on the left side is recomputed. Thus, continuous assignment
statements describe combinational logic.
 Comments and white space
5.4
The gates example showed how
SystemVerilog comments
are to format comments. just like those in C or Java.
SystemVerilog and VHDL are not
Comments beginning with /*
picky about the use of white continue, possibly across space
(i.e., spaces, tabs, and line multiple lines, to the next */. breaks).
Nevertheless, proper
Comments beginning with //
indenting and use of blank lines continue to the end of the line. is
helpful to make nontrivial
 SystemVerilog is case-sensitive.
designs readable. Be consistent y1 and Y1 are different signals in in
your use of capitalization and
SystemVerilog. However, it is
underscores in signal and confusing to use multiple signals
module names. This text uses all that differ only in case. lower case.
Module and signal names must not begin with a digit.
5.5 Reduction Operator
Reduction operators imply a multiple-input gate acting on a single
bus. Example 5 describes an eight-input AND gate with inputs a7,
a6, . . ., a0. Analogous reduction operators exist for OR, XOR,
NAND, NOR, and XNOR gates. Recall that a multiple-input XOR
performs parity, returning TRUE if an odd number of inputs are
TRUE. Project 5.5.1 find out the output of the module.
SystemVerilog
module and8(input logic [7:0] a, output
logic y); assign y = &a; // &a is much
easier to write than // assign y = a[7] &
a[6] & a[5] & a[4] & // a[3] & a[2] & a[1] &
a[0]; endmodule
5.6 Conditional Assignment
Conditional assignments select the output from among
alternatives based on an input called the condition. Example 6
illustrate a 2:1 multiplexer using conditional assignment.
module mux2(input logic [3:0] d0, d1, input
logic s, output logic [3:0] y); assign y = s
? d1 :
d0; endmodule
The conditional operator ?: chooses, based on a first expression, between a
second and third expression. The first expression is called the condition. If the
condition is 1, the operator chooses the second expression. If the condition is 0,
the operator chooses the third expression.
?: is especially useful for describing a multiplexer because, based on the first
input, it selects between two others. The following code demonstrates the idiom
for a 2:1 multiplexer with 4-bit inputs and outputs using the conditional
operator.
If s is 1, then y = d1. If s is 0, then y = d0. ?: is also called a ternary operator,
because it takes three inputs. It is used for the same purpose in the C and Java
programming languages.
 Project 5.6.1 what is the synthesied output of the module
module mux4(input logic [3:0] d0, d1, d2, d3, input
logic [1:0] s, output logic [3:0] y); assign y =
s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 :
d0); endmodule
5.7 Internal variables
Often it is convenient to break a complex function into
intermediate steps. For example, a full adder, is a circuit with
three inputs and two outputs defined by the following
equations:

If we define intermediate
signals, P and G, P=A B G = AB we can rewrite the full
adder as follows:
P and G are called internal variables,
because they are neither inputs nor
outputs but are used only internal to
module fulladder(input
logic a, b, cin, output
logic s, cout); logic p,
assign s = p ^ cin;
cin); Endmodule
Project 5.7 what is the
5.8 Operator
Precedence & Numbers
Numbers can be specified in binary,
octal, decimal, or hexadecimal (bases
2, 8, 10, and 16, respectively). The size,
i.e., the number of bits, may optionally
be given, and leading zeros are
inserted to reach this size. Underscores in numbers are ignored and can be
helpful in breaking long numbers into more readable chunks. The format for
declaring constants is N'Bvalue, where N is the size in bits, B is a letter indicating
the base, and value gives the value. For
example, 9'h25 indicates a 9-bit
number with a value of 2516 = 3710 =
0001001012. SystemVerilog supports 'b
for binary, 'o for octal, 'd for decimal,
and 'h for hexadecimal. If the base is
omitted, it defaults to decimal.
If the size is not given, the
number is assumed to have as
many bits as the expression in
which it is being used. Zeros are
automatically padded on the
front of the number to bring it
up to full size. For example, if w
is a 6-bit bus, assign w = 'b11 gives w the value 000011. It is better
practice to explicitly give the size. An exception is that '0 and '1 are
SystemVerilog idioms for filling a bus with all 0s and all 1s,
respectively.
5.9 Z’s and X’s
HDLs use z to indicate a floating value, z is particularly useful for describing a
tristate buffer, whose output floats when the enable is 0.
Similarly, HDLs use x to indicate an invalid logic level. If a bus is simultaneously
driven to 0 and 1 by two enabled tristate buffers (or other gates), the result is x,
indicating contention. If all the tristate buffers driving a bus are simultaneously
OFF, the bus will float, indicated by z. At the start of simulation, state nodes such
as flip-flop outputs are initialized to an unknown state (x in
SystemVerilog and u in VHDL). This is
module tristate(input logic [3:0] a, input
logic en, output tri [3:0] y); assign y = en
? a :
4'bz;
Endmodule

Project 5.9.1 what is the tristate

synthesized circuit?
helpful to track errors caused by
forgetting to reset a flip-flop before its
output is used.
5.10 Delays
Example 7
HDL statements may be associated
It assumes that inverters have a delay
with delays specified in arbitrary units. of 1 ns, three-input AND gates have a
They are helpful during simulation to delay of 2 ns, and three-input OR gates
predict how fast a circuit will work (if have a delay of 4 ns. you specify
meaningful delays) and also
‘timescale 1ns/1ps
for debugging purposes to understand module example(input logic
cause and effect (deducing the source a, b, c, output logic y);
of a bad output is tricky if all signals logic ab, bb, cb, n1, n2,
change

sim
ult
ane
ous
ly
in

the
n3
;
simulation results). These delays are assign #1 {ab, bb, cb} =
ignored during synthesis; the delay of a
~{a, b, c};
gate produced by the synthesizer assign #2 n1 = ab & bb &
depends on its tpd and tcd cb; assign
#2 n2 = a & bb
specifications, not on numbers in HDL
 & cb;
code.
assign #2 n3 = a & bb & c; assign #4 y = n1 | n2 |
n3; endmodule
SystemVerilog files can include a
timescale directive that indicates the value of each time unit. The
statement is of the form 'timescale unit/precision. In this file, each
unit is 1 ns, and the simulation has 1 ps precision. If no timescale
directive is given in the file, a default unit and precision (usually 1
ns for both) are used. In SystemVerilog, a # symbol is used to
indicate the number of units of delay. It can be placed in assign
statements, as well as non-blocking (<=) and blocking (=)
assignments
Project 5.10.1 What is the simulation waveform with delay of
the module
 5.11 Structural Modelling
The previous section discussed module mux4(input
behavioural modelling, describing a module in terms of the relationships
between inputs and outputs. This section examines structural modelling,
describing a module in terms of how it is composed of simpler modules Example
8
show how to assemble a 4:1 multiplexer from three 2:1 multiplexers. Each copy
of the 2:1 multiplexer is called an instance. Multiple instances of the same
module are distinguished by distinct names, in this case lowmux, highmux, and
finalmux. This is an example of regularity, in which the 2:1 multiplexer is reused
many times.
logic [3:0] d0, d1, d2, d3, input logic [1:0]
s, output logic [3:0] y); logic [3:0] low,
high; mux2 lowmux(d0, d1, s[0], low); mux2
highmux(d2, d3, s[0], high); mux2
finalmux(low, high, s[1], y); endmodule
Project 5.11.1 show the synthesized circuit
 Example 9 shows how modules can access part of a bus. An 8-bit wide 2:1
multiplexer is built using two of the 4-bit 2:1 multiplexers already defined,
operating on the low and high nibbles of the byte.
Note:
In general, complex systems are designed hierarchically. The overall system is
described structurally by instantiating its major components. Each of these
components is described structurally from its building blocks, and so forth
recursively until the pieces are simple enough to describe behaviourally. It is
good style to avoid (or at least to minimize) mixing structural and behavioural
descriptions within a single module.
module mux2_8(input logic [7:0] d0, d1, input logic s, output
logic [7:0] y); mux2 lsbmux(d0[3:0], d1[3:0], s, y[3:0]);
mux2 msbmux(d0[7:4], d1[7:4], s, y[7:4]); endmodule
Project 5.11.2
Show synthesized circuit
5.12 Sequential Logic
HDL synthesizers recognize certain module flop(input
idioms and turn them into specific sequential circuits. Other coding styles may
simulate correctly but synthesize into circuits with blatant or subtle errors. This
section presents the proper idioms to describe registers and latches. Registers
The vast majority of modern commercial systems are built with registers using
positive edge-triggered D flip-flops. Example 10 shows the idiom for such flip-
flops. Note that In general, a SystemVerilog always statement is written in the
form always @(sensitivity list) statement;
logic clk, input logic [3:0] d, output logic
[3:0] q); always_ff @(posedge clk) q <= d;
endmodule Project 5.12.1 show the
synthesized circuit
The statement is executed only when the event specified in the sensitivity list
occurs. In this example, the statement is q <= d (pronounced “q gets d”). Hence,
the flip-flop copies d to q on the positive edge of the clock and otherwise
remembers the old state of q. Note that sensitivity lists are also referred to as
stimulus lists. <= is called a nonblocking assignment. Think of it as a regular = sign
for now; we’ll return to the more subtle points in Section 4.5.4. Note that <= is
used instead of assign inside an always statement. As will be seen in subsequent
sections, always statements can be used to imply flip-flops, latches, or
combinational logic, depending on the sensitivity list and statement. Because of
this flexibility, it is easy to produce the wrong hardware inadvertently.
SystemVerilog introduces always_ff, always_latch, and always_comb to reduce
the risk of common errors. always_ff behaves like always but is used exclusively
to imply flip-flops and allows tools to produce a warning if anything else is
implied.
Resettable Register
When simulation begins or power is first applied to a circuit, the output of a flop
or register is unknown. This is indicated with x in SystemVerilog and u in VHDL.
Generally, it is good practice to use resettable registers so that on powerup you
can put your system in a known state.
The reset may be either asynchronous or synchronous. Recall that
asynchronous reset occurs immediately, whereas synchronous reset clears the
output only on the next rising edge of the clock. Example 11
demonstrates the idioms for flip-flops with asynchronous and synchronous
resets
Note that distinguishing synchronous and asynchronous reset in a schematic can
be difficult. The schematic produced by Simplify Premier places asynchronous
reset at the bottom of a flip-flop and synchronous reset on the left side.
Project 5.12.2
Show synthesized circuits
module flopr(input logic clk, input logic reset, input
logic [3:0] d, output logic [3:0] q); // asynchronous
reset always_ff @(posedge clk, posedge reset) if
(reset) q <= 4'b0; else q <= d; endmodule module
flopr(input logic clk, input logic reset, input logic
[3:0] d, output logic [3:0] q); // synchronous reset
always_ff @(posedge clk) if (reset) q <= 4'b0; else q
<= d; endmodule
Multiple signals in an always statement sensitivity list are separated
with a comma or the word or. Notice that posedge reset is in the
sensitivity list on the asynchronously resettable flop, but not on the
synchronously resettable flop. Thus, the asynchronously resettable
flop immediately responds to a rising edge on reset, but the
synchronously resettable flop responds to reset only on the rising
edge of the clock.
Because the modules have the same name, flopr, you may include
only one or the other in your design.
Enable Register
Enabled registers respond to the clock only when the enable is
asserted.
Example 12 show an asynchronously resettable enabled register
that retains its old value if both reset and en are FALSE.
Recall that a D latch is
transparent when the clock is
HIGH, allowing data to flow
from input to output.
The latch becomes
opaque when the clock is LOW,
retaining its old state. Example
13 show the idiom for a D latch.
Note
Not all synthesis tools support always latch is equivalent to always latches
well. Unless you know @(clk, d) and is the preferred idiom for describing a
latch in SystemVerilog. It
that your tool does support evaluates any time clk or d changes. If latches
and you have a good clk is HIGH, d flows through to q, so this reason to use
them, avoid them code describes a positive level sensitive and use edge-
triggered flip-flops latch. Otherwise, q keeps its old value. instead.
SystemVerilog can generate a warning if
the always_ latch block doesn’t imply a
latch.
INVERTER USING always The = in the always statement is called a blocking

assignment, in contrast to the

<= nonblocking
In
SystemVerilog, it is good practice to use blocking assignments for combinational
logic and nonblocking assignments for sequential logic. Example 14
always_comb reevaluates the define a full adder using intermediate statements
any time any of
inside the always statement signals p and g to compute s and cout.
the signals on the right
using always/process statements in hand side of <= or = in
the always place of assignment statements. statement change. In this case, it is
Note: In this case, always @(a, b, cin) equivalent to always @(a), but is better
would have been equivalent to because it avoids mistakes if signals in
always_comb. However, always_comb is the always statement are renamed or
better because it avoids common added. If the code inside the always mistakes of
missing signals in the block is not combinational logic, sensitivity list.
SystemVerilog will report a warning. Case statement
always_comb is equivalent to always A better application of using the
@(*), but is preferred in SystemVerilog. always/process statement for
 implies combinational logic if all possible
input combinations are defined;
otherwise it implies sequential logic,
because the output will keep its old value
in the undefined cases.
Synplify Premier synthesizes the
sevensegment display decoder into a read-
only memory (ROM) containing the 7

outputs for each of the 16 possible inputs.

combinational logic is a seven-segment

display decoder that takes advantage of
the case statement that must appear
inside an always statement. Example 15
using case statements describe
a seven-segment display decoder
based on its truth table.
Note: The case statement performs different actions depending on the value of
its input. A case statement
Project 5.12.3
Capture the synthesized
7 segment display circuit. If
statement
always statements may also
contain if statements. The if
statement may be followed by an Project 5.12.4 synthesized
else statement. If all possible input Capture the
combinations are handled, the priority circuit.
statement implies combinational
logic; otherwise, it produces
sequential logic.
Example 16
Priority circuit.
Note: In SystemVerilog, if
statements must appear inside of always
statements.
 Example 17
FULL ADDER USING
NONBLOCKING ASSIGNMENTS

Observe that s is computed

concurrently with p and hence uses
the old value of p, not the new
value. Therefore, s remains 0 rather
than becoming 1. However, p does
change from 0 to 1. This change
triggers the always/process
statement to evaluate a second
time, as follows:
P← 1 0 = 1 g ← 1 ∙ 0 = 0 s ← 1 0 = 1 cout ← 0 + 1 ∙ 0 = 0
This time, p is already 1, so s correctly changes to 1. The nonblocking assignments
eventually reach the right answer, but the always/ process statement had to
evaluate twice. This makes simulation slower, though it synthesizes to the same
hardware.
Another drawback of nonblocking assignments in modeling combinational logic is
that the HDL will produce the wrong result if you forget to include the
intermediate variables in the sensitivity list.
Worse yet, some synthesis tools will synthesize the correct hardware even when a
faulty sensitivity list causes incorrect simulation. This leads to a mismatch between
the simulation results and what the hardware actually does.
Test Bench
A testbench is an HDL module that is used to test another module, called the
device under test (DUT). The testbench contains statements to apply inputs to the
DUT and, ideally, to check that the correct outputs are produced. The input and
desired output patterns are called test vectors.
Example 18
Consider testing
This is a simple module, so we can perform exhaustive testing by applying all eight
possible test vectors.
Note: The initial statement executes the statements in its body at the start of
simulation. In this case, it first applies the
input pattern 000 and waits for 10 time
units. It then applies 001 and waits 10
more units, and so forth until all eight
possible inputs have been applied.
initial statements should be used only in
testbenches for simulation, not in
modules intended to be synthesized into
actual hardware. Hardware has no way of
magically executing a sequence of special
steps when it is first turned on.
Example 18 demonstrates a simple
testbench. It instantiates the DUT, then
applies the inputs. Blocking assignments
and delays are used to apply the inputs in
the appropriate order. The user must view
the results of the simulation and verify by
inspection that the correct outputs are produced. Testbenches are simulated the
same as other HDL modules. However, they are not synthesizeable.
Example 19 The SystemVerilog assert
statement SELF-CHECKING TESTBENCH
checks if a specified condition is true.
If not, it executes the else statement.
The $error system task in the else
statement prints an error message
describing the assertion failure. assert is
ignored during synthesis.
In SystemVerilog, comparison using ==
or != is effective between signals that do
not take on the values of x and z.
Testbenches use the === and !==
operators for comparisons of equality
and inequality, respectively, because
these operators work correctly with
operands that could be x or z.
TESTBENCH WITH TEST VECTOR FILE the simulation in the next example, it reads
the test vectors from a text file and pulses reset for two cycles.
example.tv is a text file containing the inputs
and expected output written in binary:
 6.1
ARITHMETIC DESIGN
Arithmetic Circuits
Computers and digital logic
perform many arithmetic functions:
addition, subtraction, comparisons,
shifts, multiplication, and division.
This section describes hardware
implementations for all of these
operations. Half Adder
Full Adder
Adder
Subtraction
6.2
adders can add positive and
negative numbers using two’s
complement number
representation. Subtraction is
almost as easy: flip the sign of the
second number, then add.
Flipping the sign of a two’s
complement number is done by
inverting the bits and adding 1.
Subtractor Comparator
6.3
A comparator determines
whether two binary numbers
are equal or if one is greater or
less than the other. A
comparator receivestwo N-bit
binary numbers A and B. There
are two common types of
comparators.
6.4
Comparator
 6.5

ALU
An Arithmetic/Logical Unit (ALU)
combines a variety of mathematical and
logical operations into a single unit. For
example, a typical ALU might perform
addition, subtraction, magnitude
comparison, AND, and OR operations. The
ALU forms the heart of most computer
systems.
 ALU Operations
The ALU receives a control signal F that specifies which function to perform.
Control signals will generally be
shown in blue to distinguish them
from the data..
The SLT function is used for
magnitude comparison and will be
discussed later in this section.
Example 20 show an
implementation of the ALU. The ALU
contains an N-bit adder and N two-
input AND and OR gates. It also
contains inverters and a multiplexer
to invert input B when the F2 control
signal is asserted. A 4:1 multiplexer
chooses the desired function based on
the F1:0 control signals.
SLT is performed by computing S = A −
B. If S is negative (i.e., the sign bit is
set), A is less than B. The zero extend
unit produces an N-bit output by
concatenating its 1-bit input with 0’s in
the most significant bits. The sign bit
(the N-1th bit) of S is the input to the
zero extend unit.
Project 6.4.1
Configure a 32-bit ALU for the SLT
operation. Suppose A = 2510 and B =
3210. Show the control signals and
output, Y.
6.5 Shifters and Rotators
Shifters and rotators move bits and multiply or divide by powers of 2. As the
name implies, a shifter shifts a binary number left or right by a specified number
of positions. There are several kinds of commonly used shifters:
a. Logical shifter—shifts the number to the left (LSL) or right (LSR) and fills
empty spots with 0’s. Ex: 11001 LSR 2
= 00110; 11001 LSL 2 = 00100
b. Arithmetic shifter—is the same as a logical shifter, but on right shifts fills
the most significant bits with a copy of the old most significant bit (msb).
This is useful for multiplying and dividing signed numbers. Ex: 11001 ASR 2
= 11110; 11001 ASL 2 = 00100
c. Rotator—rotates number in circle such that empty spots are filled with bits
shifted off the other end. Ex: 11001 ROR 2 = 01110;
11001 ROL 2 = 00111
4-bit shifters: (a) shift left, (b) logical shift right, (c) arithmetic shift right
6.6 Multiplier & Division
Division:
Binary division can be performed using
the following algorithm for Nbit
unsigned numbers in the range
7.1 MEMORY & I/O SYSTEM
A computer’s ability to solve problems is influenced by its memory
system and the input/output (I/O) devices – such as
monitors, keyboards, and printers – that allow us to manipulate
and view the results of its computations. This chapter
investigates these practical memory and I/O systems.

The processor communicates with the memory system over a

memory interface. Figure 8.1 shows the simple memory interface
used in our multicycle MIPS processor. The processor sends an
address over the Address bus to the memory system. For a read,
MemWrite is 0 and the memory returns the data on the ReadData
bus. For a write, MemWrite is 1 and the processor sends data to
memory on the WriteData bus.

Memory system performance analysis

Designers (and computer buyers) need quantitative ways to measure the
performance of memory systems to evaluate the cost-benefit trade-offs of
various alternatives. Memory system performance metrics are miss rate or hit
rate and average memory access time. Miss and hit rates are calculated as:

Example 21
Suppose a program has 2000 data access instructions (loads or stores), and 1250 of these
requested data values are found in the cache. The other 750 data values are supplied
to the processor by main memory or disk memory. What are the miss and hit rates for
the cache?
Solution
The miss rate is 750/2000 = 0.375 = 37.5%. The hit rate is 1250/2000 = 0.625 = 1
− 0.375 = 62.5%.
The miss rate is 750/2000 = 0.375 =
37.5%. The hit rate is 1250/2000 = 0.625 = 1 − 0.375 = 62.5%. the processor first
looks for the data in the cache. If the cache misses, the processor then looks in
main memory. If the main memory misses, the processor accesses virtual
memory on the hard disk. Thus, AMAT is calculated as:

where tcache, tMM, and tVM are the access times of the cache, main
memory, and virtual memory, and MRcache and MRMM are the cache and
main memory miss rates, respectively.
Compared with the ideal large, fast, cheap memory, a hard drive is large and
cheap but terribly slow. It provides a much larger capacity than is possible with a
cost-effective main memory (DRAM). However, if a significant fraction of
memory accesses involve the hard drive, performance is dismal. You may have
encountered this on a PC when running too many programs at once.
As the name implies, the hard disk contains one or more rigid disks or platters,
each of which has a read/write head on the end of a long triangular arm. The
head moves to the correct location on the disk and reads or writes data
magnetically as the disk rotates beneath it.
7.2 Virtual Memory
A computer with only 128 MB of DRAM, for example, could
effectively provide 2 GB of memory using the hard drive. This
larger 2-GB memory is called virtual memory, and the smaller 128-
MB main memory is called physical memory.
Virtual memory is divided into virtual pages, typically 4 KB in size.
Physical memory is likewise divided into physical pages of the
same size.
Virtual memory systems provide memory protection by giving
each program its own virtual
address space. Each program can use as much memory as it wants in that
virtual address space, but only a portion of the virtual address space is in
physical memory at any given time.
7.3 i/o System
Input/Output (I/O) systems are used to connect a computer with
external devices called peripherals. In a personal computer, the
devices typically include keyboards, monitors, printers, and
wireless networks. In embedded systems, devices could include a
toaster’s heating element, a doll’s speech synthesizer, an engine’s
fuel injector, a satellite’s solar panel positioning motors, and so
forth. A processor accesses an I/O device using the address and
data busses in the same way
that it accesses memory.
7.4 Embedded I/O System
Embedded systems use a processor to control interactions with
the physical environment. They are typically built around
microcontroller units (MCUs) which combine a microprocessor
with a set of easy-to-use peripherals such as general-purpose
digital and analog I/O pins, serial ports, timers, etc.
Microcontrollers are generally inexpensive and are designed to
minimize system cost and size by integrating most of the
necessary components onto a single chip.
8-bit microcontrollers are the smallest and least expensive, while
32-bit microcontrollers provide more memory and higher
performance.
Universal Asynchronous
Receiver Transmitter (UART) A UART (pronounced “you-art”) is a
serial I/O peripheral that communicates between two systems
without sending a clock. Instead, the
systems must agree in advance
about what data rate to use and
must each locally generate its own
clock.
Although these system clocks may
have a small frequency error and an
unknown phase relationship, the UART manages reliable
asynchronous communication.
UARTs are used in protocols.
Analog I/O
The real world is an analog place. Many embedded systems need
analog inputs and outputs to interface with the world. They use
analog-to-digitalconverters (ADCs) to quantize analog signals into
digital values, and digital-toanalog-converters (DACs) to do the
reverse
Character LCD
A character LCD is a small liquid crystal display capable of showing one or a few
lines of text. They are commonly used in the front panels of appliances such as
cash registers, laser printers, and fax machines that need to display a limited
amount of information. They are easy to interface with a microcontroller over
parallel, RS-232, or SPI interfaces.
Example 22
Write a program to write “I love LCDs” to a character display.

Crystalfontz CFAH2002A-TMI 20 × 2 character LCD

VGA Monitor
A more flexible display option is to drive a
computer monitor. The Video Graphics
Array (VGA) monitor standard was
introduced in 1987 for the IBM PS/2
computers, with a 640 × 480 pixel
resolution on a cathode ray tube (CRT) and
a 15-pin connector conveying colour
information with analog voltages. Modern
LCD monitors have higher resolution but
remain backward compatible with the VGA
standard.
The figure shows the pinout for a female
connector coming from a video source.
Pixel information is conveyed with three analog voltages for red, green, and blue.
Each voltage ranges from 0–0.7 V, with more positive indicating brighter. The
voltages should be 0 during the front and back porches. The cable can also
provide an I2 C serial link to configure the monitor.
The video signal must be generated in real
Project 7.4.1
time at high speed, which is difficult on a
Write HDL code to display text and a
microcontroller but easy on an FPGA. A green box on a VGA monitor using
simple black and white display could be the circuitry from diagram shown on
produced by driving all three colour pins next slide.
with either 0 or 0.7 V using a voltage
Note: The code assumes a system
divider connected to a digital output pin. clock frequency of 40 MHz and uses
A colour monitor, on the other hand, uses a phaselocked loop (PLL) on the
a video DAC with three separate D/A
FPGA to generate the 25.175 MHz
converters to independently drive the
VGA clock. PLL configuration varies
three colour pins. among FPGAs; for the Cyclone III,
an FPGA driving a VGA monitor through the frequencies are specified with
an ADV7125 triple 8-bit video DAC. The
Altera’s megafunction wizard.
DAC receives 8 bits of R, G, and B from the
 Alternatively, the VGA clock could
be
FPGA. It also receives a SYNC_b signal that provided directly from a signal
is driven active low whenever HSYNC or generator.
VSYNC are asserted.
The VGA controller counts through
The video DAC produces three output the columns and rows of the screen,
currents to drive the red, green, and blue generating the hsync and vsync
analog lines, which are normally 75 Ω signals at the appropriate times. It
transmission lines parallel terminated at also produces a blank_b signal that
both the video DAC and the monitor
is asserted low to draw black when the coordinates are outside the 640 × 480 active
region.
The video generator produces red, green, and blue colour values based on the current (x, y)
pixel location. (0, 0) represents the upper left corner. The generator draws a set of
characters on the screen, along with a green rectangle. The character generator draws an
8 × 8-pixel character, giving a screen size of 80 × 60 characters. It looks up the character
from a ROM, where it is encoded in binary as 6 columns by 8 rows. The other two columns
are blank. The bit order is reversed by the SystemVerilog code because the leftmost
column in the ROM file is the most significant bit, while it should be drawn in the least
significant x-position.
Bluetooth communication
There are many standards now available for wireless communication, including Wi-Fi,
ZigBee, and Bluetooth. The standards are elaborate and require sophisticated integrated
circuits, but a growing assortment of modules
abstract away the complexity and give the user a simple interface for wireless
communication. One of these modules is the BlueSMiRF, which is an easy-touse Bluetooth
wireless interface that can be used instead of a serial cable.
Bluetooth is a wireless standard developed by Ericsson in 1994 for lowpower, moderate
speed, communication over distances of 5–100 meters, depending on the transmitter
power level.
It is commonly used to connect an earpiece to a cellphone or a keyboard to a
computer. Unlike infrared communication links, it does not require a direct line of
sight between devices.
Bluetooth operates in the 2.4 GHz
unlicensed industrial-scientificmedical (ISM) band. It
defines 79 radio channels spaced at 1 MHz intervals
starting at 2402 MHz. It hops between these channels
in a pseudo-random pattern to avoid consistent interference with other
devices like wireless phones operating in the same band. Bluetooth transmitters
are classified at one of three power levels, which dictate the range and power
consumption.

BlueSMiRF module and USB dongle

USB
Until the mid-1990’s, adding a peripheral to a PC took some technical savvy. Adding
expansion cards required opening the case, setting jumpers to the correct position,
and manually installing a device driver. Adding an RS232 device required choosing
the right cable and properly configuring the baud rate, and data, parity, and stop
bits. The Universal Serial Bus (USB), developed by Intel, IBM, Microsoft, and others,
greatly simplified adding peripherals by standardizing the cables and software
configuration process. Billions of USB peripherals are now sold each year.
USB 1.0 was released in 1996. It uses a simple cable with four wires: 5 V, GND, and a
differential pair of wires to carry data. The cable is impossible to plug in backward or
upside down
It operates at up to 12 Mb/s. A device can pull up to 500 mA from the USB port, so
keyboards, mice, and other peripherals can get their power from the port rather
than from batteries or a separate power cable.
USB 2.0, released in 2000, upgraded the speed to 480 Mb/s. With the faster link,
USB became practical for attaching webcams and external hard disks. Flash memory
sticks with a USB interface also replaced floppy disks.
USB 3.0, released in 2008, it boosted the speed to 5 Gb/s. It uses the same shape
connector, but the cable has more wires that operate at very high speed. It is better
suited to connecting high-performance hard disks. At about the same time, USB
added a Battery Charging Specification that boosts the power supplied over the port
to speed up charging mobile devices.
PCI and PCI Express
The Peripheral Component Interconnect (PCI) bus is an expansion bus standard
developed by Intel that became widespread around 1994. It was used to add
expansion cards such as extra serial or USB ports, network interfaces, sound cards,
modems, disk controllers, or video cards. The 32-bit parallel bus operates at 33 MHz,
giving a bandwidth of 133 MB/s. The demand for PCI expansion cards has steadily
declined. More standard ports such as Ethernet and SATA are now integrated into
the motherboard. Many devices that once required an expansion card can now be
connected over a fast USB 2.0 or 3.0 link. And video cards now require far more
bandwidth than PCI can supply. Contemporary motherboards often still have a small
number of PCI slots, but fast devices like video cards are now connected via PCI
Express (PCIe).
PCI Express slots provide one or more lanes of high-speed serial links. In PCIe 3.0,
each lane operates at up to 8 Gb/s. Most motherboards provide an x16 slot with 16
lanes giving a total of 16 GB/s of bandwidth to data-hungry devices such as video
cards.
DDR3 Memory: DRAM connects to the microprocessor over a parallel bus. In 2012,
the present standard is DDR3, a 3rd generation of double-data rate memory bus
operating at 1.5 V. Typical motherboards now come with two DDR3 channels so they
can access two banks of memory modules simultaneously. Figure next slide shows a
4 GB DDR3 dual inline memory module (DIMM). The module has 120 contacts on
each side, for a total of 240 connections, including a 64-bit data bus, a 16-bit
timemultiplexed address bus, control signals, and numerous power and ground pins.
In 2012, DIMMs typically carry 1–16 GB of DRAM. Memory capacity has been
doubling approximately every 2–3 years.
DRAM presently operates at a clock rate of 100–266 MHz. DDR3 operates the
memory bus at four times the DRAM clock rate. Moreover, it transfers data on both
the rising and falling edges of the clock. Hence, it sends 8 words of data for each
memory clock.
At 64 bits/word, this corresponds to 6.4–17 GB/s of bandwidth. For example, DDR3-
1600 uses a 200 MHz memory clock and an 800 MHz I/O clock to send 1600 million
words/sec, or 12800 MB/s. Hence, the modules
are also called PC3-12800. Unfortunately, DRAM latency remains high, with a roughly 50 ns
lag from a read request until the arrival of the first word of data.
Networking
Computers connect to the Internet over a network interface running the Transmission Control
Protocol and Internet Protocol (TCP/IP). The physical connection may be an Ethernet cable
or a wireless Wi-Fi link.
Ethernet is defined by the IEEE 802.3 standard. It was developed at Xerox Palo Alto Research
Center (PARC) in 1974. It originally operated at 10 Mb/s (called 10 Mbit Ethernet), but now
is commonly found at 100 Mbit (Mb/s) and 1 Gbit (Gb/s) running on Category 5 cables
containing four twisted pairs of wires.
10 Gbit Ethernet running on fiber optic cables is increasingly popular for servers and
other high-performance computing, and 100 Gbit Ethernet is emerging. Wi-Fi is the
 popular name for the IEEE 802.11 wireless network standard. It operates in the 2.4
and 5 GHz unlicensed wireless bands, meaning that the user doesn’t need a radio
operator’s license to
transmit in these
SATA
Internal hard disks require a fast interface to a PC. In 1986, Western Digital
introduced the Integrated Drive Electronics (IDE) interface, which evolved into the
AT Attachment (ATA) standard.
The standard uses a bulky 40 or 80-wire ribbon cable with a maximum length of 18”
to send data at 16–133 MB/s.
ATA has been supplanted by Serial ATA (SATA), which uses highspeed serial links to
run at 1.5, 3, or 6 Gb/s over a more convenient 7-conductor cable
802.11 Wi-Fi Protocols
8.1 INTRODUCTION TO VERO
BOARD
Strip board
A strip board is a board that has no logic
components on it, but can have. Vero
board is an alias for strip board.
They are characterized by 0.1 inch
rectangular grid holes, and parallel
strips of copper on one side of the Stripboard. Unlike a breadboard,
you will need to practice on your soldering technique as
electrical components must be soldered onto them. With a 0.1 inch
hole, you will also require components with 0.1 inch pins
for the Stripboard.
components are always placed at one side of the board while their leads protrude at
the other end. The leads must then be soldered. The soldering orientation must
ensure leads are connected to the copper tracks at the other side of the Stripboard.
In cases where you need to connect wires, 0.1 inch wires are recommended. Wires
with this dimension can pass through holes and be soldered at the other side.
Designing Digital Circuit
Step 1: form the schematic that is synthesized with system verilog.
Step 2: Get vero board and cut to the required size. They are available in standard
sizes, the piece beside is 9 holes wide by 25 holes long and approximate dimensions
1 by 2.5 ‘’. The horizontal 9 strips is known as a
"track". A track is the same as a single wire running from opposite ends of the board.
If a track is broken, with a drill bit or veroboard cutter, you have 2 non-connected
wires on the same horizontal strip. Note that NO continuity exists across adjacent
tracks. If this should happen, i.e. when cutting a track and a piece of copper "swarf"
should accidentally bridge two tracks, then the design would be compromised and
probably not work . Therefore take care when breaking tracks and examine the
board after making each break. Step 3: Collect logic components and tools needed
Step 4: Check that the veroboard is large enough. Loosely push all components
through the holes (in any order). Leave at least a space of 2 holes between
components. This will allow room for wiring and track breaks. A small vice may be
helpful to assemble your circuit.
 Remember that as the board is now upside down that
the top and bottom tracks are reversed. If you turn it
upside down and through 180 degrees then left and
right are also interchanged. This must be born in mind
throughout construction. If in doubt, turn the board
back and forth and keep an eye on a reference point,
say pin 1 of the IC, marked with a dimple or round
spot.

Step 5: You
do need to know how to read a schematic.
The lines represent wires, the symbols
are the components.
Identify them on the vero board.
Step 6: Turn the board over, all component pins should poke through the shiny
copper side of the board. All soldering and track cutting is also done on this side. You
need a little soldering experience to begin with. If you are not used to soldering,
then it is advisable to use a plastic IC socket.

Step 7: Turn the board over and use two veropins for the power connectors. A
veropin is a short piece of metal, that makes contact with the copper side of the
veroboard
It is rigid and allows a wire to be connected on the component side of the board.
Veropins also make convenient test points as well. Push two veropins through the
copper side at the right hand side on track extremities. It is a good idea to separate
power supply rails by at least one vero track.
 Step 8: The wire (also called a "jumper")
because it bridges are spans several
tracks is soldered on the copper side.
After soldering the end wires are cut
close to the board.
Components can be added in any order. It
is however good practise to solder
veropins, jumpers first, then passive components, resistors, capacitors, inductors,
followed by active components such as diodes and transistors next. Finally IC's are
added last, the reason for this order is that repeated soldering and excessive
overheating of the board can destroy the sensitive components. If however, you are
a competant at soldering, any order of assembly can take place.
Where to buy vero board Useful Tools
Veroboard is a very popular product that has Digital Multimedia
been available for years and because of its Soldering iron
popularity it’s widely available from many Vero board cutter
outlets. You can buy at Screw drivers
https://www.amazon.co.uk/dp/B0093ZEA Loose nose pliers
ZO?tag=wwwmovinghous-
21&linkCode=ogi&th=1&psc=1
Other resources
You can get additional help on vero board at
http://www.bestsoldering.com/veroboard -and-stripboard-resources-tools-andstuff/
And
http://www.zen22142.zen.co.uk/Prac/pra c.html
What Next
If a circuit is marketable, meet a company for mass production, but patent it first.

8.2 Identifying semiconductors

Device numbering system Semiconductor devices are classified by
the manufacturer using a unique part numbering system. There are
many systems in use, but here are some popular schemes in detail;
the European based Proelectron system, the American based JEDEC
system and the
 Japanese based JIS system. Major manufacturers introduce their
own schemes as well.
JEDEC
The JEDEC system,
( J oint Electron Device Engineering Cou ncil. This system has the following format:
digit, letter, serial number, [suffix] Digit: The first digit designates the amount of P-
N junctions in the device. So a device starting with "2" would contain 2 P-N junctions
and would most likely be either a transistor or a FET.
Letter: The letter is always "N", and the remaining figures contain the device serial
number.
Serial number: The serial number runs from 100 to 9999 and indicates nothing
about the transistor.
Suffix: If a suffix is present then this indicates the gain group as below:
A = low gain
B = medium gain
C = high gain
No suffix = ungrouped (any gain). So for example, 1N4001 would be a diode and
3N201 would be a double gate MOSFET.
JEDEC applies to :
1. Diodes
2. Bipolar transistors or Field Effect
Transistors
3. Double Gate MOSFETS, SCR's
4. Opto Couplers
Pro-electron numbering system two letters, [letter], serial number, [suffix]
The 1st letter specifies the semiconductor material :
A Germanium
B Silicon
C Gallium Arsenide
R Compound Materials
The 2nd letter specifies the type of device :
A Diode, low power or signal
B Diode, variable capacitance C Transistor, audio frequency low power
D Transistor, audio frequency power E Diode, tunnel
F Transistor, high frequency low power
G Miscellaneous devices
H Diode, sensitive to magnetism
K Hall effect device
L Transistor, high frequency power
N Photocoupler
P Light detector
Q Light emitter
R Switching device, low power e.g. thyristor, diac, unijunction etc S Transistor, low
power switching T Switching device power, e.g. thyristor, triac, etc.
U Transistor, switching power
W Surface acoustic wave device
X Diode, multiplier, e.g. varactor
Y Diode, rectifying Z Diode, voltage reference Third Letter:
If present this indicates that the device is intended for industrial or professional
rather than commercial applications. It is usually a W,X,Y or Z. Examples- BFY51.
Serial Number:
The serial number runs from 100-9999.

Suffix:
If a suffix is present then this indicates the gain group as below: A = low gain
B = medium gain
C = high gain
No suffix = ungrouped (any gain).
Major Manufacturers
Major manufacturers often produce their own code and numbering scheme for
commercial reasons. The following abbreviations represent some of the larger
semiconductor manufacturers: MJ: Motorolla power, metal case
MJE: Motorolla power, plastic case
MPS: Motorolla low power, plastic case
MRF: Motorolla HF, VHF and microwave transistor
RCA: RCA
RCS: RCS
TIP: Texas Instruments power transistor (platic case)
TIPL: TI planar power transistor
TIS: TI small signal transistor (plastic case)
ZT: Ferranti
ZTX: Ferranti
Common examples include: TIP32A, MJE3055, ZTX302.
Abubakar Muhammad

faqeer4sure@gmail.com