Mikro Işlemciler

CPE303
MICROPROCESSORS
DR. OĞUZHAN MENEMENCIOĞLU
OUTLINE
 Introduction to Course
 The Syllabus
 About course
 Textbook  Introduction to Microprocessors
 General guidelines and policies  Number systems & operations
 Tentative grading  A basic overview of computer architecture
 Let’s Just remember!
 Content
2/90
OUTLINE
 Number Systems
 Digits
 Positional Notation
 Conversion from Decimal
 Conversion to Decimal
 Whole Number Conversion from Decimal
 Converting from a Decimal Fraction
 Binary-Coded Hexadecimal
 Complements
3/90
INTRODUCTION
WEEK 1
THE SYLLABUS
 This is CPE303 \ CME 321 – Microprocessors

 Objective – A basic understanding of computer architecture, specifically microprocessors programing.
5/90
ABOUT COURSE
 Instructor: Dr. Oğuzhan MENEMENCİOĞLU

 e-mail Address: omenemencioglu@karabuk.edu.tr
 Web page: http://oguzhan.menemencioglu.com/2021F_CPE303
 Presentation may be shared in this web page. The sharing notes is not core business of the lecturer. So, you
should take a note for yourself.
 Telegram announcement channel : https://bit.ly/3nxgzTO (In English)
 : https://bit.ly/2GBxhks (Türkçe)
 After this course, immediately join the channel!
6/90
TEXTBOOK
 The Intel Microprocessors, by

Brey, Prentice Hall, 5th Edition.
 The 80x86 IBM
PC and Compatible Computer,
by M. A. Mazidi &. J. G. Mazidi,
Prentice Hall, 4th Edition.
 Computer System Architecture,
by M. Morris Mano, 3th Edition.
USEFUL BOOKS
 Microprocessor Architecture, Programming, and Applications with the 8085 by Ramesh S. Gaonkar, Prentice Hall, 5th
Edition. 7/90
 X86 Tabanlı Mikroişlemci Mimarisi ve Assembly Dili, by Nurettin Topaloğlu, Seçkin Yayıncılık, 3. basım (In Turkish)
GENERAL GUIDELINES AND POLICIES
▪ Generally a quiz each week. Quiz will not necessarily be announced each week. NO MAKEUP QUIZZES
▪ Homework due prior midnight of the next classes after assigned. Homework will be delivered by submitting to
Turnitin. Turnitin will close on due date. NO LATE HOMEWORKS will be accepted by system. No submissions
after due date via email will be graded.
▪ Midterm and Final exam will be announced by deanery.
8/90
TENTATIVE GRADING
 Grading
 Midterm: 40%
 Exam: 85%
 Lab-Assignments-Quiz 15% (Max.)
 Final: 60%
 Exam: 85%
 Lab-Assignments-Quiz 15% (Max.)
 Attendance is required in all course hours and labs for new students.
9/90
LET’S JUST REMEMBER!
TRANSFORMATION HIGH LEVEL COMPUTER LANGUAGES TO MACHINE LANGUAGE
COMPUTER LANGUAGES
 Machine Language – A collection of binary numbers

 Not standardized. There is a different machine language for every processor family.
 Assembly Language - mnemonic codes that corresponds to machine language
instructions.
 Low level: Very close to the actual machine language.
 High-level Languages - Combine algebraic expressions and symbols from English
 High Level : Very far away from the actual machine language
 For example: Fortran, Cobol, C, Prolog, Pascal, C#, Perl, Java.
11/90
EXAMPLE
Memory addresses Machine Language Assembly
Instructions Language
Instructions
00000000 00000000 CLA
00000001 00010101 ADD A
00000010 00010110 ADD B
00000011 00110101 STA A
00000100 01110111 HLT
00000101 ? A?
00000110 ? B? 12/90
13/90
EXAMPLE OF COMPUTER LANGUAGES
char name[40];
C Source Code: printf("Please enter your name\n");
scanf("%s", name);
printf("Hello %s", name);
push offset string "Please enter your name\n"

(41364Ch)
call dword ptr [__imp__printf (415194h)]
add esp,4
lea eax,[name]
push eax
push offset string "%s" (413648h)
Assembly Code: call dword ptr [__imp__scanf (41519Ch)]
add esp,8
lea eax,[name]
push eax
push offset string "Hello %s" (41363Ch)
call dword ptr [__imp__printf (415194h)]
add esp,8
68 4C 36 41 00 FF 15 94 51 41 00 83 C4 04 8D 45 D8
Machine Code: 50 68 48 36 41 00 FF 15 9C 51 41 00 83 C4 08 8D 45
14/90
D8 50 68 3C 36 41 00 FF 15 94 51 41 00 83 C4 08
CONTENT
SYNOPSIS
 The microprocessor is a general-purpose programmable logic device.

 Understanding the microprocessor concepts is crucial in understanding the operation of digital computer.
 This course is an introduction to the basic concept of microprocessor architecture and operation, programming
model, pins configuration and microprocessor interfacing.
 The content of the course is divided into three sections:
 microprocessor architecture,
 programming and
 interfacing input/output.
 The course is designed around the Intel 16-bit microprocessor (8086) and its assembly language.
16/90
OUTCOMES
At the end of the course, student should be:

 Able to understand the basic operation of microprocessor.
 Able to understand the basic concept of microprocessor architecture and its pins configuration.
 Able to understand the machine language programs.
 Able to design and write programs in assembly language.
 Able to understand the basic concept of microprocessor input/output interfacing
17/90
COURSE OVERVIEW
 Introduction to Microcomputers and Microprocessors

 The 8086 Processor Architecture, Internals, Registers,
Flags, Segments
 BIOS and DOS interrupts
 8086 Address Space, Memory, Registers, and data transfers
 Memory and Memory Interfacing for 80x86
 Address Modes
 Input / Output Interface Circuits and
 Basic Instruction Set
Peripheral Devices
 Basic Arithmetic Instructions
 Logical, Shift and Rotate, Data Testing
 The remaining instructions
18/90
LET’S WARM UP!
INITIAL QUESTIONS
 What does the “micro” mean?

 What does the “computer” mean?
 What does the “microprocessor” mean?
20/90
COMPUTER HISTORY
Date Development Name Description

3000BC-500BC Abacus
1642 Calculating Machine Blaise Pascal, a French religious philosopher and mathematician, builds
the first practical mechanical calculating machine.
1673 Multiplication Machine is invented by Leibnitz
1830 Analytical Engine is designed by Charles Babbage
1890 The U.S. Census Bureau adopts the Hollerith Punch Card, Tabulating
Machine and Sorter to compile results of the 1890 census, reducing an
almost 10-year process to 2 ½ years, saving the government a whopping
$5 million. Inventor Herman Hollerith, a Census Bureau statistician,
forms the Tabulating Machine Company in 1896. The TMC eventually
evolved into IBM.
1939 The first semi-electronic digital computing device is constructed by John
21/90
Atanassoff.
COMPUTER HISTORY (CONT.)
1941 German inventor Konrad Zuse produces the Z3 for use in aircraft and
missile design but the German government misses the boat and does
not support him.
1943 English mathematician Alan Turing begins operation of his secret
computer for the British military. It was used by cryptographers to break
secret German military codes. It was the first vacuum tube computer
but its existence was not made public until decades later.
Thomas Harold Flowers built the first digital and programmable
computer called the Colossus
1946 ENIAC-First generation (Electronic Numerical Integrator And Calculator)
electronic computers 30 tons, 8 ft high, 30 ft long
Used thousands tubes & valves
1951 Univac I-First (Universal Automatic Computer), using a Teletype keyboard and printer
22/90
generation electronic for user interaction, and became the first commercially available
computers computer. It could handle both numerical and alphabetic data.
FIRST GENERATION ELECTRONIC COMPUTERS COMPUTER HISTORY (CONT.)
23
1954-59 2nd Generation Transistor invented by William Shockley at Bell Labs
Computers National Bureau of Standards (NBS) introduced its Standards Eastern
Automatic Computer (SEAC)
The first magnetic disk drive designed by Jacob Rabinow
IBM introduced the 702 business computer in 1955
Bendix G-15A small business computer sold for only $45,000, designed
by Harry Huskey of NBS in 1956
1959-71 3rd Generation Jack Kilby of Texas Instruments patented the first integrated circuit (IC)
Computers in Feb. 1959
IBM announced the System/360 all-purpose computer, using 8-bit
character word length (a "byte") in 1964
DEC introduced the first "mini-computer", the PDP-8, in 1968
Development began on ARPAnet, funded by the DOD in 1969
24/90
1971--? 4th Generation Large Scale Integration (LSI) and VLSI
Computers Intel inc introduced the 4-bit 4004, a VLSI of 2300 components in 1971
IBM developed the first true sealed hard disk drive, called the
"Winchester" in 1973
In 1980, IBM signed a contract with the Microsoft Co. of Bill Gates and
Paul Allen and Steve Ballmer to supply an operating system for IBM's
new PC model. Microsoft paid $25,000 to Seattle Computer for the
rights to QDOS that became Microsoft DOS, and Microsoft began its
climb to become the dominant computer company in the world.
Apple Computer introduced the Macintosh personal computer 1984.
? 5th Generation
Computers
25/90
G1 G2 G3 G4
Vacuum Transistor IC Better IC

Tube technology 26/90
Key inventions of generations Quiz 1

HISTORICAL PERSPECTIVE
 The microprocessor revolution began with a bold and innovative approach in logic design pioneered by Intel
engineer Ted Hoff.
 In 1969, Intel was primarily in the business of designing semiconductor memory.
 it introduced a 64-hit bipolar RAM chip that year.
27/90
 Intel coined the term “microprocessor” and in 1971 released the first 4-bit microprocessor as the 4004.
 It was designed with LSI technology;
 It had 2,300 transistors, 640 bytes of memory-addressing capacity, and a 108 kHz clock. Thus, the microprocessor revolution
began with this tiny chip.
 Gordon Moore, cofounder of Intel Corporation, predicted that the number of transistors per integrated circuit
would double every 18 months;
 this came to he known as “Moore’s Law.”
 Just twenty-five years since the invention of the 4004, we have processors that are designed with 15 million transistors, that
can address one terabyte (1 X 1012) of memory, and that can operate at 400 MHz to I.5 GHz frequency (see Table 1.1).
28/90
29/90
MOORE’S LAW
30/90
TERMS
Term Decimal Name Binary

K (kilo) 103 Thousand 210
M (mega) 106 Million 220
G (giga) 109 Billion 230
T (tera) 1012 Trillion 240
P (peta) 1015 Quadrillion 250
31/90
INTRODUCTION TO MICROPROCESSORS
(A FIRST COURSE IN COMPUTER ARCHITECTURE)
WEEK 1
OUTLINE
 Number systems & operations (But, Let’s do it first!)

 To and from base 10
 Addition
 Subtraction (made easy)
 Multiplication
 A basic overview of computer architecture
 The Von Neumann Architecture
 The Harvard architecture
 Microprocessors and Microcontrollers
33/90
NUMBER SYSTEMS & OPERATIONS
WE LIVE IN A BASE 10 WORLD
 Why base 10?

 Could have been base 5 or base 20.
 In base 10 we have 10 symbols
 0123456789
 In any number base system you have n symbols
 Base 2 - 0 1
 Base 8 - 0 1 2 3 4 5 6 7
 Base 16 - 0 1 2 3 4 5 6 7 8 9 A B C D E F
35/90
OTHER NUMBER BASES
 Number system base

 Base 10
 § § § § § § § § § § § § §
 0 1 2 3 4 5 6 7 8 9 10 11 12 13
 Base 2
 § § § § § § § § § §
 0 1 10 11 100 101 110 111 1000 1001 1010
36/90
BASE 5 AND BASE 8
 Base 10
 § § § § § § § § § § § § §
 0 1 2 3 4 5 6 7 8 9 10 11 12 13
 Base 5 (would have digits 0 to 4)

 § § § § § § § § § § § § §
 0 1 2 3 4 10 11 12 13 14 20 21 22 23
 Base 8 (octal)
 § § § § § § § § § § § § §
 0 1 2 3 4 5 6 7 10 11 12 13 14 15 37/90
TO AND FROM BASE
 Base 10 to binary (base 2)

 Number in Base 10  Divide by 2 19/2 = 9 r 1
 1910 = ?  9/2 = 4 r 1
 Procedure (Integer division)  4/2 = 2 r 0
 (In general for any number base you divide by the  2/2 = 1 r 0
number system base and use the remainders)  1/ 2 = 0 r 1
 So the binary of 1910 is 1 0 0 1 1
 More examples?
38/90
ANOTHER
 How about 13910 = ? Number Div 2 Remainder

 Again divine by 2 each time 139 69 1
69 34 1
34 17 0
17 8 1
8 4 0
4 2 0
2 1 0
 So have 1 0 0 0 1 0 1 1
1 0 1
 More Examples?
39/90
BASE 2 TO BASE 10
 In first example have 1 0 0 1 1

 In binary the digits have the following weight
 Value10 = a4 * 24 + a3 * 23 + a2 * 22 + a1 * 21 + a0 * 20
 Value10 = a4 * 16 + a3 * 8 + a2 * 4 + a1 * 2 + a0 * 1
 So here 10011 =?
 10011 = 1 * 16 + 0 * 8 + 0 * 4 + 1 * 2 + 1 * 1
 = 19
40/90
2ND EXAMPLE
 Had 1 0 0 0 1 0 1 1 (written msb (Most Significant Bit) to lsb (Least Significant Bit))
 Value of positions is (lsb to msb) 1,2,4,8,16,32,64,128,256,512,…
 The powers of 2
 Value of the number above
 = 128 + 8 + 2 + 1
 = 139
41/90
BINARY ADDITION
 Follow the same rules as base 10

 carries  1111
 11001 (25)  00111 ( 7)
 + 00010 ( 2)  + 01011 (11)
 11011 (27)  10010 (18)
 More examples?
42/90
BINARY SUBTRACTION
 And we need to borrow – step 1

 Set the problem
 2
 10000 (16)
 10000 (16)
 - 00011 ( 3)
 - 00011 ( 3)
43/90
BINARY SUBRACTION
 The next steps work through to
 To allow answer to be done
44/90
BINARY MULTIPLICATION
1 0 0 0 0 16
 Just like multiplication in base 10 x 0 0 0 1 1 3
1 0 0 0 0
1 0 0 0 0 .
1 1 0 0 0 0 48
 More examples?
45/90
2’S COMPLEMENT
 For 4 bits can represent values -8 to 7 0 0 0 0 0 -0 0 0 0 0

1 0 0 0 1 -1 1 1 1 1
2 0 0 1 0 -2 1 1 1 0
3 0 0 1 1 -3 1 1 0 1
4 0 1 0 0 -4 1 1 0 0
5 0 1 0 1 -5 1 0 1 1
6 0 1 1 0 -6 1 0 1 0
7 0 1 1 1 -7 1 0 0 1
 In general can represent -8 1 0 0 0
 -2n-1  n  2n-1 - 1
46/90
ARITHMETIC WITH 2’S COMPLEMENT
1 1
0 1 0 1 5
1 1 0 1 -3
 Add 5 and -3
0 0 1 0
Carry out = 1
47/90
FINDING THE 2’S COMPLEMENT
 To generate the 2’s complement of n

 Say n is 3
 3 in binary (4 bits) is 0011
 Procedure
 1) Take the 1’s complement, then add 1
 1’s complement – complement all bits
 0011 → 1100 +1 = 1101
 2) Starting at the lsb (rightmost) bit

 Keep the 1st 1 and then complement the rest of the bits. Can easily see on previous example.
48/90
SUBTRACTION VIA 2’S COMPLEMENT
 14 – 6
 (need 5 bits to represent in 2’s complement form)
 01110 – 00110 or
 01110 + 11010 (i.e. 14 + (-6))
 01110
 +11010
 01000 and a carry out of 1 value is 8
49/90
OPERATING IN 2’S COMPLEMENT
 In general can represent

 -2n-1  n  2n-1 - 1
 So with 4 bits can represent values of -8  n  +7
50/90
A BASIC OVERVIEW OF COMPUTER ARCHITECTURE
A BASIC OVERVIEW OF COMPUTER ARCHITECTURE
 For your reference you can find much of this information on Wikipedia.
 But can you trust Wikipedia?
 When was the first computer created?
52/90
EARLY COMPUTING TECHNOLOGY
 Early computing could be traced back to the abacus. When was the abacus in use?
 Around 2700 B.C.
 In the mid 1600’s Blaise Pascal designed and implemented a mechanical calculator.
 Note: Today we use voltage level to represent a logical TRUE and FALSE. There is no reason that the physical
position of a mechanical component cannot do the same thing.
53/90
A LITTLE MORE MODERN
 Charles Babbage 1792-1871

 The Difference Engine
 The Difference Engine 2
 Basically a programmable calculator
 Calculated artillery tables
 The Analytic Engine – a more advanced machine

 Used punch cards for input
 A precursor to the modern computer
 Boole 1815-1864
 Boolean Algebra
54/90
STILL, A LITTLE MORE MODERN
 The von Neumann architecture – 1940s and 50s

 A stored-program computer that uses a central
processing unit and a single separate storage structure
that hold both instructions and data.
55/90
BASIC OPERATION OF ARCHITECTURE
 Instructions are executed in sequence

 First step during execution
 MEM(PC) ➔ IR
 Send contents of PC (Program counter) to memory
 Memory responds with the contents at that address placing

it on the data bus.
 Increment the PC (PC+1->PC)

 The values on the data bus are loaded into the
instruction register (IR)
56/90
DECODE INSTRUCTION AND EXECUTE
 Say the instruction was a load immediate

 This means that the next word in the instruction
stream is the data that we want loaded into the
accumulator
 Operation is now
 MEM(PC)→ Accum
 Also increment the PC
57/90
MORE VON NEUMANN
 Earliest computers had fixed programs – such as a desk calculator

 The von Neumann architecture introduced the concept of a stored program. In fact, in early computers, they
often wrote programs that self modified.
 Self-modifying code is now seen as a very bad programming practice (also, it really isn’t needed).
 von Neumann’s was very familiar with Alan Turing’s (1912-1954) work – the Turing Machine (1936).
 Both von Neumann and Turing wrote papers on stored program computers.
58/90
SOME EARLY VON NEUMANN ARCHITECTURES
 ORDVAC (U of Ill) - 1951

 IAS machine (Princeton) - 1952
 MANIAC I (Las Alamos) - 1952
 ILLIAC (U of Ill) - 1952
 AVIDAC (Argonne National Labs) – 1953
 ORACLE at Oak Ridge Ntl Lab– 1953
 JOHNNIAC at RAND Corp – 1954
 BESK in Stockholm – 1953
 PERM in Munich - 1956
59/90
EARLY MICROPROCESSORS
 The Intel 4004 – 1971

 16-pin DIP (Dual in-line package) package
 92,000 instructions per sec
 10.8 microseconds per instruction
 Processor had a small address space for data and a small address space for instructions
 Designed for use in calculators
 Was the core element for the early electronic calculators – early calculators did basic arithmetic.
 Early microprocessors were often programmed in assembler or machine code. Compilers and many modern
high-level programming languages just didn’t exist.
60/90
THE HARVARD ARCHITECTURE
 In the traditional von Neumann architecture memory holds both programs and data
 In the Harvard Architecture you have separate memory spaces for data and programs. (term that came into use
during the late 1990s)
 This is not really a new concept as the 4004 had separate data and program memory address spaces.
61/90
MICROPROCESSOR VS. MICROCONTROLLER
 Basically a features issue.

 Microprocessor – (the physical processor chip)
 Composed of control unit, register, arithmetic and logic units
 NO Memory, Maybe Timers, No direct external I/O ports
 Does have pins for a data bus and an address bus
 When implemented in a PC, add a keyboard for input, a monitor, a mouse, a printer, etc.
 Microcontroller
 Central core of microprocessor but limited capabilities about registers, memory size, and speed.
 On board memory
 Several Timers
 I/O configurable ports
 In implementation, may or may not have a keyboard, rather a keypad/switches for input or other types of control, often does not have monitor
62/90
SECTION SUMMARY
 Computer are not new!

 The von Neumann architecture
63/90
NUMBER SYSTEMS
INTRODUCTION
 Although we have talked some about number systems, let’s conclude the topic.
65/90
QUIZ 2
 111.1012 = ? Decimal
 127.78 = ? Decimal  .125 = ? Binary
 11111.01112 = ? Decimal  .125 = ? Octal
 7A.CH = ? Decimal  .046875 = ? Hexadecimal
66/90
NUMBER SYSTEMS
 Use of a microprocessor requires working knowledge of numbering systems.

 binary, decimal, and hexadecimal
 This section provides a background for these numbering systems.
 Conversions are described.
 decimal and binary
 decimal and hexadecimal
 binary and hexadecimal
67/90
DIGITS
 Before converting numbers between bases, digits of a number system must be understood.
 First digit in any numbering system is always zero.
 A decimal (base 10) number is constructed with 10 digits: 0 through 9.
 A base 8 (octal) number; 8 digits: 0 through 7.
 A base 2 (binary) number; 2 digits: 0 and 1.
68/90
DIGITS
 If the base exceeds 10, additional digits use letters of the alphabet, beginning with an A.
 a base 12 number contains 10 digits: 0 through 9, followed by A for 10 and B for 11
 Note that a base 10 number does contain a 10 digit.
 a base 8 number does not contain an 8 digit
 Common systems used with computers are decimal, binary, and hexadecimal (base 16).
 many years ago octal numbers were popular
69/90
POSITIONAL NOTATION
 Once digits are understood, larger numbers are constructed using positional notation.
 position to the left of the units position is the tens position
 left of tens is the hundreds position, and so forth
 An example is decimal number 132.
 this number has 1 hundred, 3 tens, and 2 units
 Exponential powers of positions are critical for understanding numbers in other systems.
70/90
POSITIONAL NOTATION
 Exponential value of each position:

 the units position has a weight of 100, or 1
 tens position a weight of 101, or 10
 hundreds position has a weight of 102, or 100
 Position to the left of the radix (number base) point is always the units position in system.
 called a decimal point only in the decimal system
 position to left of the binary point always 20, or 1
 position left of the octal point is 80, or 1
 Any number raised to its zero power is always one (1), or the units position.
71/90
POSITIONAL NOTATION
 Position to the left of the units position always the number base raised to the first power.
 in a decimal system, this is 101, or 10
 binary system, it is 21, or 2
 11 decimal has a different value from 11 binary
 11 decimal has different value from 11 binary.
 decimal number composed of 1 ten, plus 1 unit;
a value of 11 units
 binary number 11 is composed of 1 two, plus 1 unit: a value of 3 decimal units
 11 octal has a value of 9 decimal units
72/90
POSITIONAL NOTATION
 In the decimal system, positions right of the decimal point have negative powers.
 first digit to the right of the decimal point has a value of 10−1, or 0.1.
 In the binary system, the first digit to the right of the binary point has a value of 2−1, or 0.5.
 Principles applying to decimal numbers also generally apply to those in any other system.
 To convert a binary number to decimal, add weights of each digit to form its decimal equivalent.
73/90
CONVERSION FROM DECIMAL
 To convert from any number base to decimal, determine the weights or values of each position of the number.
 Sum the weights to form the decimal equivalent.
74/90
CONVERSION TO DECIMAL
 Conversions from decimal to other number systems more difficult to accomplish.

 To convert the whole number portion of a number to decimal, divide by 1 radix.
 To convert the fractional portion, multiply by the radix.
75/90
WHOLE NUMBER CONVERSION FROM DECIMAL
 To convert a decimal whole number to another number system, divide by the radix and save remainders as
significant digits of the result.
 An algorithm for this conversion:
 divide the decimal number by the radix
(number base)
 save the remainder
(first remainder is the least significant digit)
 repeat steps 1 and 2 until the quotient is zero
76/90
 To convert 10 decimal to binary, divide it by 2.

 the result is 5, with a remainder of 0
 First remainder is units position of the result.
 in this example, a 0
 Next, divide the 5 by 2; result is 2, with a remainder of 1.
 the 1 is the value of the twos (21) position
 Continue division until the quotient is a zero.
 The result is written as 10102 from the bottom to the top.
77/90
 To convert 10 decimal to base 8, divide by 8.

 a 10 decimal is a 12 octal.
 For decimal to hexadecimal, divide by 16.
 remainders will range in value from 0 through 15
 any remainder of 10 through 15 is converted to letters A through F for the hexadecimal number
 decimal number 109 converts to a 6DH
78/90
CONVERTING FROM A DECIMAL FRACTION
 Conversion is accomplished with multiplication by the radix.

 Whole number portion of result is saved as a significant digit of the result.
 fractional remainder again multiplied by the radix
 when the fraction remainder is zero, multiplication ends
 Some numbers are never-ending (repetend).
 a zero is never a remainder
79/90
CONVERTING FROM A DECIMAL FRACTION
 Algorithm for conversion from a decimal fraction:

 multiply the decimal fraction by the radix
(number base).
 save the whole number portion of the result
(even if zero) as a digit; first result is written immediately to the right of the radix point
 repeat steps 1 and 2, using the fractional part of step 2 until the fractional part of step 2 is zero
 Same technique converts a decimal fraction into any number base.
80/90
EXAMPLE 1
 110.1012 = ? Decimal
 Power 22 21 20 2-1 2-2 2-3
 Weight 4 2 1 .5 .25 .125
 Number 1 1 0 . 1 0 1
 Numeric Value 4 + 2 + 0 + .5 + 0 + .125 = 6.625
81/90
EXAMPLE 2
 125.78 = ? Decimal
 Power 82 81 80 8-1
 Weight 64 8 1 .125
 Number 1 2 5 .7
 Numeric Value 64 + 16 + 5 + .875 = 85.875
82/90
EXAMPLE 3
 11011.01112 = ? Decimal
 Power 24 23 22 21 20 2-1 2-2 2-3 2-4
 Weight 16 8 4 2 1 .5 .25 .125 .0625
 Number 1 1 0 1 1 . 0 1 1 1
 Numeric Value 16 + 8 + 0 + 2 + 1 + 0 + .25 + .125 + .0625 = 27.4375
83/90
EXAMPLE 4
 6A.CH = ? Decimal
 Power 161 160 16-1
 Weight 16 1 .0625
 Number 6 A . C
 Number Value 96 + 10 + .75 = 106.75
84/90
EXAMPLE 5 AND 6
 .125 = ? Binary
 .125
 x 2
 0.25 digit is 0
 .125 = ? Octal
 .25  .125
 x 2  x 8
 0.5 digit is 0  1.0 digit is 1
 .5  .125 = 0.18
 x 2
 1.0 digit is 1
 .125 = 0.0012
85/90
EXAMPLE 7
 .046875 = ? Hexadecimal
 . 046875
 x 16
 0.75 digit is 0
 .75
 x 16
 12.0 digit is 12(C)
 . 046875 = 0.0CH
86/90
BINARY-CODED HEXADECIMAL
 Binary-coded hexadecimal (BCH) is a hexadecimal number written each digit is represented by a 4-bit binary
number.
 BCH code allows a binary version of a hexadecimal number to be written in a form easily converted between
BCH and hexadecimal.
 Hexadecimal represented by converting digits to BCH code with a space between each digit.
87/90
COMPLEMENTS
 At times, data are stored in complement form to represent negative numbers.

 Two systems used to represent negative data:
 radix
 radix − 1 complement (earliest)
88/90
RESOURCES
 Microprocessor Architecture, Programming, and Applications with the 8085 by Ramesh S. Gaonkar, Prentice Hall, 5th
Edition.
 Dr. Mehmet Demirer and Dr. Seniha Esen Yuksel, Lecturer Notes of Computers and Programming II, Hacettepe
University, 2014.
 Dr. Masri Ayob, Lecturer Notes of Microprocessor & Interfacing, Universiti Kebangsaan Malaysia, 2009.
 Dr. Ali Ziya Alkar, Lecturer Notes of Microprocessor and Programming II, Hacettepe University, 2016.
 Dr. Joanne E. DeGroat, Lecturer Notes of Introduction to Microcontrollers. Ohio State University, 2014.
 Dr. Joanne E. DeGroat, Lecturer Notes of Introduction to Microcontroller Based Systems. Ohio State University, 2010.
 These slides are designed to accompany The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486
Pentium, Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Architecture, Programming,
and Interfacing, Pearson Education, Inc. , Eighth Edition. Slides copyright 2009 by Barry B. Brey.
 Dr. Ihsan Yassin, Lecturer Notes of Digital Systems & Microprocessors. Universiti Teknologi Mara (UiTM), 2013.
89/90
THANK YOU
OMENEMENCIOGLU@KARABUK.EDU.TR
CPE303
MICROPROCESSORS
OUTLINE
 The Microprocessor-based Personal Computer

System
 The Memory and I/O System
 SATA
 The TPA
 The System Area
 Windows Systems
 I/O Space
 The Microprocessor
 Buses
2/53
THE MICROPROCESSOR-BASED PERSONAL
COMPUTER SYSTEM
WEEK 2
THE MICROPROCESSOR-BASED PERSONAL COMPUTER SYSTEM
 Computers have undergone many changes recently.

 Machines that once filled large areas reduced to small desktop computer systems because
of the microprocessor.
 although compact, they possess computing power only dreamed of a few years ago
4/53
THE MICROPROCESSOR-BASED PERSONAL COMPUTER SYSTEM
 Figure 1–6 shows block diagram of the personal computer.

 Applies to any computer system, from early mainframe computers to the latest systems.
 Diagram composed of three blocks interconnected by buses.
 a bus is the set of common connections that carry the same type of information
5/53
FIGURE 1–6 THE BLOCK DIAGRAM OF A MICROPROCESSOR-BASED COMPUTER SYSTEM.
6/53
TRADITIONAL BLOCK DIAGRAM OF A COMPUTER
7/53
BLOCK DIAGRAM OF A COMPUTER WITH THE MICROPROCESSOR
AS A CPU
8/53
BLOCK DIAGRAM OF A MICROCONTROLLER
9/53
THE MEMORY AND I/O SYSTEM
 Memory structure of all Intel-based personal computers similar.

 Figure 1–7 illustrates memory map of a personal computer system.
 This map applies to any IBM personal computer.
 also any IBM-compatible clones (IBM PC) in existence
10/53
FIGURE 1–7 THE MEMORY MAP OF A PERSONAL COMPUTER.
11/53
 Main memory system divided into three parts:

 TPA (transient program area)
 system area
 XMS (extended memory system)
 Type of microprocessor present determines whether an extended memory system exists.
 First 1M byte of memory often called the real or conventional memory system.
 Intel microprocessors designed to function in this area using real mode operation
12/53
 80286 through the Core2 contain the TPA (640K bytes) and system area (384K bytes).
 also contain extended memory
 often called AT class machines
 The PS/l and PS/2 by IBM are other versions of the same basic memory design.
 Also referred to as ISA (industry standard architecture) or EISA (extended ISA).
 The PS/2 referred to as a micro-channel architecture or ISA system.
 depending on the model number
13/53
 Pentium and ATX class machines feature addition of the PCI (peripheral component interconnect) bus.
 now used in all Pentium through Core2 systems
 Extended memory up to 15M bytes in the 80286 and 80386SX; 4095M bytes in 80486 80386DX, Pentium
microprocessors.
 The Pentium Pro through Core2 computer systems have up to 1M less than 4G (32bit address)or 1 M less than
64G (36 Bit address) of extended memory.
 Servers tend to use the larger memory map.
14/53
 Many 80486 systems use VESA local,VL bus to interface disk and video to the microprocessor at the local bus
level.
 allows 32-bit interfaces to function at same clocking speed as the microprocessor
 recent modification supporting 64-bit data bus
has generated little interest
 ISA/EISA standards function at 8 MHz.
 PCI bus is a 32- or 64-bit bus.
 specifically designed to function with the Pentium through Core2 at a bus speed of 33 MHz.
15/53
 Three newer buses have appeared.

 USB (universal serial bus).
 intended to connect peripheral devices to the microprocessor through a serial data path and a twisted pair of wires
 Data transfer rates are 10 Mbps for USB1.
 Increase to 480 Mbps in USB2.
 Increase to 480X10 Mbps in USB3.
16/53
 AGP (advanced graphics port) for video cards.

 The port transfers data between video card and microprocessor at higher speeds.
 66 MHz, with 64-bit data path
 Latest AGP speed 8X or 2G bytes/second.
 video subsystem change made to accommodate new DVD players for the PC.
17/53
 Latest new buses are serial ATA interface (SATA: Serial Advanced Technology Attachment) for hard disk
drives; PCI Express bus (Peripheral Component Interface) for the video card.
 The SATA bus transfers data from PC to hard disk at rates of 150M bytes per second; 300M bytes for SATA-2.
 serial ATA standard will eventually reach speeds of 450M bytes per second
 PCI Express bus video cards operate at 16X speeds today.
18/53
SATA
 Serial ATA (SATA or Serial Advanced Technology Attachment) is a computer bus interface for
connecting host bus adapters to mass storage devices such as hard disk drives and optical drives. Serial ATA was
designed to replace the older ATA (AT Attachment) standard (also known as EIDE), offering several advantages
over the older parallel ATA (PATA) interface: reduced cable-bulk and cost (7 conductors versus 40), native hot
swapping, faster data transfer through higher signalling rates, and more efficient transfer through an (optional) I/O
queuing protocol.
19/53
THE TPA
 The transient program area (TPA) holds the DOS (disk operating system) operating system; other programs
that control the computer system.
 the TPA is a DOS concept and not really applicable in Windows
 also stores any currently active or inactive DOS application programs
 length of the TPA is 640K bytes
20/53
FIGURE 1–8 THE MEMORY MAP OF THE TPA IN A PERSONAL COMPUTER
 DOS memory map shows how areas of TPA are used

for system programs, data and drivers.
 also shows a large area of memory available for
application programs
 hexadecimal number to left of each area represents the
memory addresses that begin and end each data area
21/53
(Note that this map will vary between systems.)

 Hexadecimal memory addresses number each byte of the memory system.

 a hexadecimal number is a number represented in radix 16 or base 16
 each digit represents a value from 0 to 9 and from A to F
 Often a hexadecimal number ends with an H to indicate it is a hexadecimal value.
 1234H is 1234 hexadecimal
 also represent hexadecimal data as 0xl234 for a 1234 hexadecimal
22/53
 Interrupt vectors access DOS, BIOS (basic I/O system), and applications.
 Areas contain transient data to access I/O devices and internal features of the system.
 these are stored in the TPA so they can be changed as DOS operates
23/53
 The IO.SYS loads into the TPA from the disk whenever an MSDOS system is started.
 IO.SYS contains programs that allow DOS to use keyboard, video display, printer, and other I/O devices often
found in computers.
 The IO.SYS program links DOS to the programs stored on the system BIOS ROM.
24/53
 Drivers are programs that control installable I/O devices.

 mouse, disk cache, hand scanner, CD-ROM memory (Compact Disk Read-Only Memory), DVD (Digital Versatile
Disk; Digital Video Disk), or installable devices, as well as programs
 Installable drivers control or drive devices or programs added to the computer system.
 DOS drivers normally have an extension of .SYS; MOUSE.SYS.
 DOS version 3.2 and later files have an extension of .EXE; EMM386.EXE.
25/53
 Though not used by Windows, still used to execute DOS applications, even with Win XP.
 Windows uses a file called SYSTEM.INI to load drivers used by Windows.
 Newer versions of Windows have a registry added to contain information about the system and the drivers used.
 You can view the registry with the REGEDIT program.
26/53
 COMMAND.COM (command processor) controls operation of the computer from the keyboard when
operated in the DOS mode.
 COMMAND.COM processes DOS commands as they are typed from the keyboard.
 If COMMAND.COM is erased, the computer cannot be used from the keyboard in DOS mode.
 never erase COMMAND.COM, IO.SYS, or MSDOS.SYS to make room for other software
 your computer will not function
27/53
THE SYSTEM AREA
 Smaller than the TPA; just as important.

 The system area contains programs on read-only (ROM) or flash memory, and areas of read/write (RAM)
memory for data storage.
 Figure 1–9 shows the system area of a typical personal computer system.
 As with the map of the TPA, this map also includes the hexadecimal memory addresses of the various areas.
28/53
FIGURE 1–9 THE SYSTEM AREA OF A TYPICAL PERSONAL
COMPUTER.
 First area of system space contains video display

RAM and video control programs on ROM or flash
memory.
 area starts at location A0000H and extends to C7FFFH
 size/amount of memory depends on type of video
display adapter attached
29/53
THE SYSTEM AREA
 Display adapters generally have video RAM at A0000H–AFFFFH.

 stores graphical or bit-mapped data
 Memory at B0000H–BFFFFH stores text data.
 The video BIOS on a ROM or flash memory, is at locations C0000H–C7FFFH.
 contains programs to control DOS video display
 C8000H–DFFFFH is often open or free.
 used for expanded memory system (EMS) in PC or XT system; upper memory system in an AT
30/53
THE SYSTEM AREA
 Expanded memory system allows a 64K-byte page frame of memory for use by applications.
 page frame (D0000H - DFFFFH) used to expand memory system by switching in pages of memory from EMS into this
range of memory addresses
 Locations E0000H–EFFFFH contain cassette BASIC on ROM found in early IBM systems.
 often open or free in newer computer systems
 Video system has its own BIOS ROM at location C0000H.
31/53
THE SYSTEM AREA
 System BIOS ROM is located in the top 64K bytes of the system area (F0000H–FFFFFH).
 controls operation of basic I/O devices connected to the computer system
 does not control operation of video
 The first part of the system BIOS (F0000H–F7FFFH) often contains programs that set up the computer.
 Second part contains procedures that control the basic I/O system.
32/53
WINDOWS SYSTEMS
 Modern computers use a different memory map with Windows than DOS memory maps.
 The Windows memory map in Figure 1–10 has two main areas; a TPA and system area.
 The difference between it and the DOS memory map are sizes and locations of these areas.
33/53
FIGURE 1–10 THE MEMORY MAP USED BY WINDOWS XP.
 TPA is first 2G bytes from locations 00000000H to

7FFFFFFFH.
 Every Windows program can use up to 2G bytes of
memory located at linear addresses 00000000H
through 7FFFFFFFH.
 System area is last 2G bytes from 80000000H
to FFFFFFFFH.
34/53
WINDOWS SYSTEMS
 Memory system physical map is much different.

 Every process in a Windows Vista, XP, or 2000 system has its own set of page tables.
 The process can be located anywhere in the memory, even in noncontiguous pages.
 The operating system assigns physical memory to application.
 if not enough exists, it uses the hard disk for any that is not available
35/53
I/O SPACE
 I/O devices allow the microprocessor to communicate with the outside world.
 I/O (input/output) space in a computer system extends from I/O port 0000H to port FFFFH.
 I/O port address is similar to a memory address
 instead of memory, it addresses an I/O device
 Figure 1–11 shows the I/O map found in many personal computer systems.
36/53
FIGURE 1–11 SOME I/O LOCATIONS IN A TYPICAL PERSONAL COMPUTER.
 Access to most I/O devices should always be made

through Windows, DOS, or BIOS function calls.
 The map shown is provided as a guide to illustrate
the I/O space in the system.
37/53
I/O SPACE
 The area below I/O location 0400H is considered reserved for system devices
 Area available for expansion extends from I/O port 0400H through FFFFH.
 Generally, 0000H - 00FFH addresses main board components; 0100H - 03FFH handles devices located on plug-in
cards or also on the main board.
 The limitation of I/O addresses between 0000 and 03FFH comes from original standards specified by IBM for the
PC standard.
38/53
THE MICROPROCESSOR
 Called the CPU (central processing unit).

 The controlling element in a computer system.
 Controls memory and I/O through connections called buses.
 buses select an I/O or memory device, transfer data between I/O devices or memory and the microprocessor, control I/O
and memory systems
 Memory and I/O controlled via instructions stored in memory, executed by the microprocessor.
39/53
THE MICROPROCESSOR
 Microprocessor performs three main tasks:

 data transfer between itself and the memory or I/O systems
 simple arithmetic and logic operations →processing
 program flow via simple decisions
 Power of the microprocessor is capability to execute billions of millions of instructions per second from a
program or software (group of instructions) stored in the memory system.
 stored programs make the microprocessor and computer system very powerful devices
40/53
THE MICROPROCESSOR
 Another powerful feature is the ability to make simple decisions based upon numerical facts.
 a microprocessor can decide if a number is zero, positive, and so forth
 These decisions allow the microprocessor to modify the program flow, so programs appear to think through
these simple decisions.
41/53
MICROPROCESSORS FABRICATION
1. Microprocessors are
manufactured by etching
transistors into an
empty silicon wafer.
3. Once proper leads
2. The etching process and connections are 42/53
is done in a clean room by attached, the microprocessor

using machines. is ready to be used.
BUSES
 A common group of wires that interconnect components in a computer system.

 Transfer address, data, & control information between microprocessor, memory and I/O.
 Three buses exist for this transfer of information: address, data, and control.
 Figure 1–12 shows how these buses interconnect various system components.
43/53
FIGURE 1–12 THE BLOCK DIAGRAM OF A COMPUTER SYSTEM SHOWING THE ADDRESS, DATA, AND
CONTROL BUS STRUCTURE.
44/53
BUSES
 The address bus requests a memory location from the memory or an I/O location from the I/O devices.
 if I/O is addressed, the address bus contains a 16-bit I/O address from 0000H through FFFFH.
 if memory is addressed, the bus contains a memory address, varying in width by type of
microprocessor.
 64-bit extensions to Pentium provide 40 address pins, allowing up to 1T (240 .=.1012) byte of memory to be
accessed.
45/53
BUSES
 The data bus transfers information between the microprocessor and its memory and I/O address space.
 Data transfers vary in size, from 8 bits wide to 64 bits wide in various Intel microprocessors.
 8088 has an 8-bit data bus that transfers 8 bits of data at a time
 8086, 80286, 80386SL, 80386SX, and 80386EX transfer 16 bits of data
 80386DX, 80486SX, and 80486DX, 32 bits
 Pentium through Core2 microprocessors transfer 64 bits of data
46/53
BUSES
 Advantage of a wider data bus is speed in applications using wide data.

 Figure 1–13 shows memory widths and sizes of 8086 through Core2 microprocessors.
 In all Intel microprocessors family members, memory is numbered by byte.
 Pentium through Core2 microprocessors contain a 64-bit-wide data bus.
47/53
FIGURE 1–13A THE PHYSICAL MEMORY SYSTEMS OF THE 8086 THROUGH THE CORE2
MICROPROCESSORS.
48/53
FIGURE 1–13B THE PHYSICAL MEMORY SYSTEMS OF THE 8086 THROUGH THE CORE2
MICROPROCESSORS.
49/53
BUSES
 Control bus lines select and cause memory or I/O to perform a read or write operation.
 In most computer systems, there are four control bus connections:
 MRDC (Memory ReaD Control)
 MWTC (Memory WriTe Control)
 IORC (I/O Read Control)
 IOWC (I/O Write Control).
 overbar indicates the control signal is active-low; (active when logic zero appears on control line)
 if IOWC = 0, the microprocessor is writing data from the data bus to an I/O device whose address appears on the
address bus.
50/53
BUSES
 The microprocessor reads a memory location by sending the memory an address through the address bus.
 Next, it sends a memory read control signal to cause the memory to read data.
 Data read from memory are passed to the microprocessor through the data bus.
 Whenever a memory write, I/O write, or I/O read occurs, the same sequence ensues.
51/53
RESOURCES
Pentium, Pentium Pro Processor, Pentium II, Pentium, 4, and Core2 with 64-bit Extensions Architecture,
Programming, and Interfacing, Pearson Education, Inc. , Eighth Edition. Slides copyright 2009 by Barry B. Brey.
 Microprocessor Architecture, Programming, and Applications with the 8085 by Ramesh S. Gaonkar, Prentice Hall,
5th Edition.
52/53
THANK YOU
CPE303
MICROPROCESSORS
OUTLINE
 Computer Data Formats

 ASCII and Unicode Data  CPU Execution Cycle
 BCD (Binary-Coded Decimal) Data  Fetch, Decode, Execute
 Byte-Sized Data  Fetch
 Word-Sized Data  Decode
 Doubleword-Sized Data  Execute
 Real Numbers
2/37
COMPUTER DATA FORMATS
COMPUTER DATA FORMATS
 Successful programming requires a precise understanding of data formats.

 Commonly, data appear as ASCII, Unicode, BCD, signed and unsigned integers, and floating-point numbers (real
numbers).
 Other forms are available but are not commonly found.
4/37
ASCII AND UNICODE DATA
 ASCII (American Standard Code for Information Interchange) data represent alphanumeric characters in
computer memory.
 Standard ASCII code is a 7-bit code.
 eighth and most significant bit used to hold parity
 If used with a printer, most significant bits are 0 for alphanumeric printing; 1 for graphics.
 In PC, an extended ASCII character set is selected by placing 1 in the leftmost bit.
5/37
 Extended ASCII characters store:

 some foreign letters and punctuation
 Greek & mathematical characters
 box-drawing & other special characters
 Extended characters can vary from one printer to another.
 ASCII control characters perform control functions in a computer system.
 clear screen, backspace, line feed, etc.
 Enter control codes through the keyboard.
 hold the Control key while typing a letter
6/37
 Many Windows-based applications use the Unicode system to store alphanumeric data.
 stores each character as 16-bit data
 Codes 0000H–00FFH are the same as standard ASCII code.
 Remaining codes, 0100H–FFFFH, store all special characters from many character sets.
 Allows software for Windows to be used in many countries around the world.
 For complete information on Unicode, visit: http://www.unicode.org
7/37
BCD (BINARY-CODED DECIMAL) DATA
 The range of a BCD digit extends from 00002 to 10012, or 0–9 decimal, stored in two forms:
 Stored in packed form:
 packed BCD data stored as two digits per byte;
 used for BCD addition and subtraction in the instruction set of the microprocessor
 Stored in unpacked form:
 unpacked BCD data stored as one digit per byte
 returned from a keypad or keyboard
8/37
BCD (BINARY-CODED DECIMAL) DATA
 Applications requiring BCD data are point-of-sales terminals.

 also devices that perform a minimal amount of simple arithmetic
 If a system requires complex arithmetic, BCD data are seldom used.
 there is no simple and efficient method of performing complex BCD arithmetic
9/37
BYTE-SIZED DATA
 Stored as unsigned and signed integers.

 Difference in these forms is the weight of the leftmost bit position.
 value 128 for the unsigned integer
 minus 128 for the signed integer
 In signed integer format, the leftmost bit represents the sign bit of the number.
 also a weight of minus 128
10/37
FIGURE 1–14 THE UNSIGNED AND SIGNED BYTES ILLUSTRATING THE WEIGHTS OF EACH BINARY-BIT
POSITION.
11/37
BYTE-SIZED DATA
 Unsigned integers range 00H to FFH (0–255)

 Signed integers from −128 to 0 to + 127.
 Negative signed numbers represented in this way are stored in the two’s complement form.
 Evaluating a signed number by using weights of each bit position is much easier than the act of two’s
complementing a number to find its value.
 especially true in the world of calculators designed for programmers
12/37
WORD-SIZED DATA
 A word (16-bits) is formed with two bytes of data.

 The least significant byte always stored in the lowest-numbered memory location.
 Most significant byte is stored in the highest.
 This method of storing a number is called the little endian format.
13/37
FIGURE 1–15 THE STORAGE FORMAT FOR A 16-BIT WORD IN (A) A REGISTER AND (B) TWO BYTES OF
MEMORY.
14/37
FIGURE 1–16 THE STORAGE FORMAT FOR A 32-BIT WORD IN (A) A REGISTER AND (B) 4 BYTES OF
MEMORY.
15/37
WORD-SIZED DATA
 Alternate method is called the big endian format.

 Numbers are stored with the lowest location containing the most significant data.
 Not used with Intel microprocessors.
 The big endian format is used with the Motorola family of microprocessors.
16/37
DOUBLEWORD-SIZED DATA
 Doubleword-sized data requires four bytes

of memory because it is a 32-bit number.
 appears as a product after a multiplication
 also as a dividend before a division
 Define using the assembler directive define doubleword(s), or DD.
 also use the DWORD directive in place of DD
17/37
REAL NUMBERS
 Since many high-level languages use Intel microprocessors, real numbers are often encountered.
 A real, or a floating-point number contains two parts:
 a mantissa, significant, or fraction
 an exponent.
 A 4-byte number is called single-precision.
 The 8-byte form is called double-precision.
18/37
FIGURE 1–17 THE FLOATING-POINT NUMBERS IN (A) SINGLE-PRECISION USING A BIAS OF 7FH AND (B)
DOUBLE-PRECISION USING A BIAS OF 3FFH.
19/37
REAL NUMBERS
 The assembler can be used to define real numbers in single- & double-precision forms:
 use the DD directive for single-precision 32-bit numbers
 use define quadword(s), or DQ to define 64-bit double-precision real numbers
 Optional directives (導引) are REAL4, REAL8, and REAL10.
 for defining single-, double-, and extended precision real numbers
20/37
CPU EXECUTION CYCLE
CPU EXECUTION CYCLE
 CPU executes instructions in endless fetch, decode, execute cycles.

 It only knows how to do three things:
 Fetch instructions from somewhere.
 Analyze instruction, get more data if necessary.
 Execute instruction.
 Keeps track of instruction using Program Counter (PC):
 Tells CPU location of next instruction.
22/37
FETCH, DECODE, EXECUTE
Reset
Fetch
Decode
Execute
23/37
FETCH – STEP 1
CPU Memory
$1000 Instruction #1
Control
Instruction Register
$1004 Empty
Data Registers
$1005 Empty
CPU gets $1006 Empty
instruction $1007 Data #1
address from PC $1008 Data #2

$1009 Data #3
Program Counter
$1000 24/37
FETCH – STEP 2
CPU Memory
Address Bus
Control $1000 $1001 Instruction #1
$1004 Empty
Data Registers
$1005 Empty
CPU outputs $1006 Empty
instruction address $1007 Data #1
through Address $1008 Data #2
Bus $1009 Data #3

Program Counter
25/37
$1000
FETCH – STEP 3
CPU Memory
Data Bus
Control Instruction #1 $1001 Instruction #1
$1004 Empty
Data Registers
$1005 Empty
Memory gets the $1006 Empty
instruction and $1007 Data #1
sends in to CPU $1008 Data #2
using Data Bus. $1009 Data #3

Program Counter
$1000 26/37
FETCH – STEP 4
CPU Memory
Control
Instruction #1 $1003 Instruction #2
$1004 Empty
Data Registers
$1005 Empty
CPU stores $1006 Empty
instruction in $1007 Data #1
Instruction Register $1008 Data #2

$1009 Data #3
Program Counter
27/37
$1000
FETCH – STEP 5
CPU Memory
Control
$1004 Empty
Data Registers
$1005 Empty
After instruction has $1006 Empty
been loaded, CPU $1007 Data #1
updates Program $1008 Data #2
Counter. $1009 Data #3

Program Counter
28/37
$1002
DECODE – STEP 1
CPU Memory
Control
$1004 Empty
Data Registers
$1005 Empty
CPU analyzes $1006 Empty
instructions before $1007 Data #1
executing it. $1008 Data #2

$1009 Data #3
Program Counter
$1002
Type of instruction. 29/37
Does the instruction require any data to perform calculations?
Where are the data located?
EXECUTE – STEP 1
CPU Memory
Address Bus
$1004 Empty
Data Registers
$1005 Empty
If instruction $1006 Empty
requires data from $1007 Data #1
memory, data $1008 Data #2
address is placed $1009 Data #3

Program Counter
$1002 on address bus. 30/37

EXECUTE – STEP 2
CPU Memory
Data Bus
Control Data #1 $1001 Instruction #1
$1004 Empty
Data Registers
$1005 Empty
Memory gets the $1006 Empty
instruction and $1007 Data #1
sends in to CPU $1008 Data #2
using Data Bus. $1009 Data #3

Program Counter
$1002
31/37
EXECUTE – STEP 3
CPU Memory
Control
$1004 Empty
Data Registers
$1005 Empty
Data #1
CPU puts data $1006 Empty
inside internal data $1007 Data #1
registers and $1008 Data #2
execute instructions. $1009 Data #3

Program Counter
$1002
32/37
EXECUTE – STEP 4
CPU Memory
Address Bus
Data Bus $1004 Empty

Data Registers
$1005 Empty
Data #1 Result #1
$1006 Empty
Result #1
$1007 Data #1
$1008 Data #2
If instruction wants to $1009 Data #3

Program Counter
$1002 write data to memory, 33/37

CPU puts its data and
address on the bus.
EXECUTE – STEP 5
CPU Memory
Control
$1004 Empty
Data Registers
$1005 Result #1
Data #1
$1006 Empty
Result #1
$1007 Data #1
Memory receives
$1008 Data #2
instructions and puts
$1009 Data #3
Program Counter data in the location.
34/37
$1002
ASSIGNMENT
 What is a Turing machine?

 HW1 - Write up what a Turing machine is and how a Turing Machine executes a program.
 Write up to 500 words.
 Due dates on next course.
 There are many sources for this assignment
 Google web search
 Wikipedia
 Library
35/37
RESOURCES
 Dr. Joanne E. DeGroat, Lecturer Notes of Introduction to Microcontroller Based Systems. Ohio State University,
2010.
36/37
THANK YOU
CPE303
MICROPROCESSORS
WEEK 4
OUTLINE
 Internal Microprocessor Architecture

 Internal Block Diagram of CPU
 Intel 8086 Pin Diagram
 Internal block diagram of the 8086  Introduction to Instructions Set
 The Programming Model  MOV instruction
 Multipurpose Registers  ADD instruction
 Special-Purpose Registers
 List of Each Flag bit, with a brief description of function.
 Segment Registers
3/42
INTERNAL MICROPROCESSOR ARCHITECTURE
INTERNAL BLOCK DIAGRAM OF CPU
5/42
INTEL 8086 PIN DIAGRAM
6/42
PIPELINED VS. NONPIPELINED EXECUTION
7/42
INTERNAL BLOCK DIAGRAM OF THE 8086
8/42
 Before a program is written or instruction investigated, internal configuration of the microprocessor must be
known.
 In a multiple core microprocessor each core contains the same programming model.
 Each core runs a separate task or thread simultaneously.
9/42
 A thread consists of a program counter, a register set,

and a stack space.
 A task shares with peer threads its code section,
data section, and operating system resources
10/42
THE PROGRAMMING MODEL
 8086 through Core2 considered program visible.

 registers are used during programming and are specified by the instructions
 Other registers considered to be program invisible.
 not addressable directly during applications programming
11/42
 80286 and above contain program-invisible registers to control and operate protected memory.
 and other features of the microprocessor
 80386 through Core2 microprocessors contain full 32-bit internal architectures.
 8086 through the 80286 are fully upward-compatible to the 80386 through Core2.
 Figure 2–1 illustrates the programming model 8086 through Core2 microprocessor.
 including the 64-bit extensions
12/42
FIGURE 2–1 The programming model of the
8086 through the core2 microprocessor
including the 64-bit extensions.
13/42
MULTIPURPOSE REGISTERS
 RAX - a 64-bit register (RAX), a 32-bit register (accumulator) (EAX), a 16-bit register (AX), or as either of
two 8-bit registers (AH and AL).
 The accumulator is used for instructions such as multiplication, division, and some of the adjustment instructions.
 Intel plans to expand the address bus to 52 bits to address 4P (252~1015 =peta) bytes of memory.
14/42
ADDRESS SPACE (MAIN MEMORY: RAM)
 Address bus:16 bit →Address Space:64 Kbytes (216 = 65536 = 64 * 1024)

 Address bus:20 bit →Address Space:1 Mbytes (220 = 1.048.576 =1 * 1024 * 1024)
 Address bus:32 bit →Address Space:4 Gbytes (232 = 4.294.967.296 =4 * 1024 * 1024 * 1024)
 Address bus:34 bit →Address Space:16GBytes (234 = 17.179.869.184 = 16 * 1024 * 1024 * 1024)
 Address bus:52 bit →Address Space:1015 Bytes (252 = 4.503.599.627.370.496 ~ 1015 = 1.000.000.000.000.000)
15/42
 RBX, addressable as RBX, EBX, BX, BH, BL.

 BX register (base index) sometimes holds offset address of a location in the memory system in all versions of the
microprocessor
 RCX, as RCX, ECX, CX, CH, or CL.
 a (count) general-purpose register that also holds the count for various instructions
 RDX, as RDX, EDX, DX, DH, or DL.
 a (data) general-purpose register
 holds a part of the result from a multiplication or part of dividend before a division
16/42
 RBP, as RBP, EBP, or BP.

 points to a memory (base pointer) location for memory data transfers
 RDI addressable as RDI, EDI, or DI.
 often addresses (destination index) string destination data for the string instructions
 RSI used as RSI, ESI, or SI.
 the (source index) register addresses source string data for the string instructions
 like RDI, RSI also functions as a general-purpose register
17/42
 R8 - R15 found in the Pentium 4 and Core2 if 64-bit extensions are enabled.
 data are addressed as 64-, 32-, 16-, or 8-bit sizes and are of general purpose
 Most applications will not use these registers until 64-bit processors are common.
 the 8-bit portion is the rightmost 8-bit only
 bits 8 to 15 are not directly addressable as a byte
18/42
SPECIAL-PURPOSE REGISTERS
 Include RIP, RSP, and RFLAGS

 segment registers include CS, DS, ES, SS, FS, and GS
 RIP addresses the next instruction in a section of memory.
 defined as (instruction pointer) a code segment
 RSP addresses an area of memory called the stack.
 the (stack pointer) stores data through this pointer
19/42
 RFLAGS indicate the condition of the microprocessor and control its operation.
 Figure 2–2 shows the flag registers of all versions of the microprocessor.
 Flags are upward-compatible from the 8086/8088 through Core2 .
 The rightmost five and the overflow flag are changed by most arithmetic and logic operations.
 although data transfers do not affect them
20/42
FIGURE 2–2 THE EFLAG AND FLAG REGISTER COUNTS FOR THE
ENTIRE 8086 AND PENTIUM MICROPROCESSOR FAMILY.
 Flags never change for any data

transfer or program control
operation.
 Some of the flags are also used to
control features found in the
microprocessor.
21/42
 Flag bits, with a brief description of function.

 C (carry) holds the carry after addition or borrow after subtraction.
 also indicates error conditions
 P (parity) is the count of ones in a number expressed as even or odd. Logic 0 for odd parity; logic 1 for even
parity.
 if a number contains three binary one bits, it has odd parity
 if a number contains no one bits, it has even parity
22/42
LIST OF EACH FLAG BIT, WITH A BRIEF DESCRIPTION OF FUNCTION.
 C (carry) holds the carry after addition or borrow after subtraction.

 also indicates error conditions
 P (parity) is the count of ones in a number expressed as even or odd. Logic 0 for odd parity; logic 1 for even
parity.
 if a number contains three binary one bits, it has odd parity; If a number contains no one bits, it has even parity
23/42
 A (auxiliary carry) holds the carry (half-carry) after addition or the borrow after subtraction between bit
positions 3 and 4 of the result.
 Z (zero) shows that the result of an arithmetic or logic operation is zero.
 S (sign) flag holds the arithmetic sign of the result after an arithmetic or logic instruction executes.
 T (trap) The trap flag enables trapping through an on-chip debugging feature.
24/42
 I (interrupt) controls operation of the INTR (interrupt request) input pin.

 D (direction) selects increment or decrement mode for the DI and/or SI registers.
 O (overflow) occurs when signed numbers are added or subtracted.
 an overflow indicates the result has exceeded the capacity of the machine
25/42
SEGMENT REGISTERS
 Generate memory addresses when combined with other registers in the microprocessor.
 Four or six segment registers in various versions of the microprocessor.
 A segment register functions differently in real mode than in protected mode.
 Following is a list of each segment register, along with its function in the system.
26/42
SEGMENT REGISTERS
 CS (code) segment holds code (programs and procedures) used by the microprocessor.
 DS (data) contains most data used by a program.
 Data are accessed by an offset address or contents of other registers that hold the offset address
 ES (extra) an additional data segment used by some instructions to hold destination data.
27/42
SEGMENT REGISTERS
 SS (stack) defines the area of memory used for the stack.

 stack entry point is determined by the stack segment and stack pointer registers
 the BP register also addresses data within the stack segment
28/42
INTRODUCTION TO INSTRUCTIONS SET
FIGURE 3–1 THE MOV INSTRUCTION SHOWING THE SOURCE, DESTINATION, AND
DIRECTION OF DATA FLOW.
30/42
MOV INSTRUCTION
 MOVE destination, source ; Move the source operand to the destination
31/42
MOV INSTRUCTION
 MOV CL,55H  ;move 55H into register CL

 MOV DL,CL  ;copy the contents of CL into DL  (now DL=CL=55H)
 MOV AH,DL  ;copy the contents of DL into AH  (now AH=DL=55H)
 MOV AL,AH  ;copy the contents of AH into AL  (now AL=AH=55H)
 MOV BH,CL  ;copy the contents of CL into BH  (now BH=CL=55H)
 MOV CH,BH  ;copy the contents of BH into CH  (now CH=BH=55H)
32/42
MOV INSTRUCTION (CONT.)
 MOV CX,468FH  ;move 468FH into CX (now CH=46,CL=8F)

 MOV AX,CX  ;copy contents of CX to AX (now AX=CX=468FH)
 MOV DX,AX  ;copy contents of AX to DX (now DX=AX=468FH)
 MOV BX,DX  ;copy contents of DX to BX (now BX=DX=468FH)
 MOV DI,BX  ;now DI=BX=468FH
 MOV SI,DI  ;now SI=DI=468FH
 MOV DS,SI  ;now DS=SI=468FH
 MOV BP,DI  ;now BP=DI=468FH
33/42
MOV INSTRUCTION (CONT.)
 MOV AX,58FCH  ;move 58FCH into AX  (LEGAL)

 MOV DX,6678H  ;move 6678H into DX  (LEGAL)
 MOV SI,924BH  ;move 924BH into SI  (LEGAL)
 MOV BP,2459H  ;move 2459H into BP  (LEGAL)
 MOV DS,2341H  ;move 2341H into DS  (ILLEGAL)
 MOV CX,8876H  ;move 8876H into CX  (LEGAL)
 MOV CS,3F47H  ;move 3F47H into CS  (ILLEGAL)
 MOV BH,99H  ;move 99H into BH  (LEGAL)
34/42
ADD INSTRUCTION
 ADD destination, source ; ADD the source operand to the destination
35/42
ADD INSTRUCTION
 MOV AL,25H  ;move 25 into AL

 MOV BL,34H  ;move 34 into BL
 ADD AL,BL  ;AL= AL+ BL  AL = 59H (25H + 34H = 59H)
36/42
ADD INSTRUCTION (CONT.)
 MOV DH,25H  ;move 25 into DH

 MOV CL,34H  ;move 34 into CL
 ADD DH,CL  ;add CL to DH: DH = DH + CL
37/42
 MOV DH,25H  ;Ioad one operand into DH

 What is the difference?
 ADD DH,34H  ;add the second operand to DH
38/42
 MOV AX,34EH  ;move 34EH into AX

 MOV DX,6A5H  ;move 6A5H into DX
 ADD DX,AX  ;add AX to DX: DX = DX + AX  DX = 9F3H (34EH + 6A5H = 9F3H)
39/42
 MOV CX,34EH  ;load 34EH into CX

 ADD CX,6A5H  ;add 6A5H to CX  (now CX=9F3H)
40/42
RESOURCES
 The 80x86 IBM PC and Compatible Computer, by M.A. Mazidi &. J. G. Mazidi, Prentice Hall, 4th Edition.
41/42
THANK YOU
CPE303
MICROPROCESSORS
WEEK 5-6
OUTLINE
 Data Addressing Modes

 Introduction To Program Segments  Register Addressing
 Segments and Offsets  Immediate Addressing
 Logical Address  Direct Data Addressing
 Physical Address  Register Indirect Addressing
 Base-Plus-Index Addressing
3/66
INTRODUCTION TO PROGRAM SEGMENTS
SEGMENTS AND OFFSETS
 All real mode memory addresses must consist of a segment address plus an offset address.
 segment address defines the beginning address of any 64K-byte memory segment
 offset address selects any location within the 64K byte memory segment
 Figure 2–3 shows how the segment plus offset addressing scheme selects a memory location.
5/66
FIGURE 2–3 THE REAL MODE MEMORY-ADDRESSING SCHEME,
USING A SEGMENT ADDRESS PLUS AN OFFSET.
 this shows a memory segment beginning at 10000H,

ending at location IFFFFH
 64K bytes in length
 also shows how an offset address, called a

displacement, of F000H selects location
1F000H in the memory
6/66
SEGMENTS AND OFFSETS
 Once the beginning address is known, the ending address is found by adding FFFFH.
 because a real mode segment of memory is64K in length
 The offset address is always added to the segment starting address to locate the data.
 Segment and offset address is sometimes written as 1000:2000.
 a segment address of 1000H; an offset of 2000H
7/66
DEFAULT SEGMENT AND OFFSET REGISTERS
 The microprocessor has rules that apply to segments whenever memory is addressed.
 these define the segment and offset register combination
 The code segment register defines the start of the code segment.
 The instruction pointer locates the next instruction within the code segment.
8/66
DEFAULT SEGMENT AND OFFSET REGISTERS
 Another of the default combinations is the stack.

 stack data are referenced through the stack segment at the memory location addressed by either the stack pointer (SP/ESP)
or the pointer (BP/EBP)
 Figure 2–4 shows a system that contains four memory segments.
 a memory segment can touch or overlap if 64K bytes of memory are not required for a segment
9/66
FIGURE 2–4 A MEMORY SYSTEM SHOWING THE PLACEMENT OF
FOUR MEMORY SEGMENTS.
 think of segments as Windows that can be moved

over any area of memory to access data or code
 a program can have more than four or six segments,
 but only access four or six segments at a time
10/66
FIGURE 2–5 AN APPLICATION PROGRAM CONTAINING A CODE, DATA, AND
STACK SEGMENT LOADED INTO A DOS SYSTEM MEMORY.
 a program placed in memory by DOS is loaded in

the TPA at the first available area of memory above
drivers and other TPA programs
 area is indicated by a free-pointer maintained by
DOS
 program loading is handled automatically by the
program loader within DOS
11/66
LOGICAL ADDRESS AND PHYSICAL ADDRESS
# Description CS IP
1. Step Take the Code Segment 2 5 0 0 : 9 5 F 3
2. Step Shift left CS 2 5 0 0 0
3. Step Add IP 2 E 5 F 3
 The logical address : 2500:95F3

 Offset address : 95F3
 The physical address : 2E5F3
 The lower range : 25000 (25000 + 0000)
 The upper range
of the code segment : 34FFF (25000 + FFFF)
12/66
LOGICAL ADDRESS AND PHYSICAL ADDRESS
# Description CS IP
1. Step Take the Code Segment 2 4 F 6 : 6 3 4 A
2. Step Shift left CS 2 4 F 6 0
3. Step Add IP 2 B 2 A A
 The logical address : 24F6:634A

 Offset address : 634A
 The physical address : 2B2AA
 The lower range : 24F60 (24F60 + 0000)
 The upper range
of the code segment : 34F5F (24F60 + FFFF)13/66
LOGICAL ADDRESS VS. PHYSICAL ADDRESS IN THE CODE SEGMENT
Logical address CS:IP Machine language opcode and operand Assembly language mnemonics and operand
1132:0100 B057 MOV AL,57H
1132:0102 B686 MOV OH,86H
1132:0104 B272 MOV OL,72H
1132:0106 8901 MOV CX,OX
1132:0108 88C7 MOV BH,AL
1132:010A B39F MOV BL,9FH
1132:010C B420 MOV AH,20H
1132:010E 0100 ADD AX,OX
1132:0110 0109 ADD CX,BX
1132:0112 05351F ADD AX,1F35H 14/66
DATA SEGMENT
 MOV AL,00H ;initialize AL

 ADD AL,25H ;add 25H to AL
 ADD AL,1FH ;add 1 FH to AL
15/66
DATA SEGMENT
 MOV AL,0 ;clear AL

 DS:0200 = 25
 ADD AL,[0200] ;add the contents of DS:200 to AL
 DS:0201 = 12
 DS:0202 = 15
 DS:0203 = 1F
 DS:0204 = 26
Although this program is an improvement over the preceding one, it can be improved even further. 16/66
DATA SEGMENT
 MOV AL,0 ;initialize AL

 MOV BX,0200H ;BX points to the offset addr of first byte
 ADD AL,[BX] ;add the first byte to AL
 INC BX ;increment BX to point to the next byte
 ADD AL,[BX] ;add the next byte to AL
 INC BX ;increment the pointer
 ADD AL,[BX] ;add the next byte to AL
 INC BX ;increment the pointer
 ADD AL,[BX] ;add the last byte to AL
17/66
DATA ADDRESSING MODES
 MOV instruction is a common and flexible instruction.

 provides a basis for explanation of data-addressing modes
 Figure 3–1 illustrates the MOV instruction and defines the direction of data flow.
 Source is to the right and destination the left, next to the opcode MOV.
 an opcode, or operation code, tells the microprocessor which operation to perform
19/66
FIGURE 3–1 THE MOV INSTRUCTION SHOWING THE SOURCE, DESTINATION, AND
DIRECTION OF DATA FLOW.
20/66
 Figure 3–2 shows all possible variations of the data-addressing modes using MOV.
 These data-addressing modes are found with all versions of the Intel microprocessor.
 except for the scaled-index-addressing mode, found only in 80386 through Core2
 RIP relative addressing mode is not illustrated.
 only available on the Pentium 4 and Core2in the 64-bit mode
21/66
22/66
FIGURE 3–2 8086–CORE2 DATA-ADDRESSING MODES.

REGISTER ADDRESSING
 The most common form of data addressing.

 once register names learned, easiest to apply.
 The microprocessor contains these 8-bit register names used with register addressing: AH, AL, BH, BL, CH, CL,
DH, and DL.
 16-bit register names: AX, BX, CX, DX, SP, BP, SI, and DI.
23/66
REGISTER ADDRESSING
 In 80386 & above, extended 32-bit register names are: EAX, EBX, ECX, EDX, ESP, EBP, EDI, and ESI.
 64-bit mode register names are: RAX, RBX, RCX, RDX, RSP, RBP, RDI, RSI, and R8 through R15.
 Important for instructions to use registers that are the same size.
 never mix an 8-bit \with a 16-bit register, an 8- or a 16-bit register with a 32-bit register
 this is not allowed by the microprocessor and results in an error when assembled
24/66
FIGURE 3–3 THE EFFECT OF EXECUTING THE MOV BX, CX INSTRUCTION AT THE POINT JUST BEFORE
THE BX REGISTER CHANGES. NOTE THAT ONLY THE RIGHTMOST 16 BITS OF REGISTER EBX CHANGE.
25/66
REGISTER ADDRESSING
 Figure 3–3 shows the operation of the MOV BX, CX instruction.

 The source register’s contents do not change.
 the destination register’s contents do change
 The contents of the destination register or destination memory location change for all instructions except the
CMP and TEST instructions.
 The MOV BX, CX instruction does not affect the leftmost 16 bits of register EBX.
26/66
REGISTER ADDRESSING
 MOV BX,DX ;copy the contents of DX into BX

 MOV ES,AX ;copy the contents of AX into ES
 ADD AL,BH ;add the contents of BH to contents of AL
27/66
IMMEDIATE ADDRESSING
 Term immediate implies that data immediately follow the hexadecimal opcode in the memory.
 immediate data are constant data
 data transferred from a register or memory location are variable data
 Immediate addressing operates upon a byte or word of data.
 Figure 3–4 shows the operation of a MOV EAX,13456H instruction.
28/66
FIGURE 3–4 THE OPERATION OF THE MOV EAX,13456H INSTRUCTION. THIS
INSTRUCTION COPIES THE IMMEDIATE DATA (13456H) INTO EAX.
 As with the MOV instruction illustrated in Figure 3–3, the source data overwrites the
destination data.
29/66
 In symbolic assembly language, the symbol # precedes immediate data in some assemblers.
 MOV AX,#3456H instruction is an example
 Most assemblers do not use the # symbol, but represent immediate data as in the MOV AX,3456H instruction.
 an older assembler used with some Hewlett-Packard logic development does, as may others
 in this text, the # is not used for immediate data
30/66
 The symbolic assembler portrays immediate data in many ways.

 The letter H appends hexadecimal data.
 If hexadecimal data begin with a letter, the assembler requires the data start with a 0.
 to represent a hexadecimal F2, 0F2H is used in assembly language
 Decimal data are represented as is and require no special codes or adjustments.
 an example is the 100 decimal in the MOV AL,100 instruction
31/66
 An ASCII-coded character or characters may be depicted in the immediate form if the ASCII data are enclosed in
apostrophes.
 be careful to use the apostrophe (') for ASCII data and not the single quotation mark (‘)
 Binary data are represented if the binary number is followed by the letter B.
 in some assemblers, the letter Y
32/66
 Each statement in an assembly language program consists of four parts or fields.

 The leftmost field is called the label.
 used to store a symbolic name for the memory location it represents
 All labels must begin with a letter or one of the following special characters: @, $, -, or ?.
 a label may any length from 1 to 35 characters
 The label appears in a program to identify the name of a memory location for storing data and for other
purposes.
33/66
 The next field to the right is the opcode field.

 designed to hold the instruction, or opcode
 the MOV part of the move data instruction is an example of an opcode
 Right of the opcode field is the operand field.
 contains information used by the opcode
 the MOV AL,BL instruction has the opcode MOV and operands AL and BL
 The comment field, the final field, contains a comment about the instruction(s).
 comments always begin with a semicolon (;)
34/66
Label Opcode Operand Comment

 DATA1 DB 23H ;define DATA1 as a byte of 23H
 DATA2 DW 1000H ;define DATA2 as a word of 1000H
 START: MOV AL,BL ;copy BL into AL

 MOV BH,AL ;copy AL into BH
 MOV CX,200 ;copy 200 into CX
35/66
 MOV AX,2550H ;move 2550H into AX  MOV AX,2550H

 MOV CX,625 ;Ioad the decimal value 625 into ex  MOV DS,AX
 MOV BL,40H ;Ioad 40H into BL
 MOV DS,0123H ;illegal!!
36/66
DIRECT DATA ADDRESSING
 Applied to many instructions in a typical program.

 Two basic forms of direct data addressing:
 direct addressing, which applies to a MOV between a memory location and AL, AX, or EAX
 displacement addressing, which applies to almost any instruction in the instruction set
 Address is formed by adding the displacement to the default data segment address or an alternate segment
address.
37/66
DIRECT ADDRESSING
 Direct addressing with a MOV instruction transfers data between a memory location, located within the data
segment, and the AL (8-bit), AX (16-bit), or EAX (32-bit) register.
 usually a 3-byte long instruction
 MOV AL,DATA loads AL from the data segment memory location DATA (1234H).
 DATA is a symbolic memory location, while 1234H is the actual hexadecimal location
38/66
FIGURE 3–5 THE OPERATION OF THE MOV AL,[1234H] INSTRUCTION WHEN DS=1000H .
 This instruction transfers a copy

contents of memory location 11234H
into AL.
 the effective address is formed by
adding 1234H (the offset address) and
10000H (the data segment address of
1000H times 10H) in a system
operating in the real mode
39/66
DIRECT ADDRESSING
 MOV DL,[2400] ;move contents of DS:2400H into DL
40/66
DIRECT ADDRESSING
 Solution:
 First AL is initialized to 99H, then in line two, the
 Find the physical address of the memory location contents of AL are moved to logical address DS:3518
and its contents after the execution of the following, which is 1512:3518.
 assuming that DS = 1512H  Shifting DS left and adding it to the offset gives the
physical address of 18638H (15120H + 3518H =
 MOV AL,99H
18638H).
 MOV [3518],AL
 That means after the execution of the second
instruction, the memory location with address
18638H will contain the value 99H.
41/66
DISPLACEMENT ADDRESSING
 Almost identical to direct addressing, except the instruction is 4 bytes wide instead of 3.
 In 80386 through Pentium 4, this instruction can be up to 7 bytes wide if a 32-bit register and a 32-bit
displacement are specified.
 This type of direct data addressing is much more flexible because most instructions use it.
 MOV CL,DS:[1234H]
42/66
REGISTER INDIRECT ADDRESSING
 Allows data to be addressed at any memory location through an offset address held in any of the following
registers: BP, BX, DI, and SI.
 In addition, 80386 and above allow register indirect addressing with any extended register except ESP.
 In the 64-bit mode, the segment registers serve no purpose in addressing a location in the flat model.
43/66
 MOV AL,[BX] ;moves into AL the contents of the memory location

 ;pointed to by DS:BX.
 MOV CL,[SI] ;move contents of DS:SI into CL

 MOV [DI],AH ;move contents of AH into DS:DI
44/66
 The contents of AX are moved into memory

locations with logical address DS:SI and DS:SI + I;
 DS = ll20, SI = 2498, and AX = 17FE
 therefore, the physical address starts at
 Show the contents of memory locations after the
execution of  DS (shifted left) + SI = 13698.
 MOV [SI],AX  According to the little endian convention, low

address 13698H contains FE, the low byte, and high
address 13699H will contain 17, the high byte
45/66
FIGURE 3–6 THE OPERATION OF THE MOV AX, [BX] INSTRUCTION WHEN BX = 1000H AND DS = 0100H.
NOTE THAT THIS INSTRUCTION IS SHOWN AFTER THE CONTENTS OF MEMORY ARE TRANSFERRED TO
AX.
46/66
 The data segment is used by default with register indirect addressing or any other mode that uses BX, DI, or SI
to address memory.
 If the BP register addresses memory, the stack segment is used by default.
 these settings are considered the default for these four index and base registers
 For the 80386 and above, EBP addresses memory in the stack segment by default.
 EAX, EBX, ECX, EDX, EDI, and ESI address memory in the data segment by default.
47/66
 Indirect addressing often allows a program to refer to tabular data located in memory.
 Figure 3–7 shows the table and the BX register used to sequentially address each location in the table.
 To accomplish this task, load the starting location of the table into the BX register with a MOV immediate
instruction.
 After initializing the starting address of the table, use register indirect addressing to store the 50 samples
sequentially.
48/66
FIGURE 3–7 AN ARRAY (TABLE) CONTAINING 50 BYTES THAT ARE
INDIRECTLY ADDRESSED THROUGH REGISTER BX.
49/66
BASE-PLUS-INDEX ADDRESSING
 Similar to indirect addressing because it indirectly addresses memory data.

 The base register often holds the beginning location of a memory array.
 the index register holds the relative position of an element in the array
 whenever BP addresses memory data, both the stack segment register and BP generate the effective address
50/66
LOCATING DATA WITH BASE-PLUS-INDEX ADDRESSING
 Figure 3–8 shows how data are addressed by the MOV DX, [BX + DI] instruction when the microprocessor
operates in the real mode.
 The Intel assembler requires this addressing mode appear as [BX][DI] instead of [BX + DI].
 The MOV DX, [BX + DI] instruction is MOV DX,[BX][DI] for a program written for the Intel ASM assembler.
51/66
FIGURE 3–8 AN EXAMPLE SHOWING HOW THE BASE-PLUS-INDEX ADDRESSING MODE
FUNCTIONS FOR THE MOV DX, [BX + DI] INSTRUCTION. NOTICE THAT MEMORY ADDRESS
02010H IS ACCESSED BECAUSE DS=0100H, BX=1000H AND DI=0010H.
52/66
LOCATING ARRAY DATA USING BASE-PLUS-INDEX ADDRESSING
 A major use is to address elements in a memory array.

 To accomplish this, load the BX register (base) with the beginning address of the array and the DI register (index)
with the element number to be accessed.
 Figure 3–9 shows the use of BX and DI to access an element in an array of data.
53/66
FIGURE 3–9 AN EXAMPLE OF THE BASE-PLUS-INDEX ADDRESSING MODE.
HERE AN ELEMENT (DI) OF AN ARRAY (BX) IS ADDRESSED.
54/66
REGISTER RELATIVE ADDRESSING
 Similar to base-plus-index addressing and displacement addressing.

 data in a segment of memory are addressed by adding the displacement to the contents of a base or an index register (BP,
BX, DI, or SI)
 Figure 3–10 shows the operation of the MOV AX,[BX+1000H] instruction.
 A real mode segment is 64K bytes long.
55/66
FIGURE 3–10 THE OPERATION OF THE MOV AX, [BX+1000H] INSTRUCTION,
WHEN BX=0100H AND DS=0200H .
56/66
ADDRESSING ARRAY DATA WITH REGISTER RELATIVE
 It is possible to address array data with register relative addressing.

 such as with base-plus-index addressing
 In Figure 3–11, register relative addressing is illustrated with the same example as for base-plus-index addressing.
 this shows how the displacement ARRAY adds to index register DI to generate a reference to an array element
57/66
FIGURE 3–11 REGISTER RELATIVE ADDRESSING USED TO ADDRESS AN ELEMENT OF
ARRAY. THE DISPLACEMENT ADDRESSES THE START OF ARRAY, AND DI ACCESSES AN
ELEMENT.
58/66
BASE RELATIVE-PLUS-INDEX ADDRESSING
 Similar to base-plus-index addressing.

 adds a displacement
 uses a base register and an index register to form the memory address
 This type of addressing mode often addresses a two-dimensional array of memory data.
59/66
ADDRESSING DATA WITH BASE RELATIVE-PLUS-INDEX
 Least-used addressing mode.

 Figure 3–12 shows how data are referenced if the instruction executed by the microprocessor is MOV AX, [BX +
SI + 100H].
 displacement of 100H adds to BX and SI to form the offset address within the data segment
 This addressing mode is too complex for frequent use in programming.
60/66
FIGURE 3–12 AN EXAMPLE OF BASE RELATIVE-PLUS-INDEX ADDRESSING USING A MOV
AX,[BX+SI+0100H] INSTRUCTION. NOTE: DS=1000H
61/66
ADDRESSING ARRAYS WITH BASE RELATIVE-PLUS-INDEX
 Suppose a file of many records exists in memory, each record with many elements.
 displacement addresses the file, base register addresses a record, the index register addresses an element of a record
 Figure 3–13 illustrates this very complex form of addressing.
62/66
FIGURE 3–13 BASE RELATIVE-PLUS-INDEX ADDRESSING USED TO ACCESS A FILE THAT
CONTAINS MULTIPLE RECORDS (REC).
63/66
TITLE MATCH FOR ADDRESSING MODES
# Barry B. Brey M. A. Mazidi & J. G. Mazidi Description

1 Register Register MOV BX, CX
2 Immediate Immediate MOV EAX,13456H
3 Direct Direct MOV AL,[1234H]
4 Register indirect Register indirect MOV AX, [BX]
5 Base-plus-index Based indexed MOV DX, [BX + DI]
6 Register relative Based relative MOV AX,[BX+1000H]
7 Base relative-plus-index Indexed relative MOV AX, [BX + SI + 100H]
64/66
RESOURCES
65/66
THANK YOU
CPE303
MICROPROCESSORS
WEEK 7
ARITHMETIC INSTRUCTIONS WITH CROSS FLAG-REGISTER CHECK
USE OF THE ZERO FLAG FOR LOOPING
 MOV CX,05  ;CX holds the loop count

 MOV BX,0200H  ;BX holds the offset data address
 MOV AL,00  ;initialize AL
 ADD_LP: ADD AL,[BX]  ;add the next byte to AL
 INC BX  ;increment the data pointer
 DECCX  ;decrement the loop counter
 JNZ ADD_LP  ;jump to next iteration if counter not zero
Each time the addition is performed the counter is decremented and the zero flag is checked. 3/51
When the counter becomes zero, the zero flag is set (ZF = 1) and the loop is stopped.
OUTLINE
 Arithmetic Instructions
 Addition
 Increment Addition
 Addition-with-Carry
 Subtraction
 Decrement Subtraction
 Subtraction-with-Borrow
 Comparison
4/51
ARITHMETIC INSTRUCTIONS
ADDITION, SUBTRACTION AND COMPARISON
 The bulk of the arithmetic instructions found in any microprocessor include addition, subtraction, and comparison.
 Addition, subtraction, and comparison instructions are illustrated.
 Also shown are their uses in manipulating register and memory data.
6/51
ADDITION
 Addition (ADD) appears in many forms in the microprocessor.

 A second form of addition, called add-with-carry, is introduced with the ADC instruction.
 The only types of addition not allowed are memory-to-memory and segment register.
 segment registers can only be moved, pushed, or popped
 Increment instruction (INC) is a special type of addition that adds 1 to a number.
7/51
ADDITION
 Register Addition
 When arithmetic and logic instructions execute, contents of the flag register change.
 interrupt, trap, and other flags do not change
 Any ADD instruction modifies the contents of the sign, zero, carry, auxiliary carry, parity, and overflow flags.
 Immediate Addition
 Immediate addition is employed whenever constant or known data are added.
8/51
ADDITION
 Memory-to-Register Addition
 Moves memory data to be added to the AL (and other) register.
 Array Addition
 Memory arrays are sequential lists of data.
9/51
ADDITION
 ADD destination, source;
 This instruction adds the contents of source operand with the contents of destination operand.
 The source may be immediate data, memory location or register.
 The destination may be memory location or register.
 The result is stored in destination operand.
 AX is the default destination register.
ADD AX,2020H;
ADD AX,BX;
10/51
BEFORE EXECUTION AFTER EXECUTION
AH AL ADD AX,2020H AH AL
10 10 30 30
O S Z A P C
0 0 0 0 1 0
1010
+2020
3030
AH AL AH AL
10 10 ADD AX,BX 30 30
BH BL BH BL
11/51
20 20 20 20
2050
12/51
AH AL MOV AL,0F5H AH AL
00 10 00 F5
00F5H 1111 0101

+000BH 0000 1011
0100 0001 0000 0000
O S Z A P C
0 0 1 1 1 1

AH AL AH AL
00 10 ADD AL,0BH 00 00
13/51
Flags change not after MOV instruction but after ADD !

2050
14/51
BH BL MOV BH,38H BH BL
20 20 38 20
0038H 0011 1000

+002FH 0010 1111
0067 0110 0111
O S Z A P C
0 0 0 1 0 0

BH BL BH BL
38 20 ADD BH,2FH 67 20
15/51
Flags change not after MOV instruction but after ADD !

2050
16/51
EXAMPLE OF MEMORY-TO-REGISTER ADDITION
 MOV DI,OFFSET NUMB ;address NUMB

 MOV AL,0 ;clear sum
 ADD AL,[DI] ;add NUMB
 ADD AL,[DI+1] ;add NUMB+1
17/51
ARRAY ADDITION
 Sequential lists of data.

 A sequence of instructions written 80386 shows scaled-index form addressing to add elements 3, 5, and 7 of an
area of memory called ARRAY.
 EBX is loaded with the address ARRAY, and ECX holds the array element number.
 The scaling factor is used to multiply the contents of the ECX register by 2 to address words of data.
18/51
EXAMPLE OF ARRAY ADDITION
 MOV AL,0 ;clear sum

 MOV SI,3 ;address element 3
 ADD AL,ARRAY[SI] ;add element 3
 ADD AL,ARRAY[SI+2] ;add element 5
 ADD AL,ARRAY[SI+4] ;add element 7
19/51
INCREMENT ADDITION
 The INC instruction adds 1 to any register or memory location, except a segment register.
 The size of the data must be described by using the BYTE PTR, WORD PTR, DWORD PTR, or QWORD PTR
directives.
 The assembler program cannot determine if the INC [DI] instruction is a byte-, word-, or doubleword-sized
increment.
20/51
INCREMENT ADDITION
 INC source
 This instruction increases the contents of source operand by 1.

 The source may be memory location or register.
 The source can not be immediate data.
 The result is stored in the same place.
INC AX;
INC [5000H];
21/51
AH AL INC AX AH AL
10 10 10 11
O S Z A P C
0 0 0 0 1 0
5000H 1010
INC [5000H] 5000H 1011
22/51
2050
23/51
ADDITION-WITH-CARRY
 ADC adds the bit in the carry flag (C) to the operand data.
 mainly appears in software that adds numbers wider than 16 or 32 bits in the 80386–Core2
 like ADD, ADC affects the flags after the addition
 Figure 5–1 illustrates this so placement and function of the carry flag can be understood.
 cannot be easily performed without adding the carry flag bit because the 8086–80286 only adds 8- or 16-bit numbers
24/51
FIGURE 5–1 ADDITION-WITH-CARRY SHOWING HOW THE CARRY FLAG (C)
LINKS THE TWO 16-BIT ADDITIONS INTO ONE 32-BIT ADDITION.
25/51
ADDITION-WITH-CARRY
 ADC destination, source
 This instruction adds the contents of source operand with the contents of destination operand with carry flag bit.
 The result is stored in destination operand.
 AX is the default destination register.
ADC AX,2020H;
ADC AX,BX;
26/51
C AH AL ADC AX,2020H AH AL
1 10 10 30 31
O S Z A P C
0 0 0 0 0 0
1010
+2020
3030
C AH AL AH AL
1 10 10 ADC AX,BX 30 31
BH BL BH BL
27/51
20 20 20 20
2050
28/51
SUBTRACTION
 Many forms of subtraction (SUB) appear in the instruction set.

 these use any addressing mode with 8-, 16-, or 32-bit data
 a special form of subtraction (decrement, or DEC) subtracts 1 from any register or memory location
 Numbers that are wider than 16 bits or 32 bits must occasionally be subtracted.
 the subtract-with-borrow instruction (SBB) performs this type of subtraction
29/51
SUBTRACTION
 Register Subtraction
 After each subtraction, the microprocessor modifies the contents of the flag register.
 flags change for most arithmetic/logic operations
 Immediate Subtraction
 The microprocessor also allows immediate operands for the subtraction of constant data.
 Decrement Subtraction
 Subtracts 1 from a register/memory location.
30/51
SUBTRACTION
 SUB destination, source;
 This instruction subtracts the contents of source operand from contents of destination.
 The result is stored in the destination place.
SUB AX,1000H;
SUB AX,BX;
31/51
AH AL SUB AX,1000H AH AL
20 00 10 00
O S Z A P C
0 0 0 0 1 0
2000
- 1000
1000
AH AL AH AL
20 00 SUB AX,BX 10 00
BH BL BH BL
32/51
10 00 10 00
2050
33/51
CH CL MOV CH,22H CH CL
00 10 22 10
0022H 0010 0010

-0044H 0100 0100
00DEH 1101 1110
O S Z A P C
0 1 0 1 1 1

CH CL CH CL
22 10 SUB CH,44H DE 00
34/51
2050
35/51
DECREMENT SUBTRACTION
 DEC source;
 This instruction decreases the contents of source operand by 1.

 The source may be memory location or register.
 The source can not be immediate data.
 The result is stored in the same place.
DEC AX;
DEC [5000H];
36/51
AH AL DEC AX AH AL
10 10 10 0F
5000H 1010
DEC [5000H] 5000H 100F
37/51
2050
38/51
SUBTRACTION-WITH-BORROW
 A subtraction-with-borrow (SBB) instruction functions as a regular subtraction, except that the carry flag (C),
which holds the borrow, also subtracts from the difference.
 most common use is subtractions wider than 16 bits in the 8086–80286 microprocessors or wider than 32 bits in the
80386–Core2.
 wide subtractions require borrows to propagate through the subtraction, just as wide additions propagate the carry
39/51
FIGURE 5–2 SUBTRACTION-WITH-BORROW SHOWING HOW THE
CARRY FLAG (C) PROPAGATES THE BORROW.
40/51
SUBTRACT WITH BORROW
 SBB destination, source;
 Also known as Subtract with Borrow.

 This instruction subtracts the contents of source operand & borrow from contents of destination operand.
 The result is stored in the destination place.
SBB AX,1000H;
SBB AX,BX;
41/51
B AH AL SBB AX,1000H AH AL
1 20 20 10 1F
2020
+1000
1020-1=101F
B AH AL AH AL
1 20 20 SBB AX,BX 10 1F
BH BL BH BL
42/51
10 00 10 00
2050
43/51
COMPARISON
 The comparison instruction (CMP) is a subtraction that changes only the flag bits.
 destination operand never changes
 Useful for checking the contents of a register or a memory location against another value.
 A CMP is normally followed by a conditional jump instruction, which tests the condition of the flag bits.
44/51
COMPARISON
 CMP destination, source
 Also known as Compare.

 This instruction compares the contents of source operand with the contents of destination operands.
 Then resulting carry & zero flag will be set or reset.
CMP AX,1000H;
CMP AX,BX; 45/51
C Z AH AL CMP AX,BX AH AL C Z
0 0 10 00 10 00 0 1
BH BL BH BL
10 00 10 00

C Z AH AL AH AL C Z
0 0 10 00 CMP AX,BX 10 00 0 0
BH BL BH BL
46/51
00 10 00 10
2050
47/51
C Z AH AL CMP AX,BX AH AL C Z
0 0 10 00 10 00 1 0
BH BL BH BL
20 00 20 00
48/51
2050
 So we can easily express-infer:
 If Destination = Source, C = 0 and Z = 1
 If Destination > Source, C = 0 and Z = 0
 If Destination < Source, C = 1 and Z = 0
49/51
RESOURCES
 Dr. Sadhish Prabhu. S., Lecturer Notes of Microprocessors And Microcontrollers. B.S. Abdur Rahman University,
2015.
50/51
THANK YOU

Mikro Işlemciler

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Mikro Işlemciler

Uploaded by

Copyright:

Available Formats

CPE303

 This is CPE303 \ CME 321 – Microprocessors

 Instructor: Dr. Oğuzhan MENEMENCİOĞLU

 The Intel Microprocessors, by

 Machine Language – A collection of binary numbers

push offset string "Please enter your name\n"

 The microprocessor is a general-purpose programmable logic device.

At the end of the course, student should be:

 Introduction to Microcomputers and Microprocessors

 What does the “micro” mean?

Date Development Name Description

Vacuum Transistor IC Better IC

Key inventions of generations Quiz 1

Term Decimal Name Binary

 Number systems & operations (But, Let’s do it first!)

 Why base 10?

 Number system base

 Base 5 (would have digits 0 to 4)

 Base 10 to binary (base 2)

 Procedure (Integer division)  4/2 = 2 r 0

 How about 13910 = ? Number Div 2 Remainder

 In first example have 1 0 0 1 1

 Follow the same rules as base 10

 And we need to borrow – step 1

 The next steps work through to

 To allow answer to be done

 For 4 bits can represent values -8 to 7 0 0 0 0 0 -0 0 0 0 0

 To generate the 2’s complement of n

 2) Starting at the lsb (rightmost) bit

 01110 + 11010 (i.e. 14 + (-6))

 In general can represent

 When was the first computer created?

 Charles Babbage 1792-1871

 The Analytic Engine – a more advanced machine

 The von Neumann architecture – 1940s and 50s

 Instructions are executed in sequence

 Memory responds with the contents at that address placing

 Increment the PC (PC+1->PC)

 Say the instruction was a load immediate

 Earliest computers had fixed programs – such as a desk calculator

 ORDVAC (U of Ill) - 1951

 The Intel 4004 – 1971

 Basically a features issue.

 Computer are not new!

 Use of a microprocessor requires working knowledge of numbering systems.

 Exponential value of each position:

 Conversions from decimal to other number systems more difficult to accomplish.

 To convert 10 decimal to binary, divide it by 2.

 To convert 10 decimal to base 8, divide by 8.

 Conversion is accomplished with multiplication by the radix.

 Algorithm for conversion from a decimal fraction:

 At times, data are stored in complement form to represent negative numbers.

 The Microprocessor-based Personal Computer

 Computers have undergone many changes recently.

 Figure 1–6 shows block diagram of the personal computer.

 Memory structure of all Intel-based personal computers similar.

 Main memory system divided into three parts:

 Three newer buses have appeared.

 AGP (advanced graphics port) for video cards.

 DOS memory map shows how areas of TPA are used

(Note that this map will vary between systems.)

 Hexadecimal memory addresses number each byte of the memory system.

 Drivers are programs that control installable I/O devices.