Electrical Power and Energy Systems 145 (2023) 108703

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International Journal of Electrical Power and Energy Systems

journal homepage: www.elsevier.com/locate/ijepes

Power quality improvement in single-phase transformerless

semi-quasi-Z-source inverters for off-grid photovoltaic systems
Meraj Noroozi a, Farhad Haghjoo a, *, Hamid Javadi a, Mohammad Reza Zolghadri b
a
Department of Electrical Engineering, Shahid Beheshti University, Tehran, Iran
b
Electrical Engineering Department, Sharif University of Technology, Tehran, Iran

A R T I C L E I N F O A B S T R A C T

Keywords: The transformerless single-phase semi-quasi-Z-source inverter (SqZSI) provides several advantages over classical
Power quality improvement PWM converters. Reduced or eliminated leakage current, high power density, and low cost are important fea­
DC elimination tures making this topology an attractive choice for PV micro-inverter applications. Two drawbacks of this to­
Harmonic mitigation
pology are DC and second harmonic injection in the output AC port, which in some cases prevent the fulfillment
Semi-Quasi-Z-Source
Transformerless
of standard requirements. To alleviate this power quality issue, four novel harmonic mitigation algorithms based
Single-phase inverter on PI and PR controllers are proposed, analyzed, and experimentally verified with the 90 W SqZSI in this paper.
Moreover, a modified modulation reference waveform strategy is introduced. Consequently, the converter per­
formance, in terms of total harmonic distortion (THDV) is achieved at about 1.27% under full power load. Also, in
this paper, the non-ideal state-space model of the SqZSI with the effect of the equivalent series resistance of
inductors is developed and the generation origin of DC and second harmonic component is analyzed based on the
obtained model. The achieved results confirms the significant THD reduction by more than 75%, the DC
component suppression, the second harmonic mitigation, and the power quality improvement.

1. Introduction
There is an increasing demand for low-cost single-phase DC–AC in­
verters in many applications such as PV systems [1]. PV system may also
be used without the transformer (i.e. transformerless topology), which
improves efficiency and makes the whole system lighter, smaller, and
easier to install [2,3], the system efficiency using transformerless to­
pology increases by about 2%, and the cost decreases by 25% [4]. To
minimize the leakage current of the transformerless inverter topologies,
doubly grounded schemes (i.e. common-ground topologies) can be used
[5,6]. To overcome the disadvantages, a family of single-stage trans­
formerless semi-Z-source inverters with low cost and common-ground
features has been presented [7,8]. Due to the advantages of the semi-
quasi-Z-source inverter [8–10], this topology has been considered in
recent years [11–13]. Transformerless topologies (e.g. SqZSI) introduce
the DC injection issue at their AC output terminal, which has enormous
impacts on the power quality [4].
The next generation of PV systems need to be more intelligent [12]
and must provide the desired level of power quality. Generally, the
quality of power provided by the PV system is governed by practices and
standards addressing voltage, flicker, frequency, and distortion [13]. In
some conditions and some operation points, the SqZSI injects the DC and
second harmonic in the AC terminal, which is not desirable from the
power quality perspective and may not satisfy the relevant standards.
The generation of unwanted DC and second harmonic components for
SqZSI topology is an issue, which has not been analyzed in detail in the
references. One of the most extreme issues brought on by DC current
injection is the saturation of the transformers, excessive losses, over­
heating and dimensioned life expectancy. In addition, it also may cause
mistakes in some of the measurement and protective relays systems
[14]. The SqZSI topology is particularly suitable for low-power PV ap­
plications such as AC module inverter for a PV module power range
typically under 500 W. So, the SqZSI topology can be categorized as a
low-cost micro-inverter topology.
Several standards have been set to limit DC injection, which varies
from country to country. The PV system shall not inject DC current
greater than 1% of the rated inverter output current at AC output ter­
minal under any operating condition [15]. British standard limits DC
injection to 20 mA for distributed generation with stage streams beneath
16A RMS [14]. The DC current injection in the Australian standard
AS4777.2 should not exceed 0.5% of the inverter rated output current or
5 mA [14]. Based on IEEE Std 929-2000 standard, one method to pre­
vent the injection of DC current into the AC side is to incorporate an AC

* Corresponding author.
E-mail address: f_haghjoo@sbu.ac.ir (F. Haghjoo).

https://doi.org/10.1016/j.ijepes.2022.108703
Received 21 June 2021; Received in revised form 15 May 2022; Accepted 2 October 2022
Available online 22 October 2022
0142-0615/© 2022 Elsevier Ltd. All rights reserved.
M. Noroozi et al. International Journal of Electrical Power and Energy Systems 145 (2023) 108703

Nomenclature a, b, c and u State matrix, input matrix, output matrix and input
vector respectively in small-signal analysis
SqZSI Semi-quasi-Z-source inverter I Identity matrix
PV Photovoltaic s Laplace variable
EMI Electromagnetic interference GV(s) Voltage gain transfer function
DC, AC Direct and alternating current GVss(s) Steady-state voltage gain transfer function
d, d’ Duty cycle of S1 and S2, respectively Rec-DFT Recursive discrete Fourier transformation
M Modulation index NLSPWM Nonlinear sinusoidal pulse width modulation
R Load resistance MAF Moving average filter
L1, L2 Inverter inductors h1 Fundamental harmonic component amplitude
C1, C2 Inverter capacitors h2 to h5 Harmonic components
S1, S2 Power semiconductor switches Vh1 to Vh5 Harmonic components of the voltage
rL, rL_pu Equivalent series resistance of inductors and their per-unit PI0, PI1 and PI2 Proportional – Integral controller for DC,
value fundamental and h2 components, respectively
Vin Input DC voltage of the inverter PR Proportional - Resonant
VO, IO Amplitude of output AC voltage and current K p, K i Proportional and integral gains of PI controller
VC1, VC2 Voltage across capacitors KPR-p, KPR-i Proportional and resonant gains of PR controller
IL1, IL2 Inductors current ωc Bandwidth of non-ideal PR controller (cut-off frequency)
ΔIL1, ΔIL2 Inductors ripple current vch2, vcdc Compensation signals
ΔVC1, ΔVC2 Capacitors ripple voltage Z-1 Unit delay in discrete Z-transform
PO Inverter Output power x(k) Discrete-time signal
V, ω Amplitude and angular frequency of VO k Discrete signal sample counter
η Inverter efficiency N Number of samples in the filter window
Fsw Switching frequency Sk, Ck Sine and cosine components of DFT result
Tsw, TON Switching period and conduction period of S1 α A coefficient for compensation
THDV Total harmonic distortion of output voltage θh2 Phase angle of second harmonic
DCV DC component of output voltage Vref Reference voltage waveform for modulation
x, A State variable vector and state matrix ADC Analogue to digital converter
u, B Input vector and the input matrix

output isolation transformer in the inverter, which is not possible for
transformerless topology, the other method, which uses a shunt or DC-
current sensor, initiates inverter shutdown when the DC component of
the current exceeds the specified threshold [13]. The origin and detri­
ments of DC component in AC side with the latest DC component
detection, and suppression methods (e.g. power converter with DC
suppression capability, physical capacitors, virtual capacitors, intelli­
gent compensation control, etc.) have been reviewed in [4,16].
Furthermore to the DC injection issue, according to IEC 61727-2004
standard, low levels of current and voltage harmonics are desirable; the
higher harmonic levels increase the potential for adverse effects on
connected equipment [15], such as thermal overloading of transformers
and motors, disruption, dielectric stressing, unexplained breaker trips,
misoperation of drives, relays, computers, etc. [16]. According to IEEE
Std 1547-2018 [17], the distortion of individual odd current harmonics
(h < 11) shall not exceed 4% of fundamental component, similarly with
stricter considerations for even harmonics, the maximum limits for in­
dividual even harmonic distortion are 1%, 2%, and 3% for second (h2),
forth (h4), and sixth (h6) current harmonics respectively[19,17,[13].
Hence according to IEEE Std 1547-2018 [17], the limitation of THD is at
5%, the given standard limits are voluntary and specify the minimum
requirements. Nevertheless, to increase system performance and life
span, the THD value must be kept as low as possible. In addition, IEEE
Std 519-2014 [18] recommends that general resources and related
equipment have to have no more than 5% total harmonic voltage
distortion with the largest single harmonic no more than 3% of the
fundamental voltage.
Moreover, the requirements of power quality standards for the next
generation of PV systems may include stricter revisions in the future. For
instance, the IEEE Std 1547 standard was revised in grid support func­
tions three times between 2003 and 2018, and more stringent regula­
tions were imposed [17]. Therefore, one of the aims of this paper is to
improve the power quality of the SqZSI topology.
There has been a lot of works performed in the area of harmonic
compensation in both synchronous and stationary reference frame [19].
The performance comparison of harmonic compensation methods for a
three-phase voltage source inverter based on the PI controller in the dq-
synchronous reference frame and the PR controller in the αβ stationary
reference frame has been presented in [20]. The conventional harmonic
compensation techniques in both frames through advanced control in
renewable energy sources have been reviewed and compared in [19,22];
also a robust harmonic mitigation strategy for a single-phase grid-con­
nected inverter based on the digital lock-in amplifier has been proposed
in [19], which in this strategy, the extracted harmonic is reconstructed
and subtracted from the output of the fundamental current controller to
compensate for it.
An enhanced current control scheme to eliminate the dc and har­
monic currents in transformerless grid-connected inverters has been
proposed in [22], which is designed in the synchronous (d-q) reference
frame and composed of a PR controller and a repetitive controller (RC),
the role of the RC is to regulate the grid current follow the reference
value as well as compensate harmonic components caused by distorted
grid voltage and scaling errors. In [23], causes of DC offset error in the
phase current measuring process and effects of DC offset error in phase
current of a single-phase grid-tied inverter have been analyzed; also a
compensation algorithm based on PR controller for DC component and
second harmonic component compensation has been presented. In [24],
a multi-voltage control strategy of single-phase inverter has been pro­
posed for lower THD of the output voltage, which the harmonics of the
output voltage are extracted and controlled in their own synchronous
rotating reference frames. In [10], by utilizing coupled inductor in SqZSI
topology, the performance and compatibility of modulation technique
have been verified under different loading conditions; for instance, 4.5%
THD of the output voltage for resistive load have been reported, but the
details of the closed-loop control method are not provided, and also no
compensation method is used to improve the power quality. Some

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M. Noroozi et al. International Journal of Electrical Power and Energy Systems 145 (2023) 108703

Table 1 Table 1 (continued )

Some harmonic compensation methods in the literature. Ref Compensation Controller type Results
Ref Compensation Controller type Results method
method
[25] Modifying reference Proportional Odd • Compensation with
[19] Modifying reference PI + PR • Without filters in the waveform Harmonic Multi reduction in the
waveform (novel orthogonal signal Resonant-type memory space
Digital Lock-In generator; Repetitive Controller consumption,
Amplifier) Without PLL for (POHMR-type RC) calculation burden
phase Information; and controller
Immune to DC complexity;
offset; Good dynamic
Immune to AC side performance.
harmonics; [26] Active filtering • PI (dc link) Improvement in
Satisfying the THD methods (Modifying PR (fundamental) performance and power
standards; reference waveform) quality for
Higher multifunctional
computational inverters.
burden. [27] Modifying reference PI Selective harmonic
[20] Modifying reference • (PI) in dq- • Stability and waveform compensation for
waveform synchronous refer­ effectiveness of the inverters in micro-grids.
ence frame; control algorithms [28] Modifying reference Model-based • Improve accuracy and
(PR) in the αβ across a wide range of waveform predictive controller control response speed
stationary reference operating conditions; combining a notch (MPC) when applied Modular
frame; Good current filter with decoupled multilevel cascaded
tracking, and then the double synchronous converters (MMCC)
standard harmonic reference frame used for harmonic
satisfying; elimination;
Better power quality Minimum time
for PI controller than delay;
the PR one, although Fast and accurate
the compensation tracking.
algorithm for PI is [29] Modifying reference PI + harmonic • Decouples unbalance
more complex than waveform resonant filters and harmonic
the PR controller. compensation in the
[21] • Active filtering Different types of A review on harmonic phase sequences and
methods controllers (PI, PR, mitigation techniques the frequency domain;
(Modifying Hysteresis and etc.) through advanced Designed to be
reference control methods for PV sequence-asymmetric
waveform) inverters. for the unbalanced
Virtual and harmonic local
impedance based voltage correction;
control methods Independent regula­
including: tion of the funda­
Current Control mental positive-
Method (CCM) sequence, the har­
Voltage Control monic symmetrical
Method (VCM) sequence, the funda­
Hybrid Control mental zero-sequence
Method (HCM) and the fundamental
[22] Modifying reference Proportional Resonant • Eliminating the DC negative sequence
waveform (PR) controller + a and harmonic components.
Repetitive Controller components; [30] Modifying reference Optimized MPC • Control method will
(RC) Satisfying THD waveform overcome harmonic
standards; current tracking
Reduction of time inefficiency in online
delay and then good harmonic
steady-state perfor­ compensation;
mance; The simplicity of
Simple and low implementation,
computation load in calculation delay
digital implementa­ compensation and its
tion (PR + RC). fast response to
[23] Modifying reference • PI for DC • DC offset changes.
waveform by DC elimination compensation
offset compensation PR for Power quality
algorithm fundamental improvement harmonic compensation methods presented in the literature are listed in
harmonic Table 1.
[24] Modifying reference PI (selective harmonic • Harmonics of Vo are
As can be observed, well-known linear controller methods such as PI
waveform (multi- controller) extracted and
voltage control controlled in their and PR have been utilized in most references. Therefore, similar con­
strategy) own synchronous trollers have been used in the present paper. It should be mentioned that
rotating reference the controlling approach used in this paper is closer to the methods of
frames. [19,24]. In addition, the compensation method is similar to most ref­
Satisfying THD
standards.
erences and operates on the modifying reference waveform method. It is
Good dynamic. worth to be mentioned that the power quality improvement in SqZSI
topology has not been regarded in the literature, while the compensa­
tion methods proposed in this paper have been specially customized for

3
M. Noroozi et al.
Fig. 1. (a) Semi quasi Z-source inverter topology, (b) Voltage gain curve in terms of the duty cycle d.
Fig. 2. Equivalent circuit for (a) mode I: S1 is ON, and S2 is OFF, (b) mode II: S2 is ON, and S1 is OFF.
SqZSI topology. Moreover, in autonomous mode for off-grid systems, the
micro sources are controlled to supply all the power needed by the local
loads while maintaining the voltage and frequency within the allowed
limits (i.e. V-F control mode) [31,32].
In this paper, four closed-loop compensation methods in V-f control
mode for transformerless SqZSI topology based on the well-known linear
control techniques are proposed. Also:
• The regulation and stabilization of the output in the off-grid system is
guaranteed within the allowable range according to IEEE Std
519–2014 [18] and ANSI C84-2016 [15,33];
• Desired level of power quality beyond the established standards
(THDV = 1.27%) such as IEEE Std 519–2014 [18] and IEC 61000–3-
2:2018 [34] is achieved;
• DC component injection to the AC output terminal in transformerless
SqZSI is eliminated according to IEC 61727–2004 [15];
• The second harmonic component of VO is mitigated within the limits
of IEEE Std 519-2014 [18];
• By optimum use of latent capability in the SqZSI topology (by
generating negative voltage greater than 1 pu), the power quality
improvement is achieved.
The rest of this paper is organized as follows:
The operation principle of SqZSI is described in section 2. State-space
average model of non-ideal SqZSI is developed in section 3, the origin of
the DC and h2 components generation is analyzed in section 4. Four
proposed compensation methods are fully described in section 5.
Simulation and experimental results are interpreted in section 6 and 7,
respectively. The performance comparison between the implemented
SqZSI and other SqZSIs is discussed in section 8, and finally, the paper is
concluded in section 9.
2. Operation principle of the SqZSI
The topology of single-phase SqZSI is presented in Fig. 1a [7]. In this
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International Journal of Electrical Power and Energy Systems 145 (2023) 108703
topology, the DC input source and the AC output terminal share the
same ground. Consequently, this inverter is a common-ground trans­
formerless topology; this has drastically reduced the leakage current.
The duty cycle of switch S1 is expressed by d. The voltage gain curve in
terms of d is shown in Fig. 1b. Also, to better realize the relationship
between the gain and the output voltage, the output voltage waveform
(Vo) is hypothetically displayed on the gain curve. According to the
voltage gain curve, this converter can generate a positive and negative
voltage at its output by changing the duty cycle. This topology can be
used as an inverter by changing duty cycle (d) from 0 to 0.667 and needs
a suitable modulation method [7].
Since the SqZSI voltage gain curve is not the same as a full-bridge
inverter, a nonlinear modified SPWM strategy must be used to get the
same desired sinusoidal voltage at the output. There are two operating
modes for the inverter. In mode I, S1 is ON, and S2 is OFF, while in mode
II, S1 is OFF, and the S2 is ON. In mode I, the input voltage source and C1
charge the two inductors, so the inductor’s currents are increased. In
mode II, when switch S2 is ON, the two inductors act like a discharging
source, so their current is decreased [7]. The equivalent circuits in mode
I and mode II are shown in Fig. 2a and Fig. 2b, respectively.
2.1. Single-phase SqZSI steady-state equations
The steady-state equations of the SqZSI voltage gain, VC1, IL2, and IL1
are respectively expressed as follows [7]:
Vo 1 − 2d
= (1)
Vin 1− d
d
VC1 = Vin (2)
1− d
IL2 = − Io (3)
d
IL 1 = − Io (4)
1− d
M. Noroozi et al. International Journal of Electrical Power and Energy Systems 145 (2023) 108703

circuits in Fig. 2, the state-space matrix is obtained by writing the KVL

equations in each operation mode. Considering state vector as (11), the
state-space equations are presented in (12) and (13) for mode I:
x = [iL1 iL2 vC1 vC2 ] (11)

ẋ = (A1 x + B1 u) (12)
⎡− r ⎤
L
0 0 0 ⎡ ⎤
⎡ ⎤ ⎢ L1 ⎥
⎢ ⎥ 1
⎢ − rL 1 1 ⎥⎡ ⎤ ⎢ ⎥
⎢ i˙L ⎥ ⎢ 0 ⎥ iL1 ⎢ L1⎥
⎢ 1 ⎥ ⎢ ⎥
⎢ i˙L ⎥ ⎢ L2 L2 L2 ⎥⎢ iL2 ⎥ ⎢ ⎥
⎢ 2 ⎥=⎢ ⎥⎢ ⎥+⎢ 0 ⎥
⎥Vin (13)
⎢ v̇C ⎥ ⎢ − 1 ⎥⎣ vC1 ⎦ ⎢
⎢ ⎥
⎢ 1⎥ ⎢ 0 0 0 ⎥ ⎢ 0 ⎥
⎣ v̇C ⎦ ⎢ C1 ⎥ vC ⎣ ⎦
2 ⎢ ⎥ 2
⎢ ⎥ 0
⎣ − 1 − 1 ⎦
0 0
Fig. 3. Pulse generation for switches S2 and S1 in SqZSI. C2 C2 R

The state-space equations in mode II are presented in (14) and (15).

According to (5) and (6), the values of capacitor and inductor can be
selected based on the amount of ripple considered for capacitor voltage ẋ = (A2 x + B2 u) (14)
and inductor current, which are expressed as [10]: ⎡ ⎤
− rL − 1
0 0 ⎥
△VC1 =
(1 − d)Ts IL1
(5) ⎡ ⎤ ⎢
⎢ L1 L1 ⎥ ⎡ ⎤
C1 ⎢ ⎥⎡ ⎤ 0
⎢ i˙L ⎥ ⎢ − rL 1 ⎥ ⎥ iL1 ⎢− 1⎥
⎢ 1 ⎥ ⎢ 0 0 ⎢ ⎥
⎢ i˙L ⎥ ⎢ L2 L2 ⎥⎥⎢ iL2 ⎥ ⎢ ⎥
Vin Ts d ⎢ 2 ⎥=⎢ ⎢ ⎥ +⎢ L2 ⎥Vin (15)
△IL1 = △IL2 = (6) ⎢ v̇C ⎥ ⎢ ⎥⎣
⎥ vC1 ⎦ ⎢ ⎥
L1 ⎢ 1⎥ ⎢ 1 ⎢ ⎥
⎣ v̇C ⎦ ⎢⎢ 0 0 0 ⎥ ⎥ vC2 ⎣ 0 ⎦
2
⎢ C1 ⎥
The nonlinear reference waveform for the duty cycle is obtained ⎢ ⎥ 0
⎣ − 1 − 1⎦
according to (7)-(10). In (1), substituting the output voltage VO as a si­ 0 0
C2 C2 R
nusoidal function, the duty cycle equation in terms of modulation index
(M) is obtained as: The duty cycle in mode I of the switching period is considered as d,
Vo = Vsin(ωt) (7) and the rest of the switching period in mode II is related to d’, which are
expressed by (16) and (17), respectively.
V
M= (8) d=
Ton(S1 )
(16)
Vin Tsw

1 − M sin(ωt)
(9) (17)
′
d= (for S1 ) d = 1− d
2 − M sin(ωt)
Finally, the state-space averaged method is defined based on one
1 switching period (Tsw), considering the weighted matrix differential
(10)
′
d = (for S2 )
2 − Msin(ωt) equation by d, which is expressed as (18).
According to Fig. 3, Since the switches S1 and S2 are controlled Ẋ = (A1 x + B1 u) × d + (A2 x + B2 u) × (1 − d) (18)
complementarily, for ease of generating the switching pulses, the duty
cycle of the switch S2 (d’) is used as a reference waveform [7]. Also, the matrices of differential equations in the averaged method
To achieve the dynamic behavior of this topology, considering the can be expressed by (19)-(22).
effect of parasitic elements, the analysis of the state-space model can be Ẋ = AX + BU (19)
used. Therefore, in the following section, the state-space model of the
non-ideal SqZSI is extracted. A = A1 d + A2 × (1 − d) (20)

3. State-space model of the non-ideal SqZSI B = B1 d + B2 × (1 − d) (21)

⎡ ⎤
3.1. State-space averaged model − rL iL1 + dVin − (1 − d)VC1
⎡ ⎢
⎤ L1 ⎥
⎢ ⎥
Generally, impedance source converters, including the SqZSI, are ⎢
⎢
⎥
⎢ i˙L ⎥ ⎢ − rL iL2 + dVC1 + VC2 − Vin (1 − d) ⎥
⎥
time-variant systems [35]. The small-signal modeling for impedance- ⎢ 1 ⎥ ⎢
⎢ i˙L ⎥ ⎢ L2 ⎥
⎥
source converters and comprehensive analysis have been presented in ⎢
Ẋ = ⎢ 2 ⎥
⎥=⎢ ⎥ (22)
v̇
⎢ 1⎥ ⎢ ⎢ (1 − d)iL1 − diL2 ⎥
[36]. The state-space averaging method is used to model the power
C
⎣ v̇C ⎦ ⎢ ⎥
C ⎥
electronic converters [30,32]. Also, the large-signal stability and aver­ ⎢ ⎥
2 1
⎢ ⎥
aged model for an ideal semi-quasi-Z-source inverter has been presented ⎣ − (VC2 + RiL2 ) ⎦
in [38]. In this paper, to obtain the SqZSI state-space model, the aver­ C2 R
aging method is utilized, similar to the technique used in [30,34–38].
The small-signal and dynamic modeling of Z-source converters has been
3.2. Small-signal model analysis
analyzed in [41–47]. Moreover, to obtain the non-ideal model of the
SqZS, the equivalent series resistance of the inductors is considered as rL
Linearizing the averaged model around the operating point makes
in the equations. The model of non-ideal SqZSI with the effect of the rL
the possibility to extract transfer functions. The weighted matrix dif­
has not been thoroughly analyzed before. According to equivalent
ferential equation (22) presents the nonlinear behavior of the converter.

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M. Noroozi et al. International Journal of Electrical Power and Energy Systems 145 (2023) 108703

̂i L1 = iL1 − IL1 0
̂i L2 = iL2 − IL2 0
̂v C1 = vC1 − V C1 0
(23)
̂v C2 = vC2 − V C2 0
̂d =d− D
̂ in = Vin −
V Vin0
Substituting (23) in (22) and neglecting the second-order ac terms,
which assumed much smaller than the first-order ac terms [39], the
state-space matrices in the small-signal model can be expressed as (24)
and (25).

̂x˙ = â x + b̂x
̂ o = ĉ
V x , c = [0 0 0 1] (24)
̂o = ̂
V v C2
⎡ ⎤
− rL D− 1 ⎡ ⎤
0 0 ⎥ D VC1 0 +Vin0
⎡ ⎤ ⎢ ⎢ L1 L1 ⎥
⎢ ⎥⎡ ⎤ ⎢ 1 ⎢ L L 1
⎥
⎥
⎢ ̂˙i L1 ⎥ ⎢ − rL D 1 ⎥⎥ ̂i L1 ⎢ ⎥
⎢ ⎥ ⎢ 0 ⎢ D− 1 V +V in0 ⎥[ ]
⎢ ̂˙i ⎥ ⎢ ⎥ C1 0
L2 L2 L2 ⎥⎢ ̂i L ⎥ ⎢ ⎥ V
⎢ L2 ⎥ = ⎢ ⎥⎢ 2 ⎥ + ⎢ L2 L2 ⎥ ̂ in
⎢˙ ⎥ ⎢ ⎣ ⎦ ⎢ ⎥ ̂
⎢̂v ⎥ ⎢ 1− D − D ⎥ ̂v C1 ⎢ − IL1 0 − IL2 0 ⎥
d
⎣ ˙ C1 ⎦ ⎢ ⎢ C1 0 0 ⎥⎥ ̂v C2 ⎢ ⎥
v C2
̂ ⎢ C1 ⎥ ⎢ 0 ⎥
⎢ ⎥ ⎣ C1 ⎦
⎣ − 1 − 1⎦
0 0 0 0
C2 RC2
(25)

3.3. Voltage gain transfer function of the non-ideal SqZSI

Equation (26) is used to obtain the state vector from the state matrix
in the small-signal analysis.

x = (sI − a)− 1 b̂
̂ u (26)
By solving (26), all state variables can be expressed regarding the
duty cycle and input voltage as input vector in the small-signal model.
Since the VC2 is equal to the output voltage, so for obtaining the output
voltage transfer function from the small-signal model, after several
simplifications [48], a quadratic function can be expressed by (27) and
Fig. 4. (a) The non-ideal gain curves of the SqZSI in terms of the different duty (28).
cycles and different rL, (b) The root locus of the voltage gain transfer function
for different values of d. ̂ o (s)
V q2 s2 + q1 s + q0
GV (s) = = (27)
̂ in (s) p4 s4 + p3 s3 + p2 s2 + p1 s + p0
V

q2 = − RC1 L1 (D − 1)
q1 = − C1 RrL (D − 1)
( )
q0 = R 2D2 − 3D + 1
p4 = C1 C2 L1 L2 R
p3 = C1 (L1 L2 + RrL L1 C2 + RrL L2 C2 )
p2 = C1 L1 R + C2 L2 R + C1 L1 rL + C1 L2 rL − 2C2 L2 RD + C2 L1 RD2 + C2 L2 RD2 + C1 C2 RrL2
p1 = L2 − 2L2 D + C1 RrL + C2 RrL − 2C2 RDrL + 2C2 RD2 rL + L1 D2 + L2 D2 + C1 rL2
p0 = R + rL − 2RD − 2DrL + RD2 + 2D2 rL

The linearization is necessary to use the linear control theory. Therefore,

the set of equations in (23) are presented for small-signal deviations
around the point of linearization, which the values with hat are the ac Setting the frequency to zero (S = 0) in (27), the steady-state voltage
terms of deviations; Also IL10, IL20, VC10, VC20, D and Vin0 are considered gain transfer function of the non-ideal SqZSI with the effect of rL can be
as the steady-state values of their variables. expressed by (29).
R(2D − 1)(D − 1)
GVss (s = 0) = (29)
R + rL − 2RD − 2drL + RD2 + 2rL D2

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M. Noroozi et al. International Journal of Electrical Power and Energy Systems 145 (2023) 108703

Since R is the load resistance and defining per-unit new variable of

inductor resistance as (31), the equation (29) can also be written in a
per-unit form as (32).
rL
rL pu = (31)
R

(2D − 1)(D − 1)
GVss (s = 0) = ( ) 2
(32)
1 + rL 2
pu (D − 1) + rL pu D

The non-ideal gain curve of the SqZSI in terms of the duty cycle for
different rL is depicted in Fig. 4a. Also, according to Table 5, the value of
the base resistance (R) is assumed to be 25 Ω. The ideal voltage gain
curve is obtained by ignoring the internal resistance (rL = 0), that is the
same as Fig. 1b. According to Fig. 4a, with increasing rL_pu, the voltage
gain curve moves away from the ideal state. The root locus of the voltage
gain transfer function for different values of d is shown in Fig. 4b. The
positive cycle of the output voltage corresponding to the duty cycle
between zero and 0.5 is marked in red, and the negative cycle of the
output voltage for the range 0.5 to 0.67 is marked in blue.

4. Origin of the DC and h2 components generation

In the rest of paper, it is demonstrated that undesirable components

Fig. 5. Step response analysis of GV(s), (a) Rise time for different values of d,
(b) Rise time and settling time at peak voltages and zero voltage, (c) The non-
ideal voltage gain curve for different rL, (d) Applied Sin reference and obtained
per-unit output voltage by simulation.
such as DC and h2 are injected into the output AC port with different
amplitudes in some conditions. This issue is investigated based on the
state-space model analysis, simulation validation, and experimental
confirmation, respectively.
The reason for the DC and the second harmonic components gener­
ation can be analyzed based on the non-ideal voltage gain transfer
function obtained in (27). The dynamic behavior of the transfer function
obtained from the small-signal model can be interpreted by step
response analysis. The step responses result for different, discrete and
steady-state values of the duty cycles are shown together in Fig. 5a.
According to the root locus of the voltage gain transfer function in
Fig. 4b and the rise time analysis in Fig. 5a, it can be observed that the
response speed for the positive sinusoidal area (0 < d < 0.5) is faster
than the negative area (0.5 < d < 0.67).
Also, According to Fig. 5b, the slower response of the system around
the negative peak voltage than around the positive peak can be
concluded based on the rise times and settling times comparison. Also,
due to the nonlinear nature of the SqZSI, this topology draws more
current to achieve the negative area of desired sinusoidal waveform than
the positive area, which causes more voltage drop on unwanted parasitic
elements in the negative area. It is also observed in Fig. 5c, that the
negative peak value is less than the positive peak due to the presence of
parasitic elements. As a result, the output voltage will have a positive DC
component. Finally, to better present the effect of the parasitic elements,
the particular dynamic behavior of the non-ideal transfer function and
generation of unwanted components in the output voltage, a simulation
on the SqZSI topology is used when the duty ratio is varied according to
GV(s) to draw a sinusoidal output voltage. Fig. 5d shows the difference
between applied sin reference to the PWM of SqZSI and the actual ob­
tained per-unit output voltage because of the variation of dynamics with
the value of duty ratio. In this simulation, the value of rL is assumed as
0.02 pu for greater clarity, a slower system response around the negative
voltage peak area, as well as the positive DC offset generated and the
presence effect of second harmonic component, are evident.
5. Proposed compensation methods

Also, ignoring the internal resistance of the inductors (rL = 0) in the To mitigate the second harmonic component and eliminate the DC
transfer function (29), the steady-state voltage gain transfer function of component, the effect of four compensation methods is investigated.
the ideal SqZSI obtained as (30), that is the same as (1). These compensation methods are based on:
2D − 1
GVss (s = 0) = (30) 1) PI controllers
D− 1
2) PR controller

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M. Noroozi et al. International Journal of Electrical Power and Energy Systems 145 (2023) 108703

Fig. 6. (a) Proposed compensation algorithm based on the PI controllers for DC elimination and second harmonic mitigation in single-phase SqZSI, (b) The block
diagram of the recursive discrete Fourier transform (Rec- DFT), (c) The block diagram of the moving average filter (MAF), (d)The block diagram of the (pro­
portional–integral) PI controller with external anti-windup input.

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M. Noroozi et al. International Journal of Electrical Power and Energy Systems 145 (2023) 108703

Fig. 7. (a) Proposed closed-loop control based on the PR controller on fundamental frequency for single-phase SqZSI, (b) The block diagram of non-ideal
PR controller.

Fig. 8. Proposed compensation algorithm based on the combination of PR and PI controllers for fundamental harmonic control and DC component mitigation in
single-phase SqZSI.

3) PR + PI controllers done only when required. The operation principles of these algorithms
4) modified modulation are stated in the following. Finally, the performance of the proposed
methods is compared with each other. Also, the generated reference
All proposed methods are based on modification in the reference waveforms for PWM in all proposed methods are compared in Fig. 12.
waveform applied to the SqZSI in closed-loop control. To improve the
power quality, all compensation methods are implemented based on
5.1. Based on the PI controllers
closed-loop control algorithms in the software environment. As
observed in the voltage gain curve of SqZSI in Fig. 4a, this topology can
The proposed compensation algorithm based on the PI controllers for
generate negative voltages greater than one pu. This latent capability in
DC elimination and second harmonic mitigation in single-phase SqZSI is
the SqZSI topology is utilized to eliminate undesirable positive DC offset.
shown in Fig. 6a. In this method, the output voltage needs to be
With the optimal use of the negative voltage gain area (d greater than
measured, filtered and fed to the closed-loop control as the feedback
0.667), which was not used before, it is possible to remove the DC offset.
signal. To control the fundamental harmonic amplitude, this component
In these methods, with applied limits on the controllers, compensation is
is extracted by the recursive discrete Fourier transform (Rec- DFT h1)

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M. Noroozi et al.
Fig. 9. Pulse generation in the proposed algorithm based on the modified
modulating waveform for DC elimination and second harmonic mitigation.
block [49,50], which is shown in Fig. 6b. Then the modulation index (M)
is adjusted by PI1 controller. Moreover, the controller saturation is
limited between 0 and 0.95 to prevent over-modulation. The PI
controller block diagram with the external anti-windup input [51] is
Fig. 10. Proposed compensation algorithm based on the modified modulating waveform for DC elimination and second harmonic mitigation in single-phase SqZSI.
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International Journal of Electrical Power and Energy Systems 145 (2023) 108703
shown in Fig. 6d, and all the PI controllers used in this paper are digitally
implemented in this manner; the transfer function of the PI control is
expressed as (33). It is necessary to employ an anti-windup strategy to
prevent the controller from going into deep saturation [51].
Ki
HPI (s) = Kp + (33)
s
In addition, the value of the DC component is recursively extracted
by the moving average filter (MAF) is shown in Fig. 6c [52]. PI0
controller with zero set-point generates a compensation signal (vcdc)
which is added to the primary modulation reference waveform. The
saturation of the PI0 controller is limited between − 0.05 and 0; thereby
whenever the DC component is generated in the output voltage, this
controller is activated and eliminates the DC component by adding
negative DC offset in the main reference of the inverter. Similarly, by
(Rec- DFT h2) block, the amplitude and phase of the second harmonic
component are extracted via the recursive method. Based on the second
harmonic amplitude, the amplitude of the compensation signal vch2 is
generated with the help of the PI2 controller. Since it is generally ex­
pected that the amount of the second harmonic in the open-loop control
will be less than 5%, the saturation limit of the PI2 controller is defined
between − 0.05 and 0. Whenever the amplitude of the h2 exceeds the
desired set-point, this controller is activated and reduces the h2
component by generating a compensation signal such as (34).
The vch2 compensation signal consists of the sine wave with a 2ω
frequency and the same phase value extracted from the feedback signal
of VO. In other words, the DC offset signal with negative value (vcdc) and
the second harmonic signal with the defined negative limit (vch2) are
added to the primary sinusoidal reference of the inverter as (34). Then
the inverter generates output voltage like the modified reference
waveform, which compensates the DC and h2 components. One of the
advantages of the PI-based compensation method is that it can indi­
vidually control significant harmonics simultaneously.
Vref = Msin(ωt) + vcdc + vch2
vcdc = V0 , ( − 0.05 < V0 < 0) (34)
vch2 = V2 sin(2ωt + θh2 ), ( − 0.05 < V2 < 0)
5.2. Based on the PR controller
The proposed closed-loop algorithm based on the ideal PR controller
on fundamental frequency for single-phase SqZSI is shown in Fig. 7a. In
this method, the output voltage is fed to the closed-loop control as a
sinusoidal feedback signal. The block diagram of the non-ideal PR
controller [53,54] is shown in Fig. 7b, and all the PR controllers used in
this paper are digitally implemented in this manner. The transfer
M. Noroozi et al. International Journal of Electrical Power and Energy Systems 145 (2023) 108703

Fig. 11. Load step-change simulation results, (a) Load voltage and current, (b) Load power, (c) Output voltage fundamental component, (d) Output voltage Har­
monics, (e) Output voltage THD, (f) Frequency spectrum of Vo.

function of the non-ideal PR control is expressed as (35). and the feedback to zero and generates a sinusoidal waveform as the
modulation reference at its output. The saturation of the PR controller is
2KPR− i ωc s
HPR (s) = KPR− p + (35) limited between − 1.2 and 1; therefore the controller can generate a si­
s2 + 2ωc s + ω2
nusoidal waveform with a peak of one pu and prevents over modulation.
The PR controller tries to reduce the sine error between the reference On the other hand, since the PR controller tries to follow the sinusoidal

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M. Noroozi et al. International Journal of Electrical Power and Energy Systems 145 (2023) 108703

Fig. 12. Comparison of the output voltage, the output current and the generated reference waveforms in proposed compensation methods, (a) PI-based compen­
sation method, (b) PR-based compensation method, (c) PR + PI based compensation method, (d) modified modulation compensation method.

Table 2
The designed controller gains.
Proposed method Controller: PI0 PI1 PI2 PR

Gain: Kp Ki Kp Ki Kp Ki KPR_p KPR_i

PI-based 0.5 50 0.5 60 0.5 25 – –

PR-based – – – – – – 3 100
PR + PIdc based 0.5 50 – – – – 3 100
Modified Modulation 2 100 0.5 60 – – – –

set-point strictly, it automatically tries to minimize the value of DC and
h2 components in the output voltage, using a modulation index of less
than − 1. As mentioned earlier, the SqZSI topology is capable of gener­
ating voltages greater than − 1 pu; thus the values of the DC component,
as well as the second harmonic component, are reduced. In fact, in the
PR-based method, the PWM reference waveform moves away from a
pure sine waveform, which optimally and automatically includes har­
monics and DC offset to minimize the existing sine error and to achieve
the desired pure sine voltage at the output.
As KPR_i increases, the sinusoidal error decreases but becomes closer
to the instability region. Also, the increase in KPR_p has a direct effect on
reducing DC component and oscillations. Although the PR-based

12
M. Noroozi et al.
Fig. 13. Power quality and performance comparison of proposed compensation methods, (a) Output voltage fundamental component, (b) DC component of VO, (b)
Second-harmonic component of VO, (e) Output voltage THD.
method controls the fundamental harmonic with rapid dynamics and
mitigates the h2 component to a desirable level, it is not able to entirely
eliminate the DC offset.
5.3. Based on the PR + PI controllers
In this method, to improve the PR-based method with achieving the
DC component mitigation, the combined method, including the PR and
PI controllers, is utilized simultaneously. Therefore, the DC component
is extracted recursively by the MAF block, and then the DC offset value is
adjusted to zero by the PI0 controller. The proposed compensation al­
gorithm based on the combination of PR and PI controllers for
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International Journal of Electrical Power and Energy Systems 145 (2023) 108703
fundamental harmonic control and DC component mitigation is shown
in Fig. 8.
5.4. Based on the modified modulation
The presence of the parasitic elements, the lower negative peak
compared to the positive peak and the slower system response speed in
the negative area cause the unwanted generation of the DC and h2
components. To overcome the above issues, a compensation method
based on a modified modulation waveform is proposed. The pulse gen­
eration process in this approach is presented in Fig. 9. In this method, a
negative DC offset is intentionally generated in the output voltage to
M. Noroozi et al. International Journal of Electrical Power and Energy Systems 145 (2023) 108703

Fig. 14. Output voltage frequency spectrums based on h1 = 65 V (100%) via simulation for all compensation methods.

component is extracted recursively by the MAF block, and then the DC

Table 3 offset value is adjusted to zero by the PI0 controller, which generates α
Power quality comparison of the proposed compensation methods obtained by coefficient between 0 and 10%. Finally, depending on whether it is in
simulation results.
the positive or negative area of the sine waveform, the original or
Control method PO DCV h1 h2 h3 h4 THDV modified waveform is applied as Vref. The operation principle in this
Open-loop 45 1% 68 1.76% 0.44% 0.02% 2.5% compensation method is based on the amount of the output voltage DC
W V offset; therefore, the extracted DC offset value, which is a positive value,
Open-loop 90 2% 65 3.71% 0.77% 0.08% 4.2% enters directly into the PI0 controller, then a positive value between
W V
0 and 10% is selected for the α coefficient. The higher the output voltage
PI-based 90 0% 65 0.53% 1% 0.02% 1.4%
W V DC offset, the higher the α coefficient is chosen to compensate. For
PR-based 90 0.71% 65 0.48% 0.1% 0.03% 1.1% instance, the modified reference waveform for α = 10% is shown in
W V Fig. 9.
PR + PIdc based 90 0% 65 0.48% 0.1% 0.03% 1.1%
W V
Modified 90 0% 65 2.25% 0.93% 0.48% 3.1%
Modulation W V

neutralize the effect of the undesirable positive DC component. Since the Table 5
SqZSI topology can generate voltages greater than − 1 pu, the negative Parameters for the designed single-phase SqZSI.
area of the sine reference waveform is gained by a coefficient (1 + α). Parameter Value
Moreover, the applied gain increases the system response speed in the Input DC voltage 75 V
negative area, which will indirectly reduce the second harmonic Fsw 20 kHz
component. Also, the positive area of the sine waveform is the same as FO 50 Hz
before, and only the negative area increases with the coefficient when VO(RMS) 45 V
IO(RMS) 2A
required. PO 90 W
The proposed compensation algorithm based on the modified L1, L2 1 mH
modulating waveform for DC elimination and second harmonic miti­ rL 200 mΩ
gation in single-phase SqZSI is shown in Fig. 10. The modulation index C1, C2 4.7 µF,400 V (MLCC type)
S1, S2 MOSFET(IRFP460A, 500 V & 20A)
M is adjusted by PI1, and unlike other proposed methods, it is allowed to
R 25 Ω
increase its maximum value in this method (i.e. M = 100%). The DC

Table 4
Qualitative comparison of all proposed compensation methods performance.
Proposed Method DC THD Change in Compensation Maximum use of modulation index Controllers Computational
elimination reduction h3 speed range complexity burden

PI-based High Medium Increase Slow Low Simple High(2DFTs +

1AVG)
PR-based Medium High Decrease Fast Low medium Low (No filters)
PR + PIdc based High High Decrease Medium Low medium Medium (1AVG)
Modified High Low Increase Medium High Simple Medium (1AVG)
modulation

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M. Noroozi et al. International Journal of Electrical Power and Energy Systems 145 (2023) 108703

Fig. 15. (a) Experimental setup of the 90 W single-phase SqZSI, (b) Subsystems
of setup, (c) Main components of SqZSI inverter, (d) Variable resistive load and
load change switch.

6. Simulation results

6.1. Load step-change in open-loop control

Simulations have been done in MATLAB/Simulink and PLECS soft­

ware. Simulation and experimental parameters for the designed single-
phase SqZSI are listed in Table 5. At t = 0.1 s, a load step-change from
half power to full power (load resistance from 52 Ω to 24 Ω) at constant
modulation index M = 0.95% has been simulated in open-loop control,
which its results are shown in Fig. 11. The increase in the frequency
spectrum and output voltage THD at the half and full power loads are Fig. 16. (a) Experimental results of the proposed compensation methods along
observed. It is also observed that the significant portion of the harmonic with results obtained from Power Analyzer, (b) Comparison of output voltage
spectrum is related to the second harmonic (~4%) and the DC (~2%) frequency spectrums based on h1 = 65 V (100%) for all compensation methods.
components; therefore, in the following, the simulation results of the
proposed compensation methods are presented. In all frequency spec­
trums and curves in this paper, the values of DC and h2 components are

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M. Noroozi et al. International Journal of Electrical Power and Energy Systems 145 (2023) 108703

Table 6 related constraints, with trial and error. It can be concluded that a
Power quality comparison of the proposed compensation methods by experi­ desirable stable control in the simulation and practice is achievable.
mental results. More detailed results about the power quality and performance
Control method PO DCV h1 h2 THDV THD comparison of proposed compensation methods are illustrated together
reduction in Fig. 13. The performance of the methods is comparable regarding
Open-loop 48.12 1% 66.5 2.6% 2.84% 44% oscillations and dynamics of responses. Also, for better realization, the
W V frequency spectrums of the output voltage at 90 W, and the output
Open-loop 89.42 2.2% 64 V 4.9% 5.09% Base voltage THD obtained by simulation results are depicted together in
W
Fig. 14; therefore, the reduction of components is evident. Moreover, the
PI-based 88.71 0.004% 64 V 0.9% 1.59% 69%
W power quality parameters of the methods obtained by simulation results
PR-based 88.3 W 1.1% 64 V 0.7% 1.38% 73% are compared in Table 3. Finally, to summarize, the qualitative com­
PR + PIdc based 89.63 0.05% 64 V 0.7% 1.27% 75% parison of all proposed compensation methods performance from
W different points of view is analyzed in Table 4.
Modified 89.79 − 0.4% 64 V 3.7% 3.89% 24%
Modulation W
7. Experimental results

expressed as percentages, which are calculated relative to the funda­
mental harmonic amplitude.
6.2. Simulation results of the proposed compensation methods
For better comparison, in All simulations, the proposed compensa­
tion method starts at t = 0.1 s, and the open-loop condition changes to
the closed-loop control at that moment. Also, the initial modulation
index has been set to M = 0.95% for 90 W resistive load. Simulation
results of the four proposed compensation methods along with the
generated reference waveforms for each approach are illustrated in
Fig. 12. Also, all designed controller gains used in this paper are listed in
Table 2. According to [41–43,55], it should be mentioned that the
controller gains presented in Table 2 are obtained by considering the
7.1. Design procedure of experimental set-up
Inverter governing equations (4), (5), and (6) are used for design
procedures and selecting the main components [11,7]. The maximum
components stress happens when d = 2/3, and at this operation point,
the peak voltage on switches is about three times the input voltage
(about 225 V); so S1 and S2 are selected from 500 V (IRFP460A) MOS­
FETs. Also, inductor current stress is twice the peak value of output
current. The peak value of output is 3A, and the maximum inductor
current is about 6A. Assuming that the inductor current ripple is about
30% of the maximum inductor current and the switching frequency is
20 kHz, according to (6), the inductor’s inductance is almost 1 mH. Also,
peak voltage on capacitor C1 is about twice the input voltage (about 150

Fig. 17. Curves of the efficiency, THD, DC, and h2 components of VO in open-loop experimental measurements.

Table 7
The performance comparison between the implemented SqZSI based on the proposed method and the other SqZSIs.
Control method Open loop control without compensation Closed-loop control with compensation (PR + PI)

Reference SqZSI in [7] SqZSI in [10] SqZSI in [7] SqZSI in thispaper SqZSI in thispaper SqZSI in this paper
(half power) (full power) (full power)

PO 40 W 47 W 200 W 48 W 90 W 90 W
IO (RMS) 1.4 A 1.3 A 1.8 A 1A 2A 2A
Vin (DC) 40 V 50 V 160 V 75 V 75 V 75 V
VO(RMS) 28 V 36 V 110 V 47 V 45 V 45 V
Fsw (kHz) 50 kHz 50 kHz 20 kHz 20 kHz 20 kHz 20 kHz
η 90.4% 94.9% 93.5% 95.3% 94.4% 94.4%
DC offset # # # 1% 2.2% 0.05%
THDV # 4.5% # 2.8% 5% 1.27%

# Not mentioned.

16
M. Noroozi et al.
V); then, the C1 is selected with a higher margin, from the 400 V MLCC
type capacitor. According to (5), if the capacitance of 4.7 µF is selected,
the capacitor voltage ripple is limited to 13% of the capacitor voltage.
Table 5 shows the main components chosen for the designed SqZSI. The
output capacitor C2 can be designed using a similar procedure, which is
also 4.7 μF. To decrease the ac resistance of inductors and well perfor­
mance at 20 kHz switching frequency, the inductors have been wound in
the litz-form [56,57]. The equivalent series DC resistance of the imple­
mented inductors was obtained at about 200 mΩ. Fig. 15c shows the
main components of SqZSI with a rated power of 90 W.
The experimental setup for 90 W single-phase SqZSI is shown in
Fig. 15. This setup consists of three main parts. The first part is the
inverter power circuit, the second part is the voltage and current sensors
circuit for data acquisition and the third part is the STM32F407 mi­
crocontroller board. The ARM microcontroller is responsible for pro­
cessing input data such as ADC unit, applying nonlinear sinusoidal PWM
(NLSPWM) at 20 kHz, and other digital processing. The execution time
of each cycle on the processor is set to 100 us, and all processing oper­
ations in one cycle must be executed in less than 100 us.
7.2. Experimental validation
For experimental validation, several experiments similar to the
simulations have been performed for each proposed method. The output
voltage, output current, and the experimental results obtained by the
Infratek 31 power analyzer are depicted in Fig. 16a. The THD of output
voltage and other parameters have been marked on each picture of the
experimental results. Also, for better realization, the output voltage
frequency spectrums under 90 W resistive loads with the output voltage
THD are depicted in Fig. 16b. The reduction in the undesirable com­
ponents and THDV is evident compared to the open-loop condition.
Moreover, similar to the simulation results section, the power quality
parameters of the methods obtained by experimental results are
compared in Table 6. The open-loop control at 90 W was considered as a
base, and all parameters are normalized to the base condition; for
instance, the percentage of THD reduction for each proposed method
compared to the base condition is also presented. The THD increases by
increasing the load power from half to the nominal in the open-loop
control (i.e. without compensation). It can also be observed that
maximum THD reduction has been achieved by the PR + PI compen­
sation method.
8. Discussion
The efficiency curve of the designed single-phase SqZSI with the
curves of THD, DC, and h2 components of VO are displayed together in
Fig. 17. These curves have been obtained in open-loop experimental
measurements without any compensation algorithm.
Finally, the performance comparison of the designed SqZSI with the
other SqZSIs is presented in Table 7. The performance specifications
such as output voltage, THD, and efficiency of the implemented SqZSI
are compared to the inverters available in the references. It can be
observed that the amount of the DC component is not well addressed in
the references. Moreover, with the proposed compensation method, the
amount of THD has been significantly reduced, and the amount of DC
component has been eliminated in this paper.
9. Conclusion
In this paper, four compensation methods have been proposed to
mitigate the second harmonic and eliminate the DC component in the
single-phase semi-quasi-Z-source inverter. These methods improve the
power quality characteristics of this inverter just by modifying the
modulation reference waveform, without adding any physical compo­
nent. Based on the quantitative and qualitative analyzes of the methods
presented in the paper, it can be concluded that:
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International Journal of Electrical Power and Energy Systems 145 (2023) 108703
• The PR + PI method has the best performance in THD reduction
(75%) and finest compensation characteristics, while the PR method
has the fastest performance when it comes to compensation process.
• Although the PI-based method has a relatively appropriate perfor­
mance, lower compensation speed and higher computational burden
considered as drawbacks of this method.
• While the modified modulation method is simple and provides
maximum use of modulation index range, it has more unsatisfactory
performance than the others.
Finally, several tests were performed on the 90 W designed SqZSI and
the obtained results demonstrate that the simulation outputs and the
experimental results are compatible for different load levels. To sum up,
the obtained results confirm the best performance and the favorable
effect of the proposed methods in improving the power quality of the
SqZSI, achieving 1.27% THD of output voltage and eliminating DC
component injection at full power, as well.
CRediT authorship contribution statement
Meraj Noroozi: Methodology, Software, Validation, Writing – re­
view & editing. Farhad Haghjoo: Supervision, Visualization. Hamid
Javadi: Supervision, Visualization. Mohammad Reza Zolghadri: Re­
sources, Visualization.
Declaration of Competing Interest
The authors declare that they have no known competing financial
interests or personal relationships that could have appeared to influence
the work reported in this paper.
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